DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/20/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-11, 16-17, 19, 35-36 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2020/0176468 A1 (Herner).
Re claims 1 and 35 and 36, Herner teaches a NOR-type memory device (memory structure 10), comprising:
a plurality of device layers (active layers 310, 320 etc. including dielectric portions 140/130, in Fig. 23 there are 4 stacks of 2 bits each in a staircase pattern) disposed on a substrate, wherein each of the plurality of device layers comprises a stack of a first source/drain layer (source or drain layer 70 of stack 320), a first channel layer (semiconductor layer 120 of stack 320), and a second source/drain layer (source or drain layer 50 of stack 320) (Fig. 17); and
a gate stack (gate stack including layers 200/210/220/240) that extends vertically with respect to the substrate to pass through the stack in the each of the plurality of device layers,
wherein the gate stack comprises a gate conductor layer (gate layer 240) and a memory functional layer (charge storage layer 210) disposed between the gate conductor layer and the stack, and a memory cell is defined at an intersection of the gate stack and the stack, wherein the stack surrounds a periphery of the gate stack (the stack includes dielectric portions 140/130 therefore the entirety of the stack surrounds the gate stack) (Figs. 1-24);
wherein the stack of at least one of the plurality of device layers further comprises a second channel layer (semiconductor layer 120 of stack 310) and a third source/drain layer (source or drain layer 50 in stack 310), and two memory cells stacked with each other are defined at the intersection of the gate stack and the stack (the top stack comprising 310 and 320 define two memory cells wherein the bit is stored in the gate and selected by the transistor structure as is nominal in 3D EEPROM), and
wherein the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer and the third source/drain layer, which are comprised in the stack, are stacked in sequence from bottom to top, and adjacent layers in the stack are in direct contact with each other (Figs. 17-23);
an electronic apparatus comprising the NOR-type memory device according to claim 1 (claim 35);
wherein the electronic apparatus comprises a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply (claim 36) (Flash memory is used in computers).
PNG
media_image1.png
593
538
media_image1.png
Greyscale
PNG
media_image2.png
791
549
media_image2.png
Greyscale
Re claim 3, Herner teaches wherein the memory functional layer comprises at least one of a charge trapping material or a ferroelectric material (charge storage layer 210 [0033]).
Re claim 4, Herner teaches wherein the stack comprises a single crystal semiconductor material ([0020] while Herner does not explicitly state that the semiconductor layers are single crystal Examiner takes Official Notice that single crystal semiconductor is used for deposited active layers in stacked 3D memory due to the reduced thickness of these layers, the deposition types listed).
Re claim 5, Herner teaches wherein an isolation layer is disposed between at least one pair of adjacent device layers among the plurality of device layers (hard mask layer 30 [0020]).
Re claim 6, Herner teaches wherein a bit line (bit lines are connected at the top of each of conductive material 400 Fig. 24) that is electrically connected to a source/drain layer adjacent to the isolation layer in a device layer above the isolation layer is different from a bit line that is electrically connected to a source/drain layer adjacent to the isolation layer in a device layer below the isolation layer.
PNG
media_image3.png
595
509
media_image3.png
Greyscale
Re claim 7, Herner teaches wherein the memory functional layer is formed on a bottom surface of the gate conductor layer and a sidewall of the gate conductor layer (charge storage layer 210 is formed conformally in the trenches thus meeting this relative requirement Fig. 18).
PNG
media_image2.png
791
549
media_image2.png
Greyscale
Re claim 8, Herner teaches wherein the NOR-type memory device comprises a plurality of gate stacks disposed in an array (Figs. 1-24).
Re claim 9, Herner teaches wherein the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer, and the third source/drain layer comprise the same semiconductor material, wherein a doping concentration interface is provided between adjacent layers (Examiner takes official notice that enhancement mode field effect transistors of Herner are formed of NPN or PNP structures).
Re claim 10, Herner teaches further comprising:
a first bit line and a second bit line (separate bit lines are connected to the transistors in each vertical line of stacked memory FETs) that is different from the first bit line;
a source line;
a first contact portion to the first source/drain layer (vertical conductive portion 400);
a second contact portion to the second source/drain layer (vertical conductive portion 400); and
a third contact portion to the third source/drain layer (vertical conductive portion 400), wherein the first contact portion and the third contact portion are electrically connected to the first bit line and the second bit line respectively, and
the second contact portion is electrically connected to the source line (NOR circuitry requires two transistors in each cell which share connection to the same bit line and the common source line and each string is connected to a different bit line to form the array [0037] Fig. 24).
Re claim 11, Herner teaches further comprising: a fourth contact portion (portion of channel layers 120 in contact with layer 60. The claim language merely requires a portion of something in contact with the channel layers.) to the first channel layer; and a fifth contact portion to the second channel layer.
Re claim 16, Herner teaches wherein the substrate comprises a device region and a contact region adjacent to the device region, the memory cell is formed on the device region, and the contact portions are formed on the contact region (Fig. 24).
Re claim 17, Herner teaches the first source/drain layer, the first channel layer, the second source/drain layer, the second channel layer, and the third source/drain layer in each of the plurality of device layers form a step structure in the contact region (Fig. 24 the claim does not require a contact on each region and the staircase structure of Herner exposes the input/output terminals of each transistor).
Re claim 19, Herner teaches further comprising: a word line; and a sixth contact portion to the gate conductor layer, wherein the sixth contact portion is electrically connected to the word line (word lines 230 Fig. 18).
PNG
media_image2.png
791
549
media_image2.png
Greyscale
Response to Arguments
Applicant's arguments filed 7/20/2026 have been fully considered but they are not persuasive. Applicant’s arguments relate to the assertion that the claim requires that the first source/drain region, first channel, second source/drain region, second channel and third source/drain region are in direct contact with each other in the stack from bottom to top such that there are no intervening layers. However, the claim is not written in such a way as to require this. The claim uses “comprising” when referring to the constituents of the device layers which is an open term allowing for other unclaimed layers to be present. Additionally, the final clause states “adjacent layers in the stack are in direct contact with each other”. All adjacent layers in the stack of the prior art are in direct contact with each other and includes the hard mask and isolation layers between memory cell portions. If Applicant believes that the crux of the invention lies in the shared source/drain region between two adjacent memory transistors in the stack thus having no additional layers between the second channel and second source/drain layer then this should be positively claimed either by using “consisting of” language in the description of the layers of the stack or by expressly claiming that the named layers are in direct physical contact with each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Prosecution Insights