DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grötsch (US 2019/0207071 A1).
With respect to claim 1, Grötsch discloses, in Figs.1-25, a semiconductor device, comprising: a substrate (270) having a pixel region in which a plurality of pixels (211) is arranged; and one or more chips flip-chip (211) bonded to the substrate (270) via a connection terminal (219) (see Par.[0174]-[0177] wherein a construction comparable to that of the component 202 comprising six surface-emitting semiconductor chips 211 arranged on a carrier 270; like the semiconductor chips 210, the semiconductor chips 211 each comprise a non-radiation-transmissive chip substrate 215 and, arranged thereon, a semiconductor layer sequence 220 for generating radiation; via the contacts 219, the semiconductor chips 211 electrically and mechanically connect to mating contacts of the carrier 270, wherein a connection may be produced via an electrically conductive connection medium such as, for example, a solder or an electrically conductive adhesive (not illustrated in each case); see Par.[0084] wherein the at least one semiconductor layer sequence of the radiation source may be part of a radiation-emitting semiconductor chip, for example, a light-emitting diode chip LED chip ( i.e.; LED can be pixel or part of pixel); see Par.[0131] wherein the component 102/202 comprises a single LED chip 111/211 in the form of a volume-emitting flip-chip, the LED chip being arranged on a carrier substrate 170/270), wherein, for each chip (211), a material of a first resin (250) provided in contact with a back surface of the chip (211) is different from a material of a second resin (260) provided in contact with a side surface of the chip (211) and overlapping a top corner portion of the first resin (250) at an edge between the back surface and the side surface of the chip (211) (see Par.[0150] wherein the radiation-transmissive material 250 may be a silicone resin material, for example; see Par.[0155] wherein the plastics material 260 may be, for example, a silicone material comprising particles of TiO.sub.2 resin embedded therein; moreover, the plastics material 260 may be applied on the carrier substrate 270, for example, by potting or carrying out a molding process).
With respect to claim 2, Grötsch discloses, in Figs.1-25, he semiconductor device, wherein the second resin (260) is formed on a side surface of the chip (211) on a side of the pixel region.
With respect to claim 3, Grötsch discloses, in Figs.1-25, the semiconductor device, wherein the second resin (260) is also formed at a corner between the side surface of the chip (211) on the side of the pixel region and an upper surface of the chip (211).
With respect to claim 4, Grötsch discloses, in Figs.1-25, the semiconductor device, wherein a height of the second resin (260) formed on the side surface of the chip (211) is larger than a height of the first resin (250) that protects the back surface of the chip.
With respect to claim 12, Grötsch discloses, in Figs.1-25, the semiconductor device, wherein a plurality of chips is flip-chip bonded to the substrate via connection terminals.
With respect to claim 13, Grötsch discloses, in Figs.1-25, a method of producing a semiconductor device, comprising: flip-chip (211) bonding, via a connection terminal (219), a chip to a substrate (270) having a pixel region in which a plurality of pixels is arranged; and coating a side surface of the chip using a second resin (260) that is a material different from a first resin (250) that protects a back surface of the chip (270) such that the second resin (260) overlaps a top corner portion of the first resin (250) at an edge between the back surface and the side surface of the chip (210) (see Par.[0174]-[0177] wherein a construction comparable to that of the component 202 comprising six surface-emitting semiconductor chips 211 arranged on a carrier 270; like the semiconductor chips 210, the semiconductor chips 211 each comprise a non-radiation-transmissive chip substrate 215 and, arranged thereon, a semiconductor layer sequence 220 for generating radiation; via the contacts 219, the semiconductor chips 211 electrically and mechanically connect to mating contacts of the carrier 270, wherein a connection may be produced via an electrically conductive connection medium such as, for example, a solder or an electrically conductive adhesive (not illustrated in each case); see Par.[0084] wherein the at least one semiconductor layer sequence of the radiation source may be part of a radiation-emitting semiconductor chip, for example, a light-emitting diode chip LED chip ( i.e.; LED can be pixel or part of pixel); see Par.[0131] wherein the component 102/202 comprises a single LED chip 111/211 in the form of a volume-emitting flip-chip, the LED chip being arranged on a carrier substrate 170/270; see Par.[0150] wherein the radiation-transmissive material 250 may be a silicone resin material, for example; see Par.[0155] wherein the plastics material 260 may be, for example, a silicone material comprising particles of TiO.sub.2 resin embedded therein; moreover, the plastics material 260 may be applied on the carrier substrate 270, for example, by potting or carrying out a molding process).
With respect to claim 14, Grötsch discloses, in Figs.1-25, the method of producing a semiconductor device, further comprising attaching the first resin to the back surface of the chip and then flip-chip bonding the chip to the substrate.
Claims 1-4, 7-14, 16, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon et al. (US 2018/01 75268 A1 hereinafter referred to as “Moon’).
With respect to claim 1, Moon discloses, in Figs.1-7, a semiconductor device, comprising: a substrate (100) having a pixel region (SP) in which a plurality of pixels (AE) is arranged (see Par.[0088]- [0089] wherein the light emitting diode display apparatus according to this example includes a plurality of pixels SP, a first planarization layer 110, a light emitting diode chip 300, a pixel electrode AE, and a common electrode CE; each of the plurality of pixels SP includes a pixel circuit PC that includes a driving thin film transistor T2 provided on the first substrate 100); and one or more chips flip-chip (EL) bonded to the substrate (100) via a connection terminal (E1-E2), wherein, for each chip, a material of a first resin (315) provided in contact with a back surface of the chip (EL) is different from a material of a second resin (160) provided in contact with a side surface of the chip (EL) and overlapping a top corner portion of the resin at an edge between the back surface and the side surface of the chip (see Par.[0068]-[0069] wherein the emission layer EL according to one example includes a first semiconductor layer 320, an active layer 330, and a second semiconductor layer 350; see Figs.4-5, wherein chip EL are flip bonded to substrate 100; see Par.[0113]-[0115] wherein the encapsulation layer 160 is coated on the first substrate 100 that includes the pixel SP and the light emitting diode chip 300, thereby protecting the pixel SP and the light emitting diode chip 300, which are provided in the first substrate 100; the encapsulation layer 160 according to one example may be, but not limited to, an optical clear adhesive (OCA) or an optical clear resin (OCR); see Par.[0077] wherein the insulating layer 315 is provided on the semiconductor substrate 310 to surround a front surface and a side of each of the first and second light emitting diodes D1 and D2, thereby electrically insulating the first and second light emitting diodes D1 and D2 from each other and preventing damage from external impact from occurring; the insulating layer 315 according to one example may be made of an inorganic material such as SiOx and SiNx, or may be made of an organic material such as benzocyclobutene or photo acryl).
Moreover, regarding the limitation “flip-chip bonded to a substrate” refers to a specific method step of bonding the chip, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Moon. Therefore, the said claimed limitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 2, Moon discloses, in Figs.1-7, the semiconductor device, wherein the second resin (315) is formed on a side surface of the chip (EL) on a side of the pixel region (AE/SP) (for example, see Fig.6).
With respect to claim 3, Moon discloses, in Figs.1-7, the semiconductor device, wherein the second resin (160) is also formed at a corner between the side surface of the chip (EL) on the side of the pixel region and an upper surface of the chip.
With respect to claim 4, Moon discloses, in Figs.1-7, the semiconductor device, wherein a height of the second resin (815) formed on the side surface of the chip (EL) is larger than a height of the first resin (315) that protects the back surface of the chip.
With respect to claim 7, Moon discloses, in Figs.1-7, the semiconductor device, further comprising an underfill resin/(portion or resins under the chips EL) that protects the connection terminal (E1-E2) between the substrate (100) and the chip (EL), wherein the substrate (100) includes a first resin dam (160) configured to prevent outflow of the underfill resin and a second resin dam (160) for configured to prevent outflow of the second resin (see Figs.5-6 wherein portion of material 160 within substrate).
With respect to claim 8, Moon discloses, in Figs.1-7, the semiconductor device, wherein each of the first resin dam and the second resin dam has a rectangular planar shape.
With respect to claim 9, Moon discloses, in Figs.1-7, the semiconductor device, wherein the first resin dam has a rectangular plane shape, and the second resin dam has a planar shape of a U-shaped planar shape in which a side opposite to a side adjacent the pixel region, of four sides corresponding to a rectangular outline of the chip.
With respect to claim 10, Moon discloses, in Figs.1-7, the semiconductor device, wherein the first resin dam has a rectangular plane shape, and the second resin dam has a planar shape of an I-shaped planar shape formed only alongside adjacent to the pixel region among, four sides corresponding to a rectangular outline of the chip.
With respect to claim 11, Moon discloses, in Figs.1-7, the semiconductor device, wherein the first resin dam has a planar shape in which a portion a side the pixel region, among four sides corresponding to the rectangular outline of the chip.
With respect to claim 12, Moon discloses, in Figs.1-7, the semiconductor device, wherein a plurality of chips is flip-chip bonded to the substrate via connection terminals.
With respect to claim 13, Moon discloses, in Figs.1-7, a method of producing a semiconductor device, comprising: flip-chip (EL) bonding, via a connection terminal (E1, E2), a chip (EL) to a substrate (100) having a pixel region (SP) in which a plurality of pixels is arranged (see Par.[0088]-[0089] wherein the light emitting diode display apparatus according to this example includes a plurality of pixels SP, a first planarization layer 110, a light emitting diode chip 300, a pixel electrode AE, and a common electrode CE; each of the plurality of pixels SP includes a pixel circuit PC that includes a driving thin film transistor T2 provided on the first substrate 100); and coating a side surface of the chip (EL) using a second resin (160) that is a material different from a first resin (315) that protects a back surface of the chip such that the second resin (160) overlaps a top corner portion of the first resin (315) at an edge between the back surface and the side surface of the chip (see Par.[0068]-[0069] wherein the emission layer EL according to one example includes a first semiconductor layer 320, an active layer 330, and a second semiconductor layer 350; see Figs.4-5, wherein chip EL are flip bonded to substrate 100; see Par.[0113]-[0115] wherein the encapsulation layer 160 is coated on the first substrate 100 that includes the pixel SP and the light emitting diode chip 300, thereby protecting the pixel SP and the light emitting diode chip 300, which are provided in the first substrate 100; the encapsulation layer 160 according to one example may be, but not limited to, an optical clear adhesive (OCA) or an optical clear resin (OCR); see Par.[0077] wherein the insulating layer 315 is provided on the semiconductor substrate 310 to surround a front surface and a side of each of the first and second light emitting diodes D1 and D2, thereby electrically insulating the first and second light emitting diodes D1 and D2 from each other and preventing damage from external impact from occurring; the insulating layer 315 according to one example may be made of an inorganic material such as SiOx and SiNx, or may be made of an organic material such as benzocyclobutene or photo acryl; see Par.[0067] wherein the semiconductor substrate 310 has uniform light transmittance).
With respect to claim 14, Moon discloses, in Figs.1-7, the method of producing a semiconductor device, further comprising attaching the first resin (810) to the back surface of the chip and then flip-chip bonding the chip to the substrate (100) (see steps of Figs.5-6).
With respect to claim 16, Moon discloses, in Figs.1-7, the method of producing a semiconductor device, further comprising attaching a tape-type resin material as the first resin (160) and then curing the tape-type resin material (see Par.[0115] wherein the encapsulation layer 160 according to one example may be made of heat and/or optical hardening resin, may be coated on the first substrate 100 in a liquid state and then hardened by a hardening process based on heat and/or light).
With respect to claim 18, Moon discloses, in Figs.1-7, the method of producing a semiconductor device, wherein the substrate includes a first resin dam for damming outflow of an underfill resin that protects the connection terminal and a second resin dam for damming outflow of the second resin, the first resin dam has a planar shape in which a portion of a side adjacent to the pixel region, located outside a rectangular outline of the chip, is recessed toward the chip, and a needle position of the underfill resin is set in a space having no recess of the first resin dam outside the chip in a longitudinal direction (see Figs.5-6 wherein portion of material 160 within substrate).
Moreover, regarding the limitation “is recessed” refers to a specific method step of bonding the chip, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Moon. Therefore, the said claimed limitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 12-13, 15, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iguchi (US 2018/0358339 A1 hereinafter referred to as “Iguchi’) in view of Grötsch (US 2019/0207071 A1).
With respect to claim 1, Iguchi discloses, in Figs.1-25, a semiconductor device, comprising: a substrate (200) having a pixel region (100) in which a plurality of pixels (3) is arranged (see Par.[0111] wherein an N-well layer 202, a shallow trench isolation (STI) layer 203, and N+ diffusion layers 204a and 204b are formed on the P-well layer 201 of the silicon substrate 200; see Par.[0089]-[0093] wherein the pixel drive circuit 100 drives the pixel 3 (I, J) to emit light by supplying the drive current 54 to the blue LED chip 50 of the pixel 3 (I, J) in the I-th row selected by the row selection circuit 4 according to a signal output from the column signal output circuit 5); and one or more chips flip-chip (70) bonded to the substrate (200) via a connection terminal (40-41), wherein, for each chip, a material of a first resin (62) provided in contact with a back surface of the chip (70) is different from a material of a second resin (61) provided in contact with a side surface of the chip (70) and overlapping a top corner portion of the first resin at an edge between the back surface and the side surface of the chip (see Par.[0006] wherein as an example of a technique in the related art of the present invention, in addition, an example in which a pixel is configured with an LED chip including a cathode and an anode provided on one side of the LED chip; that is, so-called flip chip connection is applied to an LED display; see Par.[0162]-[0163] wherein each of light emitting elements 11, 12, and 13 of the LED display chips 1R, 1G, and 1B includes a blue-violet LED chip 70 and a wavelength conversion layer 62; see Par.[0165] wherein as illustrated in FIG. 12, a dam layer 61 is provided between adjacent blue-violet LED chips 70, and thus leakage of light transmitting through the wavelength conversion layer 62 is minimized; the dam layer 61 is formed using a material having a high reflection property and a low light absorption property, and is preferably formed using the same material as that of the light-shielding reflection layer 60). However, Iguchi does not explicitly disclose a material of a first resin provided in contact with a back surface of the chip is different from a material of a second resin provided in contact with a side surface of the chip and overlapping a top corner portion of the first resin at an edge between the back surface and the side surface of the chip.
Grötsch discloses, in Figs.1-25, a semiconductor device, comprising: a substrate (270) having a pixel region in which a plurality of pixels (211) is arranged; and one or more chips flip-chip (211) bonded to the substrate (270) via a connection terminal (219) (see Par.[0174]-[0177] wherein a construction comparable to that of the component 202 comprising six surface-emitting semiconductor chips 211 arranged on a carrier 270; like the semiconductor chips 210, the semiconductor chips 211 each comprise a non-radiation-transmissive chip substrate 215 and, arranged thereon, a semiconductor layer sequence 220 for generating radiation; via the contacts 219, the semiconductor chips 211 electrically and mechanically connect to mating contacts of the carrier 270, wherein a connection may be produced via an electrically conductive connection medium such as, for example, a solder or an electrically conductive adhesive (not illustrated in each case); see Par.[0084] wherein the at least one semiconductor layer sequence of the radiation source may be part of a radiation-emitting semiconductor chip, for example, a light-emitting diode chip LED chip ( i.e.; LED can be pixel or part of pixel); see Par.[0131] wherein the component 102/202 comprises a single LED chip 111/211 in the form of a volume-emitting flip-chip, the LED chip being arranged on a carrier substrate 170/270), wherein, for each chip (211), a material of a first resin (250) provided in contact with a back surface of the chip (211) is different from a material of a second resin (260) provided in contact with a side surface of the chip (211) and overlapping a top corner portion of the first resin (250) at an edge between the back surface and the side surface of the chip (211) (see Par.[0150] wherein the radiation-transmissive material 250 may be a silicone resin material, for example; see Par.[0155] wherein the plastics material 260 may be, for example, a silicone material comprising particles of TiO.sub.2 resin embedded therein; moreover, the plastics material 260 may be applied on the carrier substrate 270, for example, by potting or carrying out a molding process).
Iguchi and Grötsch are analogous art because they are all directed to a semiconductor device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Iguchi to include Grötsch because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the chip side surface resin disposition by including covering the chip back surface resin at the corner as taught by Grötsch in order to utilize side or surface regions covered by both resin materials so as of the optical waveguide device not used for optical coupling are configured in reflective fashion thereby an emission of light radiation from the conversion element in the central portion od device with a high luminance may be achieved as a result.
With respect to claim 2, Iguchi discloses, in Figs.1-25, the semiconductor device, wherein the second resin (61) is formed on a side surface of the chip on a side/(upper side surface) of the pixel region (100) (for example, see Fig.12).
With respect to claim 3, Iguchi discloses, in Figs.1-25, the semiconductor device, wherein the second resin (61) is also formed at a corner between the side surface of the chip (70) on the side/(upper side surface) of the pixel region (100) and an upper surface of the chip (70) (for example, see Fig.19A).
With respect to claim 4, Iguchi discloses, in Figs.1-25, the semiconductor device, wherein a height of the second resin (61) formed on the side surface of the chip (70) is larger than a height of the first resin (62) that protects the back surface of the chip (70) (for example, see Fig.19A).
With respect to claim 6, Iguchi discloses, in Figs.1-25, the semiconductor device, wherein the first resin (62) is a material that causes infrared light to be transmitted therethrough (see Par.[01 70] wherein as a red phosphor to be mixed in the wavelength conversion layer 62, various materials, for example, a nitride phosphor such as FOX (Y.sub.20.sub.3:Eu) or CaAlISiN.sub.3, a fluoride phosphor such as KSF, or the like can be used. Among the materials, a KSF phosphor such as K.sub.2(Si.sub.0.99Mn.sub.0.01)F.sub.6 (a manganese-activated fluorinated tetravalent metal salt phosphor), which has a small light emission amount in an infrared region and has a sharp light emission peak in a wavelength region near 600 [nm] to 650 [nm], is advantageous in expanding the color gamut).
With respect to claim 12, Iguchi discloses, in Figs.1-25, the semiconductor device, wherein a plurality of chips is flip-chip bonded to the substrate via connection terminals.
With respect to claim 13, Iguchi discloses, in Figs.1-25, a method of producing a semiconductor device, comprising: flip-chip (70) bonding, via a connection terminal (40-41), a chip to a substrate (200) having a pixel region (100) in which a plurality of pixels is arranged; and coating a side surface of the chip (70) using a second resin (61) that is a material different from a first resin (62) that protects a back surface of the chip (see Par.[0111] wherein an N-well layer 202, a shallow trench isolation (STI) layer 203, and N+ diffusion layers 204a and 204b are formed on the P-well layer 201 of the silicon substrate 200; see Par.[0089]-[0093] wherein the pixel drive circuit 100 drives the pixel 3 (I, J) to emit light by supplying the drive current 54 to the blue LED chip 50 of the pixel 3 (I, J) in the I-th row selected by the row selection circuit 4 according to a signal output from the column signal output circuit 5; see Par.[0006] wherein as an example of a technique in the related art of the present invention, in addition, an example in which a pixel is configured with an LED chip including a cathode and an anode provided on one side of the LED chip; that is, so-called flip chip connection is applied to an LED display; see Par.[0162]-[0163] wherein each of light emitting elements 11, 12, and 13 of the LED display chips 1R, 1G, and 1B includes a blue-violet LED chip 70 and a wavelength conversion layer 62; see Par.[0165] wherein as illustrated in FIG. 12, adam layer 61 is provided between adjacent blue-violet LED chips 70, and thus leakage of light transmitting through the wavelength conversion layer 62 is minimized; the dam layer 61 is formed using a material having a high reflection property and a low light absorption property, and is preferably formed using the same material as that of the light-shielding reflection layer 60). However, Iguchi does not explicitly disclose the second resin overlaps a top corner portion of the first resin at an edge between the back surface and the side surface of the chip.
Grötsch discloses, in Figs.1-25, a method of producing a semiconductor device, comprising: flip-chip (211) bonding, via a connection terminal (219), a chip to a substrate (270) having a pixel region in which a plurality of pixels is arranged; and coating a side surface of the chip using a second resin (260) that is a material different from a first resin (250) that protects a back surface of the chip (270) such that the second resin (260) overlaps a top corner portion of the first resin (250) at an edge between the back surface and the side surface of the chip (210) (see Par.[0174]-[0177] wherein a construction comparable to that of the component 202 comprising six surface-emitting semiconductor chips 211 arranged on a carrier 270; like the semiconductor chips 210, the semiconductor chips 211 each comprise a non-radiation-transmissive chip substrate 215 and, arranged thereon, a semiconductor layer sequence 220 for generating radiation; via the contacts 219, the semiconductor chips 211 electrically and mechanically connect to mating contacts of the carrier 270, wherein a connection may be produced via an electrically conductive connection medium such as, for example, a solder or an electrically conductive adhesive (not illustrated in each case); see Par.[0084] wherein the at least one semiconductor layer sequence of the radiation source may be part of a radiation-emitting semiconductor chip, for example, a light-emitting diode chip LED chip ( i.e.; LED can be pixel or part of pixel); see Par.[0131] wherein the component 102/202 comprises a single LED chip 111/211 in the form of a volume-emitting flip-chip, the LED chip being arranged on a carrier substrate 170/270; see Par.[0150] wherein the radiation-transmissive material 250 may be a silicone resin material, for example; see Par.[0155] wherein the plastics material 260 may be, for example, a silicone material comprising particles of TiO.sub.2 resin embedded therein; moreover, the plastics material 260 may be applied on the carrier substrate 270, for example, by potting or carrying out a molding process).
Iguchi and Grötsch are analogous art because they are all directed to a semiconductor device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Iguchi to include Grötsch because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the chip side surface resin disposition by including covering the chip back surface resin at the corner as taught by Grötsch in order to utilize side or surface regions covered by both resin materials so as of the optical waveguide device not used for optical coupling are configured in reflective fashion thereby an emission of light radiation from the conversion element in the central portion od device with a high luminance may be achieved as a result.
With respect to claim 15, Iguchi discloses, in Figs.1-25, the method of producing a semiconductor device, wherein the first resin (61) is a material that causes infrared light to be transmitted therethrough (see Par.[0165] wherein as illustrated in FIG. 12, adam layer 61 is provided between adjacent blue-violet LED chips 70, and thus leakage of light transmitting through the wavelength conversion layer 62 is minimized; the dam layer 61 is formed using a material having a high reflection property and a low light absorption property, and is preferably formed using the same material as that of the light-shielding reflection layer 60).
With respect to claim 20, Iguchi discloses, in Figs.1-25, an electronic apparatus, comprising: an optical system; a semiconductor device that receives light from the optical system, the semiconductor device comprising: a substrate (200) having a pixel region (100) in which a plurality of pixels (3) is arranged, and one or more chips flip-chip (70) bonded to the substrate (200) via a connection terminal (40-41), wherein, for each chip, a material of a first resin (62) provided in contact with a back surface of the chip (200) is different from a material of a second resin (61) provided in contact with a side surface of the chip (70) and overlapping a top corner portion of the first resin at an edge between the back surface and the side surface of the chip; and a digital signal processor (6) that processes signals (5) received from the semiconductor device (see Par.[0111] wherein an N-well layer 202, a shallow trench isolation (STI) layer 203, and N+ diffusion layers 204a and 204b are formed on the P-well layer 201 of the silicon substrate 200; see Par.[0089]- [0093] wherein the pixel drive circuit 100 drives the pixel 3 (I, J) to emit light by supplying the drive current 54 to the blue LED chip 50 of the pixel 3 (I, J) in the I-th row selected by the row selection circuit 4 according to a signal output from the column signal output circuit 5; see Par.[0006] wherein as an example of a technique in the related art of the present invention, in addition, an example in which a pixel is configured with an LED chip including a cathode and an anode provided on one side of the LED chip; that is, so-called flip chip connection is applied to an LED display; see Par.[0162]-[0163] wherein each of light emitting elements 11, 12, and 13 of the LED display chips 1R, 1G, and 1B includes a blue-violet LED chip 70 and a wavelength conversion layer 62; see Par.[0165] wherein as illustrated in FIG. 12, a dam layer 61 is provided between adjacent blue-violet LED chips 70, and thus leakage of light transmitting through the wavelength conversion layer 62 is minimized; the dam layer 61 is formed using a material having a high reflection property and a low light absorption property, and is preferably formed using the same material as that of the light-shielding reflection layer 60; see Par.[0091]-[0093] wherein the column signal output circuit 5 controls light emission of the pixel 3 (I, J) in the selected i-th row based on the image data. The image processing circuit 6 controls the row selection circuit 4 and the column signal output circuit 5 based on the image data). However, Iguchi does not explicitly disclose a second resin provided in contact with a side surface of the chip and overlapping a top corner portion of the first resin at an edge between the back surface and the side surface of the chip.
Grötsch discloses, in Figs.1-25, a semiconductor device, comprising: a substrate (270) having a pixel region in which a plurality of pixels (211) is arranged; and one or more chips flip-chip (211) bonded to the substrate (270) via a connection terminal (219) (see Par.[0174]-[0177] wherein a construction comparable to that of the component 202 comprising six surface-emitting semiconductor chips 211 arranged on a carrier 270; like the semiconductor chips 210, the semiconductor chips 211 each comprise a non-radiation-transmissive chip substrate 215 and, arranged thereon, a semiconductor layer sequence 220 for generating radiation; via the contacts 219, the semiconductor chips 211 electrically and mechanically connect to mating contacts of the carrier 270, wherein a connection may be produced via an electrically conductive connection medium such as, for example, a solder or an electrically conductive adhesive (not illustrated in each case); see Par.[0084] wherein the at least one semiconductor layer sequence of the radiation source may be part of a radiation-emitting semiconductor chip, for example, a light-emitting diode chip LED chip ( i.e.; LED can be pixel or part of pixel); see Par.[0131] wherein the component 102/202 comprises a single LED chip 111/211 in the form of a volume-emitting flip-chip, the LED chip being arranged on a carrier substrate 170/270), wherein, for each chip (211), a material of a first resin (250) provided in contact with a back surface of the chip (211) is different from a material of a second resin (260) provided in contact with a side surface of the chip (211) and overlapping a top corner portion of the first resin (250) at an edge between the back surface and the side surface of the chip (211) (see Par.[0150] wherein the radiation-transmissive material 250 may be a silicone resin material, for example; see Par.[0155] wherein the plastics material 260 may be, for example, a silicone material comprising particles of TiO.sub.2 resin embedded therein; moreover, the plastics material 260 may be applied on the carrier substrate 270, for example, by potting or carrying out a molding process).
Iguchi and Grötsch are analogous art because they are all directed to a semiconductor device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Iguchi to include Grötsch because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the chip side surface resin disposition by including covering the chip back surface resin at the corner as taught by Grötsch in order to utilize side or surface regions covered by both resin materials so as of the optical waveguide device not used for optical coupling are configured in reflective fashion thereby an emission of light radiation from the conversion element in the central portion od device with a high luminance may be achieved as a result.
Claims 5, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Grötsch in view of Watanabe (US 2010/0133722 A1).
With respect to claim 5, Grötsch discloses all the claimed limitations of claim 1. Moreover, Grötsch does not explicitly disclose the limitations of claim 5.
Watanabe discloses, in Figs.1-3, the semiconductor device, wherein a coefficient of thermal expansion of the first resin (21) is the same as a coefficient of thermal expansion of the chip (8c) (see Par.[0045]-[0046], [0056] wherein the first resin layer 18 having a thermal expansion coefficient nearly equal to that of the wiring motherboard 1 and the second resin layer 21 having a thermal expansion coefficient nearly equal to that of the semiconductor chip 8 form the seal 22).
Grötsch and Watanabe are analogous art because they are all directed to a semiconductor packaging device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Grötsch to include Watanabe because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the material over chip sidewall in Grötsch by including material of thermal expansion coefficient equal to that of the chip as taught by Watanabe in order to utilize the equal thermal expansion between chip and covering material thereof for contraction synchronously occurrence; thus, the mechanical load to the chip due to the thermal expansion and contraction of the covering material itself may generally be ignored, accordingly, the mechanical load to the chip is significantly reduced thereby preventing the package from warping.
With respect to claim 17, Grötsch discloses all the claimed limitations of claim 1. Moreover, Grötsch does not explicitly disclose the limitations of claim 17.
Watanabe discloses, in Figs.1-3, the semiconductor device, wherein a coefficient of thermal expansion of the first resin (21) is the same as a coefficient of thermal expansion of the chip (8c) (see Par.[0045]-[0046], [0056] wherein the first resin layer 18 having a thermal expansion coefficient nearly equal to that of the wiring motherboard 1 and the second resin layer 21 having a thermal expansion coefficient nearly equal to that of the semiconductor chip 8 form the seal 22).
Grötsch and Watanabe are analogous art because they are all directed to a semiconductor packaging device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Grötsch to include Watanabe because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the material over chip sidewall in Grötsch by including material of thermal expansion coefficient equal to that of the chip as taught by Watanabe in order to utilize the equal thermal expansion between chip and covering material thereof for contraction synchronously occurrence; thus, the mechanical load to the chip due to the thermal expansion and contraction of the covering material itself may generally be ignored, accordingly, the mechanical load to the chip is significantly reduced thereby preventing the package from warping.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Sakata et al. (US 2010/0244228 A1 hereinafter referred to as “Sakata”).
With respect to claim 19, Moon discloses all the claimed limitations of claim 13. Moreover, Moon discloses the method of producing a semiconductor device according to claim 13, wherein the substrate includes a first resin dam for damming outflow of an underfill resin that protects the connection terminal and a second resin dam for damming outflow of the second resin. However, Moon does not explicitly disclose that the method further comprising applying the second resin while moving a needle in a line along a side surface of the chip on a side of the pixel region.
Sakata discloses, in Figs.1-29, the method of producing a semiconductor device, the method further comprising applying the second resin while moving a needle in a line along a side surface of the chip on a side of the pixel region (see Par.[0017]-[0018], [0144] wherein specific examples of the shape of the fillet 105 are described with the aid of FIGS. 27A and 27B and FIGS. 28A and 28B. FIGS. 27A and 27B show the shape of a fillet 105 obtained when the underfill resin 104 was injected from one point, and FIGS. 28A and 28B show the shape of a fillet 105 obtained when the injection of the underfill resin 104 was performed while a needle was being moved along one side of the chip 101 the underfill resin 104 is injected, with the position of the needle for injecting the underfill resin 104 fixed at one point (the needle position 111 of FIG. 27B, a portion of the fillet 105 whose center is the needle position 111 becomes a large-sized portion 105a whose size is relatively large; in the fillet 105, a portion other than the needle position 111 and the surrounding portion thereof becomes a small-sized portion 105b whose size is smaller than the large-sized portion 105a).
Moon and Sakata are analogous art because they are all directed to a semiconductor device method, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Moon to include Sakata because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the method of applying chip protective resin in Moon by including applying chip protective resin material while moving needle in line surrounding along entire chip as taught by Sakata in order to utilize the needle direction movement during filling of protective resin so as to mitigate the position of the whole filler outer circumference of the underfill resin that is asymmetrical with reference to the center position and to obtain the injection of the underfill resin that is performed while a needle was being moved along one side of the chip for more cost-effective precision method of underfilling.
Response to Arguments
Applicant’s arguments with respect to claims 1, 13, 20 have been considered but are moot because the current rejection does not rely on the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818