Prosecution Insights
Last updated: August 18, 2026
Application No. 18/043,628

LOW TEMPERATURE BONDING OF MICRODEVICE INTEGRATION INTO A SYSTEM SUBSTRATE

Non-Final OA §102
Filed
Mar 01, 2023
Priority
Sep 02, 2020 — provisional 63/073,594 +3 more
Examiner
JEAN BAPTISTE, WILNER
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
VueReal Inc.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
950 granted / 1098 resolved
+18.5% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
20 currently pending
Career history
1118
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
62.5%
+22.5% vs TC avg
§102
25.1%
-14.9% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1098 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Un-der 37 CFR 1.114 2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/19/2026 has been entered. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claim(s) 1-2, 5-6, 12-14, 50, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Miyazaki US 2006/0214275 A1. Claim 1. Miyazaki discloses a bonding process of a microdevice into a system substrate (such as the one in fig. 3, items 10, 20) where the system substrate has at least one pad (item 13/23) for coupling to the microdevice and a dielectric layer (item 14/24) formed adjacent to the at least one pad, the dielectric layer being configured to bond to a corresponding dielectric on the microdevice, the dielectric layer comprising a shield layer surrounding at least a portion of the at least one pad and configured to limit expansion of the at least one pad during bonding to prevent shorting (this limitation would read through the structure of fig. 3A, as [0035] indicates that while an arrangement of the bumps 23 is configured to present "two rows-three rows-two rows" in FIG. 3A, it is not intended to particularly limit to this arrangement, and a desired arrangement may also be employed as required). Claim 2. Miyazaki discloses the bonding process of claim 1, wherein the dielectric layer is separated from the pads (this limitation would read through the structure of fig. 3A, as [0035], disclosed in the bumps-formed region 12 and 22, the bumps 13 formed in the first semiconductor chip 10 is opposed to the bumps 23 formed in the second semiconductor chip 20). Claim 6. Miyazaki discloses the bonding process of claim 1, wherein a housing structure holds the microdevices and the microdevices have has connections that are formed as microdevice pads (this limitation would read through the structure of fig. 3A, as [0035], disclosed in the bumps-formed region 12 and 22, the bumps 13 formed in the first semiconductor chip 10 is opposed to the bumps 23 formed in the second semiconductor chip 20). Claim 12. Miyazaki discloses the bonding process of claim 1, wherein the at least one pad is heated up at high temperature and under pressure expanding a system substrate pad area (this limitation would read through the structure of fig. 3A, as [0038], disclosed in this case, the penetration of the resin 31 can be accelerated by heating the resin 31 to a temperature for providing a fused condition). Claim 13. Miyazaki discloses the bonding process of claim 1, wherein the dielectric layer is formed before integration of the microdevice (this limitation would read through the structure of fig. 3A, as [0040], disclosed in this case, when air is entrapped in the inside of the opening 16 of the first semiconductor chip 10, the air can also be easily eliminated by a defoaming process before the thermal cure process in the similar way). Claims 5, 14, 50. Miyazaki discloses the bonding process of claim 1, wherein microdevice pads and the at least one pad are in a contact wherein the contact between the microdevice pads and the at least one pad is formed at a temperature below a temperature needed to form an alloy (this limitation would read through the structure of fig. 3A, as [0038], disclosed in this case, the penetration of the resin 31 can be accelerated by heating the resin 31 to a temperature for providing a fused condition). Allowable Subject Matter 5. Claims 7-11, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (A) Claim 7 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the microdevice pads are conductive and are composed of one or more types of material). (B) Since claims 8-11 is/are dependent claim of objected claim (claim 7), They are also objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claim (e.g., claim 7). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Show 3 earlier events
Feb 20, 2026
Final Rejection mailed — §102
Mar 16, 2026
Interview Requested
Apr 01, 2026
Examiner Interview Summary
Apr 01, 2026
Applicant Interview (Telephonic)
Apr 20, 2026
Response after Non-Final Action
May 19, 2026
Request for Continued Examination
May 21, 2026
Response after Non-Final Action
Jun 11, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.1%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1098 resolved cases by this examiner. Grant probability derived from career allowance rate.

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