DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed April 29, 2026. Claim 1 has been amended. No claims have been added. Claims 3 and 7 have been canceled. Currently, claims 1-2, 4-6, and 8-11 are pending.
Applicant’s Amendments to the specification overcome the drawing objections outlined in the previous Office Action. The drawing objections have been withdrawn.
Response to Arguments
Applicant’s arguments, see pages 8-12, filed April 29, 2026, with respect to the rejection of claim 1 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Cao et al. (US 20160163842 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cao et al. (US 20160163842 A1) herein after “Cao” in view of Ando et al. (US 20170092723 A1) herein after “Ando”.
Regarding claim 1, Fig. 9 of Cao discloses a transistor (Fig. 9, “complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor”, ¶ [0001]), comprising:
a substrate (Fig. 9, substrate 10, ¶ [0021]);
a low-dimensional material layer (Fig. 9, nanostructure channel 125, ¶ [0039]) provided above the substrate (10), wherein a material for the low-dimensional material layer (125) comprises at least one selected from carbon nanotubes, silicon nanowires, nanowires of elements of groups II-VI, nanowires of elements of groups III-V, and two-dimensional layered semiconductor materials (“The nanostructure layer 120 may include a nanotube, a nanowire or a combination of these two types of nanomaterials”, “The nanostructure layer 120 employed in the present invention typically includes a Carbon-based nanomaterial”, ¶ [0026] and [0030]);
a gate (Fig. 9, gate electrode 240, ¶ [0044]);
a source (Fig. 9, source/drain region 15, ¶ [0021]), located at a first side of the gate (240);
a drain (15), located at a second side of the gate (240);
a gate dielectric layer (Fig. 9, gate dielectric 230, ¶ [0044]) provided between the gate (240) and the low-dimensional material layer (125);
and spacers (Fig. 9, spacer 220, ¶ [0043]), provided between the source (15) and the gate (240) and between the drain (15) and the gate (240),
wherein the low-dimensional material layer (125) is covered by the gate (240), the gate dielectric layer (230), the source (15), the drain (15) and the spacers (220).
Cao a channel (“hereinafter “nanostructure channel” 125”, ¶ [0039]) of the low-dimensional material layer (125) in a spacer region overlapped by the spacers (220), but fails to disclose wherein dipoles are formed in the spacers to electrostatically dope a channel of the material layer in a spacer region overlapped by the spacers.
In the similar field of endeavor of field effect transistor devices, Fig. 9 of Ando discloses wherein dipoles are formed in the spacers to electrostatically dope a channel of the material layer in a spacer region overlapped by the spacers (“The negative charge (or dipoles) in the inner spacer 232 induces a hole inversion layer 246 in a channel region 244”, ¶ [0055]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the dipole formation as disclosed by Ando, to increase channel quality and carrier mobility (see Ando, ¶ [0055]).
Regarding claim 2, Cao and Ando together disclose the transistor according to claim 1 as applied above, but Cao fails to disclose wherein:
the dipoles are formed at an interface of each of the spacers and the gate dielectric layer; or each of the spacers comprises two sublayers, and the dipoles are formed at an interface of the two sublayers.
In the similar field of endeavor of field effect transistor devices, Figs. 6 and 9 of Ando discloses wherein:
the dipoles are formed at an interface of each of the spacers (Fig. 9, outer spacer 230, inner spacer 232, ¶ [0051]) and the gate dielectric layer (Fig. 6, gate dielectric 210, ¶ [0043]) (“The inner spacer 232 includes the negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 232. The negative charge (or dipoles) in the inner spacer 232 induces a hole inversion layer 246 in a channel region (244) 244 for PFETs”, ¶ [0055]), or
each of the spacers (230, 232) comprises two sublayers (230, 232), and the dipoles are formed at an interface of the two sublayers (230, 232).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the dipole formation as disclosed by Ando, to increase channel quality and carrier mobility (see Ando, ¶ [0055]).
Regarding claim 4, Cao and Ando together disclose the transistor according to claim 1 as applied above, Fig. 9 of Cao further discloses wherein:
a material for the spacers (220) comprises at least one of a high-K dielectric and a low-K dielectric, comprising at least one selected from silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide and aluminum nitride (“the spacers 220 may be made of any insulating material, such as silicon nitride, silicon oxide, silicon oxynitrides, or a combination thereof”, ¶ [0042]); and/or
a material for the gate dielectric layer (230) comprises a high-K dielectric, comprising yttrium oxide.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (US 20160163842 A1) and Ando (US 20170092723 A1) in further view of Datta et al. (US 20090159872 A1) herein after “Datta”.
Regarding claim 5, Cao and Ando together disclose the transistor according to claim 1 as applied above, and Fig. 9 of Cao further discloses wherein the gate dielectric layer (230) is located at a channel region (125) and separates the low-dimensional material layer (125) from the gate (240).
Cao and Ando fail to disclose that the gate dielectric layer separates the low-dimensional material layer from the spacers.
In the similar field of endeavor of carbon nanotube transistors, Fig. 1 of Datta discloses wherein the gate dielectric layer (Fig. 1, high dielectric constant material 18, ¶ [0014]) separates the low-dimensional material layer (Fig. 1, carbon nanotubes 14, ¶ [0014]) from the spacers (Fig. 1, spacers 20, ¶ [0015]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the gate dielectric layer and spacers as disclosed by Datta, to obtain the desired charge transport properties (see Datta, ¶ [0025]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (US 20160163842 A1) and Ando (US 20170092723 A1) in further view of Chi et al. (US 20110260220 A1) herein after “Chi”.
Regarding claim 6, Cao and Ando together disclose the transistor according to claim 1 as applied above, but the combination fails to disclose wherein a gap exists between each of the spacers and the gate.
In the similar field of endeavor of transistors, Fig. 4I of Chi discloses wherein a gap (Fig. 4I, air gap 426, ¶ [0036]) exists between each of the spacers (Fig. 4I, liner layer 412, main spacer 420, ¶ [0034]) and the gate (Fig. 4I, gate electrode layer 406, ¶ [0030]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the gaps as disclosed by Chi, to reduce capacitance between the gate electrode and drain (see Chi, ¶ [0038]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (US 20160163842 A1) and Ando (US 20170092723 A1) in further view of Vasen et al. (US 20200161574 A1) herein after “Vasen”.
Regarding claim 8, Cao and Ando together disclose the transistor according to claim 1 as applied above, but the combination fails to disclose wherein the transistor comprises a plurality of low-dimensional material layers, which are spaced apart from each other by at least the gate, the gate dielectric layer, the source, the drain and the spacers.
In the similar field of endeavor of field effect transistors, Fig. 16 of Vasen discloses wherein the transistor comprises a plurality of low-dimensional material layers (Fig. 16, channel regions 100C of the CNTs, ¶ [0048]), which are spaced apart from each other by at least the gate (Fig. 16, gate structure 101, ¶ [0048]), the gate dielectric layer (Fig. 16, gate dielectric layer 102, ¶ [0048]), the source (Fig. 16, source/drain structure 76, ¶ [0068]), the drain (76) and the spacers (Fig. 16, spacers 44, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the plurality of low-dimensional material layers as disclosed by Vasen, to improve device scaling (see Vasen, ¶ [0021]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cao (US 20160163842 A1) and Ando (US 20170092723 A1) in further view of Chang et al. (US 20140264276 A1) herein after “Chang”.
Regarding claim 9, Cao and Ando together disclose the transistor according to claim 1 as applied above, but the combination fails to disclose comprising:
a second dielectric layer on a surface of the gate away from the gate dielectric layer, wherein:
a ratio of a thickness of the second dielectric layer to a thickness of the gate is in a range of 1:1 to 20:1;
the second dielectric layer comprises at least one selected from silicon nitride and silicon oxide;
and/or the gate comprises at least one selected from TaN, TiN and polycrystalline silicon.
In the similar field of endeavor of field effect transistors, Fig. 10B of Chang discloses comprising:
a second dielectric layer (Fig. 10B, gate cap dielectric 58, ¶ [0068]) on a surface of the gate (Fig. 10B, gate electrode 54, ¶ [0071]) away from the gate dielectric layer (Fig. 10B, gate dielectrics 50, ¶ [0080]), wherein:
a ratio of a thickness of the second dielectric layer (58) to a thickness of the gate (54) is in a range of 1:1 to 20:1 (Fig. 10B, “The thickness of the semiconductor gate electrode material layer, as measured in a planar region, can be from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed”, “The thickness of the gate cap dielectric layer, as measured in a planar region, can be from 50 nm to 300 nm”, ¶ [0068]);
the second dielectric layer (58) comprises at least one selected from silicon nitride and silicon oxide (Fig. 10B, “The gate cap dielectric layer includes a dielectric material layer such as silicon oxide, silicon nitride”, ¶ [0068]); and/or
the gate (54) comprises at least one selected from TaN, TiN and polycrystalline silicon (Fig. 10B, “The semiconductor gate electrode material layer can include a doped semiconductor material such as doped polysilicon”, ¶ [0068]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the second dielectric layer as disclosed by Chang, to protect the stack and gate structure during processing (see Chang, ¶ [0079]).
Regarding claim 10, Cao, Ando and Chang together disclose the transistor according to claim 9 as applied above, but Cao and Ando fails to disclose wherein the thickness of the second dielectric layer is in a range of 100 to 2000 nm, and the thickness of the gate is in a range of 5 to 100 nm.
In the similar field of endeavor of field effect transistors, Fig. 10B of Chang discloses wherein the thickness of the second dielectric layer (58) is in a range of 100 to 2000 nm (Fig. 10B, “The thickness of the gate cap dielectric layer, as measured in a planar region, can be from 50 nm to 300 nm”, ¶ [0068]), and the thickness of the gate (54) is in a range of 5 to 100 nm (Fig. 10B, “The thickness of the semiconductor gate electrode material layer, as measured in a planar region, can be from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed”, ¶ [0068]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the second dielectric layer as disclosed by Chang, to protect the stack and gate structure during processing (see Chang, ¶ [0079]) and/or because it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05, citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (US 20160163842 A1) and Ando (US 20170092723 A1) in further view of Jambunathan et al. (US 20200411691 A1) herein after “Jambunathan”.
Regarding claim 11, Cao, Ando and Chang together disclose the transistor according to claim 9 as applied above, but Cao and Ando fails to disclose wherein:
an orthographic projection of the gate on the substrate is within an orthographic projection of the second dielectric layer on the substrate;
a ratio of a distance between the source and the gate or a distance between the drain and the gate to a length of a channel is in a range of 0.1 to 0.4; and/or
the length of the channel is in a range of 20 nm to 5 µm.
In the similar field of endeavor of field effect transistors, Figs. 5B and 5D of Chang disclose wherein:
an orthographic projection of the gate (54) on the substrate (10) is within an orthographic projection of the second dielectric layer (58) on the substrate (10) (shown in Figs. 5B and 5D).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the second dielectric layer as disclosed by Chang, to protect the stack and gate structure during processing (see Chang, ¶ [0079]).
Chang fails to disclose a ratio of a distance between the source and the gate or a distance between the drain and the gate to a length of a channel is in a range of 0.1 to 0.4; and/or
the length of the channel is in a range of 20 nm to 5 µm.
in the similar field of endeavor of field effect transistors, Fig. 4 of Jambunathan discloses a ratio of a distance between the source (Fig. 4, S/D regions 260, ¶ [0064]) and the gate (Fig. 4, gate electrode 284, ¶ [0068]) or a distance between the drain (260) and the gate (284) to a length of a channel is in a range of 0.1 to 0.4; and/or
the length of the channel is in a range of 20 nm to 5 µm (Fig. 4, “the gate length may be in the range of 3-100 nm”, “the gate length may be the same as or similar to the channel length”, ¶ [0076]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Cao with the channel width as disclosed by Jambunathan, to achieve the desired diffusion properties (see Jambunathan, ¶ [0076]) and/or because it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05, citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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