DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 1-11 in the reply filed on September 19, 2025 is acknowledged.
Claims 12-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 19, 2025.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “510A”, “510B”, “501C’, “520A”, “520B”, and “520C” in Fig. 6.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, and 7 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ando et al. (US 20170092723 A1) herein after “Ando”.
Regarding claim 1, Figs. 6 and 9 of Ando disclose a transistor (Fig. 9, PFET area 216, ¶ [0043]), comprising:
a substrate (Fig. 9, substrate material 202, ¶ [0031]);
a low-dimensional material layer (Fig. 9, semiconductor layer 206, ¶ [0042]) provided above the substrate (202) (Fig. 9, “semiconductor layer 206… may be processed to form… nanowires”, ¶ [0042]);
a gate (Fig. 9, gate structures 220, ¶ [0044]);
a source (Fig. 9, S/D regions 248, ¶ [0054]), located at a first side of the gate (220);
a drain (248), located at a second side of the gate (220);
a gate dielectric layer (Fig. 6, gate dielectric 210, ¶ [0043]) provided between the gate (220) and the low-dimensional material layer (206);
and spacers (Fig. 9, outer spacer 230, inner spacer 232, ¶ [0051]), provided between the source (248) and the gate (220) and between the drain (248) and the gate (220), respectively, wherein dipoles are formed in the spacers (230, 232) to electrostatically dope the low-dimensional material layer (206) (“The inner spacer 232 includes the negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 232. The negative charge (or dipoles) in the inner spacer 232 induces a hole inversion layer 246 in a channel region (244) 244 for PFETs”, ¶ [0055]).
Regarding claim 2, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, and Fig. 9 of Ando further discloses wherein:
the dipoles are formed at an interface of each of the spacers (230, 232) and the gate dielectric layer (210) (“The inner spacer 232 includes the negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 232. The negative charge (or dipoles) in the inner spacer 232 induces a hole inversion layer 246 in a channel region (244) 244 for PFETs”, ¶ [0055]), or
each of the spacers (230, 232) comprises two sublayers (230, 232), and the dipoles are formed at an interface of the two sublayers (230, 232).
Regarding claim 3, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, and Fig. 9 of Ando further discloses wherein a material for the low-dimensional material layer (206) comprises at least one selected from carbon nanotubes, silicon nanowires, nanowires of elements of groups II-VI, nanowires of elements of groups III-V, and two-dimensional layered semiconductor materials (Fig. 9, “The bulk substrate material 202 may include a III-V material while the semiconductor layer 206 may include SiGe, or vice versa”, “semiconductor layer 206… may be processed to form… nanowires”, ¶ [0041-0042]).
Regarding claim 4, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, and Fig. 9 of Ando further discloses wherein:
a material for the spacers (230, 232) comprises at least one of a high-K dielectric and a low-K dielectric, comprising at least one selected from silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide and aluminum nitride (Fig. 9, “The inner PFET spacer may include dielectric materials with a k-value greater than that of SiN (e.g., k≧˜7), Al.sub.2O.sub.3, TiO.sub.2, HfO.sub.2, etc”, ¶ [0023]); and/or
a material for the gate dielectric layer (210) comprises a high-K dielectric, comprising yttrium oxide.
Regarding claim 7, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, and Fig. 9 of Ando further discloses wherein the low-dimensional material layer (206) is covered by the gate (220), the gate dielectric layer (210), the source (248), the drain (248) and the spacers (230, 232).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ando (US 20170092723 A1) in view of Gardner et al. (US 6144071 A) herein after “Gardner”.
Regarding claim 5, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, and Fig. 9 of Ando further discloses wherein the gate dielectric layer (210) is located at a channel region (Fig. 9, channel region 244, ¶ [0055]) and separates the low-dimensional material layer (206) from the gate (220).
Ando discloses that the channel region (244) is in the low-dimensional material layer (206), but fails to disclose that the gate dielectric layer separates the channel region from the spacers.
In the similar field of endeavor of transistors, Fig. 8 of Gardner discloses wherein the gate dielectric layer (Fig. 8, gate dielectric layer 22, cool. 8, lines 44-45) separates the channel region (Fig. 8, region in substrate 20 between regions 21) from the spacers (Fig. 8, spacers 27, col. 10, line 8).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the gate dielectric layer as disclosed by Gardner, to improve production reliability (see Gardner, col. 2, lines 16-20).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ando (US 20170092723 A1) in view of Wu (US 6180988 B1).
Regarding claim 6, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, but Ando fails to disclose wherein a gap exists between each of the spacers and the gate.
In the similar field of endeavor of MOSFETS, Figs. 6 and 8 of Wu discloses wherein a gap (Fig. 8, air gaps 22, col. 4, line 17) exists between each of the spacers (Fig. 6, doped oxide layer 18, col. 3, line 64) and the gate (Fig. 8, silicon layer 8, col. 2, line 19).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the gaps as disclosed by Wu, to reduce parasitic capacitance (see Gardner, col. 4, lines 26-27).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ando (US 20170092723 A1) in view of Chang et al. (US 20140264276 A1) herein after “Chang”.
Regarding claim 8, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, but Ando fails to disclose wherein the transistor comprises a plurality of low-dimensional material layers, which are spaced apart from each other by at least the gate, the gate dielectric layer, the source, the drain and the spacers.
In the similar field of endeavor of field effect transistors, Fig. 10B of Chang discloses wherein the transistor comprises a plurality of low-dimensional material layers (Fig. 10B, body regions 120B, ¶ [0088]), which are spaced apart from each other by at least the gate (Fig. 10B, semiconductor gate electrode 54, ¶ [0081]), the gate dielectric layer (Fig. 10B, gate dielectrics 50, ¶ [0080]), the source (Fig. 10B, source regions 130S, ¶ [0085]), the drain (Fig. 10B, drain regions 130D, ¶ [0085]) and the spacers (Fig. 10B, gate spacer 56, ¶ [0079]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the plurality of low-dimensional material layers as disclosed by Chang, to improve device scaling (see Chang, ¶ [0002]).
Regarding claim 9, Figs. 6 and 9 of Ando disclose the transistor according to claim 1 as applied above, but Ando fails to disclose comprising:
a second dielectric layer on a surface of the gate away from the gate dielectric layer, wherein:
a ratio of a thickness of the second dielectric layer to a thickness of the gate is in a range of 1:1 to 20:1;
the second dielectric layer comprises at least one selected from silicon nitride and silicon oxide;
and/or the gate comprises at least one selected from TaN, TiN and polycrystalline silicon.
In the similar field of endeavor of field effect transistors, Fig. 10B of Chang discloses comprising:
a second dielectric layer (Fig. 10B, gate cap dielectric 58, ¶ [0068]) on a surface of the gate (54) away from the gate dielectric layer (50), wherein:
a ratio of a thickness of the second dielectric layer (58) to a thickness of the gate (54) is in a range of 1:1 to 20:1 (Fig. 10B, “The thickness of the semiconductor gate electrode material layer, as measured in a planar region, can be from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed”, “The thickness of the gate cap dielectric layer, as measured in a planar region, can be from 50 nm to 300 nm”, ¶ [0068]);
the second dielectric layer (58) comprises at least one selected from silicon nitride and silicon oxide (Fig. 10B, “The gate cap dielectric layer includes a dielectric material layer such as silicon oxide, silicon nitride”, ¶ [0068]); and/or
the gate (54) comprises at least one selected from TaN, TiN and polycrystalline silicon (Fig. 10B, “The semiconductor gate electrode material layer can include a doped semiconductor material such as doped polysilicon”, ¶ [0068]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the second dielectric layer as disclosed by Chang, to improve device scaling and simplify production (see Chang, ¶ [0002]).
Regarding claim 10, Ando and Chang together disclose the transistor according to claim 9 as applied above, but Ando fails to disclose wherein the thickness of the second dielectric layer is in a range of 100 to 2000 nm, and the thickness of the gate is in a range of 5 to 100 nm.
In the similar field of endeavor of field effect transistors, Fig. 10B of Chang discloses wherein the thickness of the second dielectric layer (58) is in a range of 100 to 2000 nm (Fig. 10B, “The thickness of the gate cap dielectric layer, as measured in a planar region, can be from 50 nm to 300 nm”, ¶ [0068]), and the thickness of the gate (54) is in a range of 5 to 100 nm (Fig. 10B, “The thickness of the semiconductor gate electrode material layer, as measured in a planar region, can be from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed”, ¶ [0068]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the second dielectric layer as disclosed by Chang, to improve device scaling and simplify production (see Chang, ¶ [0002]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ando (US 20170092723 A1) and Chang (US 20140264276 A1) in further view of Kizilyalli et al. (US 20130032812 A1) herein after “Kizilyalli”.
Regarding claim 11, Ando and Chang together disclose the transistor according to claim 9 as applied above, but Ando fails to disclose wherein:
an orthographic projection of the gate on the substrate is within an orthographic projection of the second dielectric layer on the substrate;
a ratio of a distance between the source and the gate or a distance between the drain and the gate to a length of a channel is in a range of 0.1 to 0.4; and/or
the length of the channel is in a range of 20 nm to 5 µm.
In the similar field of endeavor of field effect transistors, Figs. 5B and 5D of Chang disclose wherein:
an orthographic projection of the gate (54) on the substrate (10) is within an orthographic projection of the second dielectric layer (58) on the substrate (10) (shown in Figs. 5B and 5D).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the second dielectric layer as disclosed by Chang, to improve device scaling and simplify production (see Chang, ¶ [0002]).
Chang fails to disclose a ratio of a distance between the source and the gate or a distance between the drain and the gate to a length of a channel is in a range of 0.1 to 0.4; and/or
the length of the channel is in a range of 20 nm to 5 µm.
in the similar field of endeavor of field effect transistors, Fig. 5 of Kizilyalli discloses a ratio of a distance between the source (248) and the gate (220) or a distance between the drain (248) and the gate (220) to a length of a channel is in a range of 0.1 to 0.4; and/or
the length of the channel is in a range of 20 nm to 5 µm (Fig. 5, “the width 506 of the channel region 501 can be between 0.5 µm and… less than 3 µm”, ¶ [0042]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Ando with the channel width as disclosed by Kizilyalli, to achieve the desired functionality (see Kizilyalli, ¶ [0042]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893