DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group II (method), Species A of Fig. 1, claims 11-13, in the reply filed on September 16, 2025 is acknowledged. The traversal is on the ground that (1) “the purpose of a restriction requirement is to address an undue burden of search and examination on the Examiner…” and (2) “Group I and Group II are linked by a single general inventive concept.” Applicant’s arguments have been fully considered but are not found persuasive, because the arguments presented do not address the standards applicable to a restriction requirement under 35 U.S.C. 371 national stage application practice. Moreover, all of the limitations of claim 1 or 11, or at least renders claim 1 or 11 obvious, as set forth in the restriction requirement. The requirement is still deemed proper and is therefore made FINAL. Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b). Therefore, claims 11-13 are presented for examination.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, in “forming spacers between the source and the gate and between the drain and the gate, respectively” recited on line 6-7 of claim 11, a shape of spacer in a top view must be shown in a method for fabricating a transistor, or the feature(s) canceled from the claim(s), because even though Applicants showed a cross-sectional view of the transistor in Fig. 1 of the current application, a shape (or geometry) of spacer 500 in a top view was not shown, and multiple spacers would only be present if spacer 500 has a rectangular in a top view, however, if spacer 500 has a circular shape in a top view (i.e., a cylindrical spacer), only a single spacer would be exist between the source/drain and the gate (see attached Examiner’s figure below). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
PNG
media_image1.png
477
715
media_image1.png
Greyscale
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, it is not clear what shape spacer(s) recited on line 6 are intended to have, because Applicants did not originally disclose or do not specifically claim whether spacer 500 has a rectangular (or square) or circular configuration when viewed from the top of the transistor. Multiple spacers would only be present if spacer 500 has a rectangular in a top view, however, if spacer 500 has a circular shape in a top view (i.e., a cylindrical spacer), only a single spacer would be existed between the source/drain and the gate. Also see Drawing Objections above.
Claims 12-13 depend on claim 11, therefore, claims 12-13 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Meng et al. (CN 110350029 A, hereinafter Meng).
Regarding claim 11, Meng discloses for a method for fabricating a transistor comprising that
forming a low-dimensional material layer (carbon nanotubes 110, Fig. 2a), a gate dielectric layer (gate stack structure 120, Fig. 2a), a source (source contact structure 130, Fig. 2f), a drain (drain contact structure 140, Fig. 2f) and a gate (gate stack structure 120, Fig. 2a-2g) above a substrate (substrate 101, Fig. 2a), because the gate stack structure 120 by Meng includes a gate dielectric and a gate conductor stacked on the carbon nanotubes 110 ([0041], Fig. 2a),
wherein the gate dielectric layer (a portion of 120, Fig. 2a) is located between the low-dimensional material layer (110, Fig. 2a) and the gate (a portion of 120, Fig. 2a), because it is well established in the semiconductor industry that a functioning transistor employing a carbon nanotube channel necessarily includes a gate dielectric layer disposed between the gate conductor and the carbon nanotube channel, as the presence of such a dielectric is fundamental to enabling proper gate control and device operation; and
forming spacers (spacers 103 on both sides of the gate stack structure 120, Fig. 2a) between the source (130, Fig. 2f) and the gate (a portion of 120, Fig. 2f) and between the drain (140, Fig. 2f) and the gate (a portion of 120, Fig. 2f), respectively;
wherein the substrate (101, Figs. 2a-2g) has fixed charges, or interface dipoles are formed by the substrate and an insulating dielectric layer (gate dielectric layer of the gate stack structure 120, Fig. 2g) comprising at least one of the gate dielectric layer (a portion of 120, Fig. 2g) and the spacers (103, Fig. 2g), because Applicants do not specifically claim what the substrate is made of or what material’s composition the substrate has, the substrate 101 by Meng includes an insulating layer such as silicon oxide ([0040]) and it is well-known in the semiconductor industry that fixed charges are inherently present in insulating substrates such as SiO2, arising from impurities, defects, or structural imperfections in the SiO2 network. Since such impurities or defects are practically unavoidable in semiconductor manufacturing processes, any real SiO2 substrate would inherently exhibit some level of fixed charges; also, because Applicants originally disclosed that the insulating dielectric layer includes the gate dielectric layer 310 and/or spacers 500 (line 32, page 9 of the current application), and therefore, the gate dielectric layer of the gate stack structure 120 and/or the spacers 103 by Meng (Fig. 2g) can correspond to the insulating dielectric layer in the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Cao et al. (US 9,287,516, hereinafter Cao).
Regarding claim 11, Cao discloses for a method for fabricating a transistor (Fig. 9) comprising that
forming a low-dimensional material layer (carbon nanotubes 206, Fig. 9), because carbon nanotubes (CNTs) are classified as one-dimensional (1-D) material, which corresponds to the low-dimensional material layer in the claimed invention, a gate dielectric layer (first gate dielectric material 214, Fig. 9), a source (source electrode 208, Fig. 9), a drain (drain electrode 210, Fig. 9) and a gate (gate electrode material 212, Fig. 9) above a substrate (a composite substrate of substrate 202 and dielectric layer 204, Fig. 9), because Applicants do not specifically claim what a substrate is made of and/or what material’s composition a substrate has, i.e., whether it is a single layer substrate or multilayers such as semiconductor-on-insulator (SOI) wafer, and the Merriam-Webster dictionary defines a word “substratum” as “an underlying support or foundation”, and the substrate 202 and the dielectric layer 204 by Cao is the underlying support of several layers and components, therefore, the composite substrate of layers 202 and 204 can correspond to the substrate in the claimed invention,
wherein the gate dielectric layer (214, Fig. 9) is located between the low-dimensional material layer (206, Fig. 9) and the gate (212, Fig. 9); and
forming spacers (dielectric 216 and 218, Fig. 9) between the source (208, Fig. 9) and the gate (212, Fig. 9) and between the drain (210, Fig. 9) and the gate (212, Fig. 9), respectively;
wherein the substrate (202/204, Fig. 9) has fixed charges, or interface dipoles are formed by the substrate (202/204, Fig. 9) and an insulating dielectric layer (216/218 or 214, Fig. 9) comprising at least one of the gate dielectric layer (214, Fig. 9) and the spacers (216/218, Fig. 9), because the insulating layer 204 of a composite substrate of 202/204 by Cao “may be made of silicon dioxide, silicon nitride, or other dielectrics for insulating purposes” (emphasis added, Col. 3, lines 10-12) and it is well-known in the semiconductor industry that fixed charges are inherently present in insulating substrates such as SiO2, arising from impurities, defects, or structural imperfections in the SiO2 network. Since such impurities or defects are practically unavoidable in semiconductor manufacturing processes, any real SiO2 substrate would inherently exhibit some level of fixed charges; also, because Applicants originally disclosed that the insulating dielectric layer includes the gate dielectric layer 310 and/or spacers 500 (line 32, page 9 of the current application), and therefore, the gate dielectric 214 and/or the dielectrics 216/218 by Cao (Fig. 9) can correspond to the insulating dielectric layer in the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over by Meng et al. (CN 110350029 A, hereinafter Meng).
Regarding claim 12, Meng does not explicitly disclose that forming the substrate by thermal oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition; and/or subjecting a surface of the substrate to a pretreatment before the low-dimensional material layer is formed, wherein the pretreatment comprises at least one of plasma treatment, annealing treatment, wet chemical cleaning, and surface molecule modification.
However, Meng further discloses that “using chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a physical vapor deposition (Physical Vapor Deposition (PVD) process to form the interlayer dielectric layer 106, wherein the material, the interlayer dielectric layer 106 comprises silicon oxide” (emphasis added, [0071], see the attached machine-translated copy) and since the substrate 101 by Meng includes an insulating layer such as silicon oxide ([0040]), therefore, one would readily recognize that the substrate 101 would be deposited by using CVD or PVD process and one of ordinary skill in the semiconductor industry that CVD and PVD are widely used and industry standard.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Chemical Vapor Deposition and Physical Vapor Deposition are widely used and industry standard for deposition of silicon oxide and other insulating materials, as disclosed by Meng.
Furthermore, it is obvious to one of ordinary skill in the semiconductor industry that the substrate would be subjected to some form of treatments such as wet/dry cleaning and/or annealing prior to CNT (i.e., low-dimensional material layer in the claimed invention) formation and it is generally considered as a routine optimization to adjust surface energy or remove adsorbates/contaminants from the substrate ensuring good adhesion and good electrical contact.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over by Cao et al. (US 9,299,939, hereinafter Cao).
Regarding claim 12, Cao further discloses for the method according to claim 11 that forming the substrate (202/204, Fig. 9) by thermal oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition, because “dielectric layer 204 may be deposited on substrate 202 by chemical vapor deposition method or atomic layer deposition method or other suitable techniques” (Col. 4, line 11-14).
Cao does not explicitly disclose that optionally, the method further comprises subjecting a surface of the substrate to a pretreatment before the low-dimensional material layer is formed, wherein the pretreatment comprises at least one of plasma treatment, annealing treatment, wet chemical cleaning, and surface molecule modification.
However, it is obvious to one of ordinary skill in the semiconductor industry that the substrate would be subjected to some form of treatments such as wet/dry cleaning and/or annealing prior to CNT (i.e., low-dimensional material layer in the claimed invention) formation and it is generally considered as a routine optimization to adjust surface energy or remove adsorbates/contaminants from the substrate ensuring good adhesion and good electrical contact.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over by Cao et al. (US 9,299,939, hereinafter Cao) in view of Xu et al. (US 2020/0259009, hereinafter Xu).
Regarding claim 13, Cao further discloses for the method according to claim 11 that sequentially forming the low-dimensional material layer (206, Fig. 4), a gate dielectric material layer (214, Fig. 6) and a gate material layer (212, Fig. 7) on the substrate (202/204, Figs. 4-9);
patterning the gate material layer to form the gate (212, Fig. 7) and expose a part of the gate dielectric material layer where the gate is not located (sidewall of the first gate dielectric material 214 shown in Fig. 8);
forming a spacer material layer (216/218, Fig. 9) on a top and a sidewall of the gate (top surface and sidewall of the gate electrode material 212, Fig. 9) and the exposed part of the gate dielectric material layer (sidewall of the first gate dielectric material 214, Fig. 9) by atomic layer deposition or chemical vapor deposition, because Cao further discloses that “In one embodiment, dielectric 214 may include AlON/HfO2 and dielectric 216 and 218 may include AlON/Al2O3. In another embodiment, dielectric 214 may include AlON/Al2O3 and dielectric 216 and 218 may include AlON/HfO2” (Col. 3, lines 31-35) and it is well-known in the semiconductor industry that chemical vapor deposition and atomic layer deposition are widely used for deposition of AlON or HfO2;
removing a part of the spacer material layer (216/218, Fig. 9) by dry etching and retaining the spacer material layer at the sidewall of the gate (sidewall of 212, Fig. 9) to form the spacers (216/218, Fig. 9), because “the second dielectric may be deposited to cover the source electrode 208, drain electrode 210, gate 224 and the first gap 220 and second gap 222 and an etching process may be used to remove the second dielectric from the source electrode 208, drain electrode 210 and gate electrode 212, thereby leaving second dielectric 216 and 218 in their respective gaps 220 and 222” (Col. 4, lines 55-61), therefore, the etching process by Cao removes a part of the second dielectric layer 216 and 218 (Fig. 9);
Cao differs from the claimed invention by not showing that removing the gate dielectric material layer at a side of the spacers away from the gate by etching to form the gate dielectric layer; and depositing a metal to form the source and the drain, respectively.
However, Xu discloses for a double gate two-dimensional (2D) material transistor that the top gate dielectric 140 is deposited on the layer of 2D material 130 (Fig. 3, [0030]), the first/second/third sets of spacers 170/180/190 are deposited on the top gate dielectric 140 (Figs. 4-6), and the top gate dielectric 140 at a side of the spacers 170/180/190 is removed by a directional etch (Fig. 7, [0035]); and then the source and drain contact metal 210 is deposited (Fig. 12, [0037]), as described in claim 13 of the current application.
Moreover, it is well-known in the semiconductor industry that numerous methods are available for fabricating field-effect transistors based on 2D materials and that various combinations of conventional techniques such as gate dielectric deposition, insulator deposition, gate/source/drain formation, photolithography, and plasma etching can be employed.
Since both Cao and Xu teach a low-dimensional material-based transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a gate electrode and spacers can be formed on a gate dielectric layer prior to forming source/drain electrodes, as disclosed by Xu, in order to implement one of the well-known fabrication sequences for 1D/2D materials-based field-effect transistors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
Prosecution Insights