Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: OSR-847-HQ
Filling Date: 03/03/2023
Priority Date: 10/29/21
Inventor: Stauss et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 43 is objected to because of the following informalities:
Claim 43 in last line recites “the first layer”. However, it should be “the first doped layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 43 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wierer et al (WO 2010/112980 A1, the document is attached).
Regarding claim 43, Wierer discloses a semiconductor arrangement (Figs. 1-4, Paras. 21-42) comprising: a carrier substrate 10 (Para. 21); a first doped layer 12, 14 arranged on the carrier substrate 10 and having at least one first region 54; a second layer 36 arranged on the first doped layer 12, 14; and a functional semiconductor layer sequence 12, 54 arranged on the second layer 36 (on the lower surface), wherein the at least one first region 54 of the first doped layer 12, 14 comprises a porosified semiconductor material 54 having a degree of porosity of at least 20% by volume (Paras. 21-23), wherein the functional semiconductor layer sequence 12, 54 has at least one trench 54 which separates regions of the functional semiconductor layer 12 sequence from one another, and wherein each of these regions 12 (portion between 54) is arranged over a second region 12 (bottom portion) of the first layer 12, 14.
Allowable Subject Matter
Claims 22-29, 32-41 and 44-45 are allowed.
Response to Arguments
Applicant’s arguments with respect to claim(s) 43 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817