DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/02/2026 was filed after the mailing date of the Final Office Action on 11/20/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/2/2026 has been entered.
Response to Amendment
Acknowledgment is made of the amendment filed 03/02/2026, in which: the title and claims 1 and 4 are amended; claims 9 and 17 are cancelled; and the rejection of the claims are traversed. Claims 1, 3-8, 10-16, and 18 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US Publication 20210359073) in view of Yanase et al. (US Publication 20200035156) and Zheng et al. (US Publication 20210359031).
Regarding independent claim 1, Cha teaches a display substrate (fig. 3, 10), comprising a display area (DA) and a peripheral area (DPA) located on at least a side of the display area, the display substrate comprising:
a base substrate (100);
a plurality of subpixels (fig. 4, Pm) located on the base substrate, at least part of the subpixels located in the display area comprises a light-emitting element (fig. 7, OLED) and a pixel circuit (PC/PC’), the light-emitting element comprising a light-emitting functional layer (fig. 6, 122e) and a first electrode (121 and 121’) and a second electrode (123) on both sides of the light-emitting functional layer in a direction perpendicular to the base substrate, the first electrode being located between the light-emitting functional layer and the base substrate (fig. 6);
the pixel circuit comprising a driving transistor (fig. 7, T1) and a light-emitting control transistor (T6), and the first electrode of the light-emitting element being electrically connected to the light-emitting control transistor (fig. 7, drain electrode of T6 connected to anode of OLED); and
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a bonding area (fig. 3, PAD) located in the peripheral area and on a first side of the display area (paragraph 0084), wherein the pixel circuit comprises an active semiconductor pattern (fig. 6, A1), the active semiconductor pattern comprises a channel region (center region of A1) and a source/drain region (left and right sides of A1 corresponding to S1/D1 respectively, see figure below) of each transistor;
in a same pixel circuit, the channel region of the light-emitting control transistor is located on a side of the channel region of the driving transistor away from the bonding area (fig. 10, G6 of T6 which overlaps channel region of T6 is located on a side of G1 of T1 which overlaps channel region of T1 away from bonding area PAD),
wherein the plurality of subpixels comprises a plurality of first subpixels (fig. 4, Pr), a plurality of second subpixels (Pg), and a plurality of third subpixels (Pb), the plurality of first subpixels and the plurality of third subpixels are alternately provided in a first direction (x) and a second direction (y) to form a plurality of first pixel rows (1SN) and a plurality of first pixel columns (1M, 3M, etc.), the plurality of second subpixels are arranged in array along the first direction and the second direction to form a plurality of second pixel rows (2SN) and a plurality of second pixel columns (2SN), the plurality of first pixel rows and the plurality of second pixel rows are alternately arranged along the second direction and staggered from each other in the first direction (fig. 4), the plurality of first pixel columns and the plurality of second pixel columns are alternately arranged along the first direction and staggered from each other in the second direction (fig. 4), and the first direction and the second direction intersect with each other (fig. 4),
wherein at least one of the first subpixel and the third subpixel is a red subpixel (Pr) configured to emit red light, the other one of the first subpixel and the third subpixel is a blue subpixel (Pb) configured to emit blue light, and the second subpixel is a green subpixel (Pg) configured to emit green light (paragraph 0096).
Cha does not teach wherein, in a subpixel closest to the bonding area, an end of the active semiconductor pattern of the pixel circuit closest to the bonding area is a first end, an end of the first electrode of the light-emitting element closest to the bonding area is a second end, and the second end is closer to the bonding area than the first end, wherein a row of subpixels closest to the bonding area is the first pixel row.
Yanase teaches in a subpixel closest to the bonding area (fig. 5C, see figure below), an end of the active semiconductor pattern (T1) of the pixel circuit closest to the bonding area is a first end (see figure below), an end of the first electrode (162) of the light-emitting element closest to the bonding area is a second end (see figure below), and the second end is closer to the bonding area than the first end (see figure below).
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Zheng teaches wherein a row of subpixels closest to the bonding area is the first pixel row (fig. 2, row closest to bonding area corresponds to last row of R and B subpixels).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha, the first and second ends of Yanase, and the subpixel arrangement of Zheng in order to attain a configuration to transmit light coming from the organic light-emitting films (Yanase paragraph 0051) and reduce pixel density (Zheng paragraph 0041).
Regarding dependent claim 18, Cha further teaches a display device (fig. 3), comprising a display substrate (10) according to claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cha in view of Yanase and Zheng as applied to claim 1 above, and further in view of Du et al. (CN Publication 114255703/Machine Translation Document 11/13/2025).
Regarding dependent claim 3, Cha in view of Yanase and Zheng teach the display substrate according to claim 1.
Cha in view of Yanase and Zheng do not teach wherein, in a same subpixel of at least one subpixel, the channel region of the light-emitting control transistor is located on a side of a center of a light-emitting region of the light-emitting element away from the bonding area in a direction parallel to the base substrate.
Du teaches wherein, in a same subpixel of at least one subpixel, the channel region of the light-emitting control transistor (fig. 3, T5) is located on a side of a center of a light-emitting region (1201c) of the light-emitting element away from the bonding area in a direction parallel to the base substrate (fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha and the channel region of the light-emitting control transistor of Du in order to reduce the size of the lower frame (Du machine translation, page 10 paragraph 4).
Claims 4-6, 10, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cha in view of Du as applied to claim 1 above, and further in view of Yang (US Publication 20140071175).
Regarding dependent claim 4, Cha further teaches the display substrate according to claim 1,
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wherein a second pixel row (2SN) comprising a plurality of second subpixel pairs (see figure below) arranged in the first direction, two second subpixels in each second subpixel pair are a first pixel block (see figure below) and a second pixel block (see figure below), and the first pixel block and the second pixel block are alternately arranged along the first direction (see figure below);
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the plurality of subpixels comprises a plurality of minimum repeating units (see figure below), each minimum repeating unit comprising one first subpixel, one first pixel block, one second pixel block and one third subpixel (see figure below), in which the first pixel block and the first subpixel constitute a first pixel unit (see figure below), the second pixel block and the third subpixel constitute a second pixel unit (see figure below);
in the first pixel unit, the first pixel block is located on a side of the first subpixel away from the bonding area (fig. 4), and in the second pixel unit, the second pixel block is located on a side of the third subpixel away from the bonding area (fig. 4).
Cha in view of Yanase and Zheng does not teach the first pixel block and the second pixel block in a second pixel column are alternately arranged in the second direction.
Yang teaches the first pixel block and the second pixel block in a second pixel column are alternately arranged in the second direction (see figure below, first and second pixel blocks alternate vertically).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yanase and Zheng and the arrangement of first/second pixel blocks of Yang in order to arrange the pixels in a pentile matrix (Yang paragraph 0020).
Regarding dependent claim 5, Cha further teaches the display substrate according to claim 4, wherein, in a same subpixel of at least one of the first subpixel and the third subpixel, the channel region of the light-emitting control transistor is located on a side of a center of a light-emitting region (fig. 6, 122b) of the light-emitting element away from the bonding area (fig. 6, A1 of TFT is located on a side of a center of light emitting region 122b).
Regarding dependent claim 6, Cha further teaches the display substrate according to claim 4, wherein the first electrode of the light-emitting element comprises a main electrode (fig. 6, 121) and a connecting electrode (CM) electrically connected to each other, the main electrode overlaps with the light-emitting region of the light-emitting element (fig. 6, 121 overlaps with 122b), and the connecting electrode is electrically connected to the light-emitting control transistor (fig. 6, CM connected to D1 of TFT);
in the same subpixel of at least one of the first subpixel and the third subpixel, the channel region of the light-emitting control transistor is located on a side of a center of the main electrode away from the bonding area (fig. 6, A1 of TFT is located on a side of a center of 121 away from bonding area PAD in fig. 3).
Yanase further teaches the connecting electrode (fig. 5C, 181G2 occupies space for connecting electrode of Cha) does not overlap with the light-emitting region (185G2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yang and the connecting electrode position of Yanase per the reason(s) stated above in claim 4.
Regarding dependent claim 10, Cha further teaches the display substrate according claim 4, wherein, in the first pixel unit, the pixel circuit of the first pixel block and the pixel circuit of the first subpixel are arranged in the first direction;
in the second pixel unit, the pixel circuit of the second pixel block and the pixel circuit of the third subpixel are arranged in the first direction (fig. 4, pixel circuit PCA for each subpixel/pixel block are arranged in the first direction).
Regarding dependent claim 15, Cha in view of Yanase, Zheng, and Yang teaches the display substrate according to claim 4.
Cha in view of Yanase, Zheng, and Yang does not explicitly teach wherein, in at least one of the first subpixel and the third subpixel, corners of a light-emitting region of the light-emitting element comprises a first corner and a second corner opposite to each other, and a distance from an intersection of extension lines of two sides constituting the first corner to a center of the light-emitting region is greater than a distance from an intersection of two sides or extension lines of the two sides constituting the second corner to the center of the light-emitting region; at least one of the first subpixel and the third subpixel comprises a first type subpixel and a second type subpixel; for different types of subpixels, directions from a vertex of the first corner to a vertex of the second corner are different; and in the first type subpixel and the second type subpixel, the directions from the vertex of the first corner to the vertex of the second corner direction are a first orientation and a second orientation, respectively, and the first orientation and the second orientation are opposite to each other.
However, Cha discloses a plurality of main sub-pixels Pm may be arranged in various configurations such as a stripe structure, a mosaic arrangement structure, a delta arrangement structure, etc., or any other suitable pixel arrangement or structure according to the design of the display device (paragraph 0100).
It would have been obvious to one having ordinary skill in the art before the effective date of the invention to modify the shape of the first and third subpixels, since it has been held that changing the shape of part of an invention involves only routine skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding dependent claim 16, Cha in view of Yanase, Zheng, and Yang teaches the display substrate according to claim 15.
Cha in view of Yanase, Zheng, and Yang does not explicitly teach wherein at least one of the first subpixel and the third subpixel further comprises a third type subpixel and a fourth type subpixel; for the third type subpixel and the fourth type subpixel, directions from the vertex of the first corner to the vertex of the second corner direction are a third orientation and a fourth orientation, respectively, the third orientation and the fourth orientation are opposite to each other, and the first orientation intersects with the third orientation.
However, Cha discloses a plurality of main sub-pixels Pm may be arranged in various configurations such as a stripe structure, a mosaic arrangement structure, a delta arrangement structure, etc., or any other suitable pixel arrangement or structure according to the design of the display device (paragraph 0100).
It would have been obvious to one having ordinary skill in the art before the effective date of the invention to modify the shape of the first and third subpixels, since it has been held that changing the shape of part of an invention involves only routine skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cha in view of Yanase, Zheng, and Yang as applied to claim 4 above, and further in view of Du.
Regarding dependent claim 7, Cha in view of Yanase, Zheng, and Yang teach the display substrate according to claim 4.
Cha in view of Yanase, Zheng, and Yang do not teach wherein, for the channel region of the light-emitting control transistor and the light-emitting region of the light-emitting element of the same second subpixel, the channel region is farther away from the bonding area than the light-emitting region of the light-emitting element.
Du teaches wherein, for the channel region of the light-emitting control transistor (fig. 3, T5) and the light-emitting region (1201b) of the light-emitting element of the same second subpixel, the channel region is farther away from the bonding area than the light-emitting region of the light-emitting element (fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yanase, Zheng, and Yang, and the channel/light-emitting region of Du in order to reduce the size of the lower frame (Du machine translation, page 10 paragraph 4)
Regarding dependent claim 8, Cha in view of Yanase, Zheng, and Yang teach the display substrate according to claim 4.
Cha in view of Yanase, Zheng, and Yang does not teach wherein a shape of the channel region of the driving transistor comprises a U-shape, and the U-shape opens towards a side away from the bonding area.
Du teaches wherein a shape of the channel region of the driving transistor (fig. 5a, T1a) comprises a U-shape, and the U-shape opens towards a side away from the bonding area (fig. 5, U shape of T1a opens sideways away from bonding area COF located below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yanase, Zheng, and Yang, and the channel region shape of Du in order to reduce the size of the lower frame (Du machine translation, page 10 paragraph 4).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cha in view of Yanase, Zheng, and Yang as applied to claim 4 above, and further in view of Jo et al. (US Publication 20210126079).
Regarding dependent claim 11, Cha in view of Du and Yang teaches the display substrate according to claim 4.
Cha in view of Yanase, Zheng, and Yang does not teach wherein, in the first pixel unit, the active semiconductor pattern of the first pixel block and the active semiconductor pattern of the first subpixel are symmetrically distributed with respect to a straight line located between the two active semiconductor patterns and extending in the second direction; in the second pixel unit, the active semiconductor pattern of the second pixel block and the active semiconductor pattern of the third subpixel are symmetrically distributed with respect to a straight line located between the two active semiconductor patterns and extending in the second direction.
Jo teaches wherein, in the first pixel unit, the active semiconductor pattern of the first pixel block and the active semiconductor pattern of the first subpixel are symmetrically distributed with respect to a straight line located between the two active semiconductor patterns and extending in the second direction (fig. 3 paragraph 0086, one unit semiconductor pattern 150 corresponds to two pixels in which the two pixels correspond to the first pixel block and the first subpixel of Cha);
in the second pixel unit, the active semiconductor pattern of the second pixel block and the active semiconductor pattern of the third subpixel are symmetrically distributed with respect to a straight line located between the two active semiconductor patterns and extending in the second direction (fig. 3 paragraph 0086, one unit semiconductor pattern 150 corresponds to two pixels in which the two pixels correspond to the second pixel block and the third subpixel of Cha).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yanase, Zheng, and Yang and the symmetry of the active semiconductor pattern of Jo in order to form a high resolution display device by sharing wiring and reducing the area to be occupied (Jo paragraph 0086).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cha in view of Yanase, Zheng, and Yang as applied to claim 4 above, and further in view of Huang et al. (US Publication 20210159284).
Regarding dependent claim 12, Cha in view of Du and Yang teaches the display substrate according to claim 4.
Cha in view of Yanase, Zheng, and Yang does not teach further comprising: a first conductive layer located between the first electrode of the light-emitting element and the base substrate; a second conductive layer located between the first conductive layer and the first electrode of the light-emitting element, wherein the first conductive layer comprises a first connection structure and a first power signal line, the second conductive layer comprises a data line, a second connection structure and a second power signal line, and the second power signal line is electrically connected to the first power signal line; the first electrode of the light-emitting control transistor is electrically connected to the driving transistor, and the second electrode of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through the first connection structure and the second connection structure.
Huang teaches further comprising:
a first conductive layer (fig. 7B 600) located between the first electrode of the light-emitting element and the base substrate;
a second conductive layer (200) located between the first conductive layer and the first electrode of the light-emitting element, wherein the first conductive layer comprises a first connection structure (620) and a first power signal line (610), the second conductive layer comprises a data line (fig. 8C, Vd located in first conductive layer, but can be rearranged to be placed in second conductive layer per MPEP 2144.04, In re Japikse, 86 USPQ 70), a second connection structure (fig. 7B 220) and a second power signal line (210), and the second power signal line is electrically connected to the first power signal line (fig. 7B, paragraph 0129);
the first electrode of the light-emitting control transistor is electrically connected to the driving transistor (fig. 2, first electrode of T5 which corresponds to light-emitting control transistor of Cha electrically connected to T1 corresponding to driving transistor of Cha), and the second electrode of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through the first connection structure and the second connection structure (paragraph 0194, drain electrode corresponds to second electrode of light-emitting control transistor of Cha).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yang and the first/second conductive layers of Huang in order to transmit a driving voltage, thereby reducing the adverse effect of the load on the transmitted drive voltage (Huang paragraph 0132).
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Regarding dependent claim 13, Huang further teaches the display substrate according to claim 12, wherein the second conductive layer further comprises a first overlap portion (see figure below) overlapping with a light-emitting region (fig. 7B, 50) of at least one of the first subpixel and the third subpixel, a ratio of an area of the first overlap portion to an area of the light-emitting region is 0.6~1 (see figure below, obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to obtain ratio of overlap portion to light-emitting with routine experiment and optimization, see MPEP 2144.05), and the first overlap portion is substantially symmetrically distributed relative to a straight line extending along the second direction (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yanase, Zheng, and Yang and the overlap portion of Huang per the reason(s) stated above in claim 12.
Regarding dependent claim 14, Huang further teaches the display substrate according to claim 12,
wherein the second conductive layer further comprises a second overlap portion overlapping with a light-emitting region of the second subpixel (see figure below), and the second overlap portion is substantially symmetrically distributed relative to a straight line extending in the second direction (see figure below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Cha in view of Yanase, Zheng, and Yang and the second overlap portion of Huang per the reason(s) stated above in claim 12.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-8, 10-16, and 18 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 03/02/2026 have been fully considered but are not persuasive.
Applicant argues on pages 8-11 of the instant Remarks: “For example, as shown in the comparison between Fig. 3 of Du and Fig. 5A of Du below, the blue annotated line (the upper annotated line appearing between the reproductions of Figs. 3 and 5A of Du below) represents the lower edge of the first electrode (1202b) of the second sub- pixel (1002), while the red line (the lower annotated line appearing between the reproductions of Figs. 3 and 5A of Du below) represents the lower edge of the active semiconductor pattern of the corresponding pixel circuit. It is evident from these figures that the red/lower line is positioned lower than the blue/upper line. Consequently, in Du, the lower end of the active semiconductor pattern is farther down (i.e., closer to the bonding area) than the lower end of the first electrode… As specifically defined in the amended claim 1, the row of subpixels closest to the bonding area must be the "first pixel row," which consists of red and blue subpixels alternately arranged. In contrast, an analysis of Fig. 4 in Cha (reproduced above) reveals that its subpixel repeating pattern (where Pr, Pg, and Pb represent red, green, and blue subpixels, respectively) would result in the row closest to the bottom being a row of green subpixels, which corresponds to the "second pixel row" of the present application.”
However, as stated above, Yanase teaches in a subpixel closest to the bonding area, an end of the active semiconductor pattern (fig. 5C, T1) of the pixel circuit closest to the bonding area is a first end, an end of the first electrode (162) of the light-emitting element closest to the bonding area is a second end, and the second end is closer to the bonding area than the first end (see marked figure corresponding to claim 1) and Zheng teaches wherein a row of subpixels closest to the bonding area is the first pixel row (fig. 2, row closest to bonding area corresponds to last row of R and B subpixels). Therefore, claim 1, as well as dependent claims 3-8, 10-16, and 18, are not patentable over the cited art.
Conclusion
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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