DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on January 21, 2026 was considered by the Examiner.
Response to Arguments
RE: the rejection of claim(s) 1-9 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1-9 has been withdrawn.
RE: the rejection of claim(s) under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new ground of rejection presented herein.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 includes “first information regarding the semiconductor package is written on the the stiffener” (two instances of “the”) which is a typographical error. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO2020162417A1 (“Tsuchida”; previously cited in Office Action dated Dec. 22, 2025) in view of in view of US20160095209A1 (“Starkston”), further in view of KR20140038078A (“Chul”), further in view of Engineering.com, “How to Interpret Capacitor Markings,” available at https://www.engineering.com/how-to-interpret-capacitor-markings/, published January 24, 2018 (“Engineering”); where citations from Tsuchida below are from US20220262759A1 which corresponds to an English translation of WO2020162417A1.
RE: Claim 1, Tsuchida discloses An electronic device (device in FIGs. 3A, 2) comprising:
a semiconductor package (package 1 in FIG. 3A, [0051]) that includes:
a semiconductor chip (11) mounted on a package base material (17);
a sealing member (33; 33 that surrounds the thermally conductive material 31, [0047]; A square opening as viewed in plan is formed in the seal member 33, and the thermally conductive material 31 and the semiconductor chip 11 are located on the inside of the seal member 33, [0047]) that surrounds the semiconductor chip;
a stiffener (14) that surrounds the sealing member; and
a section positioned outside an outer edge of the semiconductor chip and inside an outer edge of the package base material (FIG. 3A shows section between 14 and outer edge of 11 which is positioned outside an outer edge of the semiconductor chip and inside an outer edge of the package base material 17); and
a radiator (50), wherein:
a thermally conductive material (31; 31 is a material having fluidity, [0036]) having fluidity is disposed between a surface of the semiconductor chip and the radiator,
the sealing member encloses the thermally conductive material in a plan view and has an opening to expose the surface of the semiconductor chip (33 surrounds 31, [0047]; A square opening as viewed in plan is formed in the seal member 33, and the thermally conductive material 31 and the semiconductor chip 11 are located on the inside of the seal member 33, [0047]; FIG. 2 shows 33 enclosing 11 in plan view; Accordingly, 33 would also enclose 31 in a plan view; FIG. 2 shows the opening in 33 exposes 11).
Tsuchida does not explicitly disclose:
first information regarding the semiconductor package is written on the the stiffener outside the sealing member and away from the semiconductor chip in the plan view,
second information regarding the semiconductor package is written on a portion of the package base material, and
the portion is inside the sealing member and toward the semiconductor chip in the plan view but not on the surface of the semiconductor chip.
However, Tsuchida teaches that 14 is a stiffener, [0031]
FIG. 2 shows the stiffener 14 is outside the sealing member 33 and away from the semiconductor chip 11 in the plan view.
In the same field of endeavor, Starkston teaches Embodiments of the invention however allow each stiffener in a panel to be marked with traceability marks before the start of the package assembly process. For instance, each stiffener in a panel of stiffeners may be pre-marked with traceability marks during its manufacturing. Thus, when the panel of stiffeners is attached to the panel of package substrates, the traceability mark is already exposed and a re-mark is not needed, [0026].
Starkston teaches a traceability mark is for identification purposes, [0026].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the stiffener 14 to have traceability marks (corresponding to the claimed first information) as taught by Starkston for identification purposes such as providing identification of the chip and/or package. As a result, the traceability marks would be written on stiffener 14 which would be outside 33 and away from the chip 11 in the plan view.
In the same field of endeavor Chul discloses the supporting stiffener 54 is provided at the center of its upper surface with a partial mark 56 (serving as a reference point) for guiding the correct seating direction of the interposer 20 to be mounted on the supporting stiffener 52 ) Are formed in a cross shape or the like using a laser processing method or the like, [0033].
Chul further discloses the support stiffener 54 is provided at its central portion with the upper surface of the support stiffener 54 in the form of a parting mark 56. The support stiffener 54 is provided with a delivery tool (not shown) for attracting the interposer and lowering it to the adhesive material 52 Of the support stiffener 54 can be accurately positioned on the upper surface of each corner of the supporting stiffener 54 by recognizing the partial mark 56 by using the conventional vision system, [0046].
FIGs. 2-4 show the mark 56 is on a top surface of the stiffener 54.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traceability marks on the stiffener 14 to be on its top surface as taught by Chul in order to improve its readability from a top view.
Further, Tsuchida discloses 16 are capacitors, [0031].
In the same field of endeavor, Engineering discloses The image above is of an electrolytic capacitor marked with “100μF,” meaning it has a capacitance of 100 microfarads (the μ prefix indicates 10−6). Expressed differently, this is 0.0001 farads; see pg. 4 top paragraph, see image at the bottom of pg. 3.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mark each capacitor 16 indicating its capacitance as taught by Engineering in order to make this information readily available, which would help in future diagnostics or repairs. As a result, a marking indicating capacitance would be written on the right capacitor 16 in FIG. 3A (corresponding to the second information) which is on a portion of the package base material 17, and this second information would be inside the sealing member 33 and toward the semiconductor chip 11 in the plan view but not on the surface of the semiconductor chip.
RE: Claim 2, Tsuchida in view of Starkston, Chul, Engineering discloses The electronic device according to claim 1, wherein the first information regarding the semiconductor package is written on an upper surface of the stiffener (As modified, the first information is written on an upper surface of the stiffener 14).
RE: Claim 3, Tsuchida in view of Starkston, Chul, Engineering discloses The electronic device according to claim 2, wherein the stiffener is mounted on the package base material (FIG. 3A shows stiffener 14 mounted on 17).
RE: Claim 5, Tsuchida in view of Starkston, Chul, Engineering discloses The electronic device according to claim 1, wherein the semiconductor package further comprises at least one capacitor (right 16 in FIG. 3A), wherein, in the plan view, a portion of the first information is written on the package base material between the at least one capacitor and the stiffener (As modified each capacitor 16 is marked; Accordingly, the left 16 in FIG. 3A would be marked with its capacitance, and marking on the left 16 would be considered to correspond to part of the claimed first information and would be between the right capacitor 16 and the stiffener 14).
RE: Claim 7, Tsuchida in view of Starkston, Chul, Engineering discloses The electronic device according to claim 1, wherein a liquid metal serves as the thermally conductive material (In Tsuchida 31 is in liquid form, [0036]).
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida in view of Starkston, Chul, Engineering as applied to claim 2, further in view of US20110096503 A1 (“Avery”).
RE: Claim 4, Tsuchida in view of Starkston, Chul, Engineering discloses The electronic device according to claim 2, wherein the semiconductor package includes an electronic part (right 16 in FIG. 3A) mounted on the package base material, wherein the second information is written on the electronic part (As modified the second information is written on the right 16 in FIG. 3A).
Tsuchida in view of Starkston, Chul, Engineering does not explicitly disclose:
the electronic part being configured to generate a smaller amount of heat than the semiconductor chip.
However Tsuchida discloses The semiconductor chip 11 functions as a CPU, a GPU, or the like [0030].
In the same field of endeavor, Avery discloses As is known in the industry, certain of these chip components 16, such as central processing unit (CPU) 22, video chips 23, or memory (not shown) produce comparatively greater amounts of heat than do less heat-producing chips 16 such as input or output controllers 27 or individual electrical components 28, such as capacitors or resistors, [0023].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitors 16 to generate a lower amount of heat than the semiconductor chip 11 as taught by Avery to prevent the capacitor from overheating the chip 11 and improve heat dissipation of the device.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida in view of Starkston, Chul, Engineering as applied to claim 1, further in view of US 4594263 A (“Folk”), further in view of US20150348912A1 (“Su”).
RE: Claim 6, Tsuchida in view of Starkston, Chul, Engineering does not explicitly disclose The electronic device according to claim 1, wherein at least one of a letter, a symbol, and a code indicating the first information regarding the semiconductor package is written by at least one of inking, lasering, and sealing.
However, Tsushida discloses The stiffener 14 is a square frame formed by a metal, [0032].
In the same field of endeavor, Folk discloses a high quality, low cost laser marking method which is suitable for marking on metal surfaces of semiconductor device packages, Col. 1, lines 44-48.
Folk further discloses improved laser marking of metal surfaces is accomplished by first depositing a layer of nickel, then converting the nickel to an optically black surface by means of an acid bath, then exposing the surface to laser energy through a mask. This process provides a marking which is highly resistant to abrasion and corrosion, yet is suitable for use with high volume laser marking machinery. In addition, it requires no curing as is the case with ink markings, Col. 4, line 67 to Col. 5, line 8.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mark the metal stiffener 14 using the laser marking method as taught by Folk to ensure the marking is highly resistant to abrasion and corrosion as also taught by Folk.
In the same field of endeavor, Su discloses A package and the method of forming laser marks in the package are provided, [0013].
Su further discloses Laser marks 132 may include letters, digits, figures, or any other symbols that can be used for identification purpose, [0029]. Accordingly, before the effective filing date of the claimed invention, there was a need to determine the content of the traceability marks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traceability marks to include letters, digits, figures, or any other symbols as these would have been obvious to try since letters, digits, figures, or any other symbols are solutions for marks used for identification purposes provided by Su and these would have had a reasonable expectation of success, see MPEP 2143.
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida in view of Starkston, Chul, Engineering as applied to claim 1, further in view of US 5841194 A (“Tsukamoto”).
RE: Claim 9, Tsuchida in view of Starkston, Chul, Engineering does not explicitly disclose The electronic device according to claim 1, wherein the first information regarding the semiconductor package is covered with a removable member.
However Tsuchida discloses when the thermally conductive material 31 has fluidity at room temperature, the radiator 50 can be separated from the semiconductor chip 11. As a result, at the time of repairing the electronic apparatus 1, for example, repair work can be performed after the radiator 50 is removed from the semiconductor device 10, [0037].
Accordingly, radiator 50 is a removable member.
Tsuchida further discloses The radiator 50 is, for example, a heat sink, [0034].
In the same field of endeavor, Tsukamoto discloses the finned heat sink 701 surrounds the peripheral stiffener. In this manner, heat can be efficiently emitted even if a more powerful semiconductor device is packaged, Col. 8, lines 50-55, see FIG. 10.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the radiator 50 to surround the stiffener 14 as taught by Tsukamoto so that heat can be efficiently emitted and removed from the device. As a result, the traceability marks on the stiffener 14 would be covered by the radiator 50.
Claim(s) 10-11, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida in view of Starkston, Chul, Engineering.
RE: Claim 10, Tsuchida discloses An electronic device (device in FIGs. 3A, 2) comprising:
a semiconductor package (package 1 in FIG. 3A, [0051]) that includes a semiconductor chip (11), a package base material (17) on which the semiconductor chip is mounted, and
a stiffener (14) that surrounds the semiconductor chip in a plan view; and a radiator (14 surrounds 11 in plan view in FIG. 2), wherein:
the semiconductor package includes a first section (31 and 11) and a second section (section of package including 14, 16, 17 and excluding 11, 31, 50 and portion of 17 under 11),
the first section is configured to transfer heat from the semiconductor chip to the radiator through a thermally conductive material having fluidity (31; 31 is thermally conductive, [0035] and therefore would transfer heat from 11 to 50; 31 is a material having fluidity, [0036]),
the thermally conductive material is formed on the first section (FIG. 3A shows 31 is formed on 11),
the second section is different from the first section (the second section excludes 11, 31, 50) and includes a first portion covered by the stiffener in the plan view and a second portion corresponding to the package base material (FIG. 3A shows first portion of 17 would be covered by 14 in plan view, and a second portion corresponding to 17 under 16).
Tsuchida does not explicitly disclose:
first information regarding the semiconductor package is written on the second portion, and
second information regarding the semiconductor package is written on the stiffener.
However, Tsuchida teaches that 14 is a stiffener, [0031]
FIG. 2 shows the stiffener 14 is outside the sealing member 33 and away from the semiconductor chip 11 in the plan view.
In the same field of endeavor, Starkston teaches Embodiments of the invention however allow each stiffener in a panel to be marked with traceability marks before the start of the package assembly process. For instance, each stiffener in a panel of stiffeners may be pre-marked with traceability marks during its manufacturing. Thus, when the panel of stiffeners is attached to the panel of package substrates, the traceability mark is already exposed and a re-mark is not needed, [0026].
Starkston teaches a traceability mark is for identification purposes, [0026].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the stiffener 14 to have traceability marks (corresponding to the claimed second information) as taught by Starkston for identification purposes such as providing identification of the chip and/or package. As a result, the traceability marks would be written on stiffener 14 which would be outside 33 and away from the chip 11 in the plan view.
In the same field of endeavor Chul discloses the supporting stiffener 54 is provided at the center of its upper surface with a partial mark 56 (serving as a reference point) for guiding the correct seating direction of the interposer 20 to be mounted on the supporting stiffener 52 ) Are formed in a cross shape or the like using a laser processing method or the like, [0033].
Chul further discloses the support stiffener 54 is provided at its central portion with the upper surface of the support stiffener 54 in the form of a parting mark 56. The support stiffener 54 is provided with a delivery tool (not shown) for attracting the interposer and lowering it to the adhesive material 52 Of the support stiffener 54 can be accurately positioned on the upper surface of each corner of the supporting stiffener 54 by recognizing the partial mark 56 by using the conventional vision system, [0046].
FIGs. 2-4 show the mark 56 is on a top surface of the stiffener 54.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traceability marks on the stiffener 14 to be on its top surface as taught by Chul in order to improve its readability from a top view.
Further, Tsuchida discloses 16 are capacitors, [0031].
In the same field of endeavor, Engineering discloses The image above is of an electrolytic capacitor marked with “100μF,” meaning it has a capacitance of 100 microfarads (the μ prefix indicates 10−6). Expressed differently, this is 0.0001 farads; see pg. 4 top paragraph, see image at the bottom of pg. 3.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mark each capacitor 16 indicating its capacitance as taught by Engineering in order to make this information readily available, which would help in future diagnostics or repairs. As a result, a marking indicating capacitance would be written on the right capacitor 16 in FIG. 3A (corresponding to the first information) which is on a portion of the package base material 17 not under 31.
RE: Claim 11, Tsuchida in view of Starkston, Chul, Engineering discloses The electronic device according to claim 10, wherein the thermally conductive material is not attached to the second section (FIG. 3A shows 31 is not directly attached to the second section of 17).
RE: Claim 16, Tsuchida discloses A semiconductor package (device in FIGs. 3A, 2) comprising:
a semiconductor chip (11);
a package base material (17) on which the semiconductor chip is mounted;
a stiffener (14) that surrounds the semiconductor chip in a plan view; and
a section (outer portion of 17 excluding the portion of 17 under 11) positioned outside an outer edge of the semiconductor chip and inside an outer edge of the package base material.
Tsuchida does not explicitly disclose:
first information regarding the semiconductor package is written on the stiffener, and second information regarding the semiconductor package is written on the section of the semiconductor package and not on a surface of the semiconductor chip,
wherein the second information is positioned toward the semiconductor chip in the plan view as compared to the first information.
However, Tsuchida teaches that 14 is a stiffener, [0031]
FIG. 2 shows the stiffener 14 is outside the sealing member 33 and away from the semiconductor chip 11 in the plan view.
In the same field of endeavor, Starkston teaches Embodiments of the invention however allow each stiffener in a panel to be marked with traceability marks before the start of the package assembly process. For instance, each stiffener in a panel of stiffeners may be pre-marked with traceability marks during its manufacturing. Thus, when the panel of stiffeners is attached to the panel of package substrates, the traceability mark is already exposed and a re-mark is not needed, [0026].
Starkston teaches a traceability mark is for identification purposes, [0026].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the stiffener 14 to have traceability marks (corresponding to the claimed first information) as taught by Starkston for identification purposes such as providing identification of the chip and/or package. As a result, the traceability marks would be written on stiffener 14 which would be outside 33 and not on the surface of the chip 11.
In the same field of endeavor Chul discloses the supporting stiffener 54 is provided at the center of its upper surface with a partial mark 56 (serving as a reference point) for guiding the correct seating direction of the interposer 20 to be mounted on the supporting stiffener 52 ) Are formed in a cross shape or the like using a laser processing method or the like, [0033].
Chul further discloses the support stiffener 54 is provided at its central portion with the upper surface of the support stiffener 54 in the form of a parting mark 56. The support stiffener 54 is provided with a delivery tool (not shown) for attracting the interposer and lowering it to the adhesive material 52 Of the support stiffener 54 can be accurately positioned on the upper surface of each corner of the supporting stiffener 54 by recognizing the partial mark 56 by using the conventional vision system, [0046].
FIGs. 2-4 show the mark 56 is on a top surface of the stiffener 54.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traceability marks on the stiffener 14 to be on its top surface as taught by Chul in order to improve its readability from a top view.
Further, Tsuchida discloses 16 are capacitors, [0031].
In the same field of endeavor, Engineering discloses The image above is of an electrolytic capacitor marked with “100μF,” meaning it has a capacitance of 100 microfarads (the μ prefix indicates 10−6). Expressed differently, this is 0.0001 farads; see pg. 4 top paragraph, see image at the bottom of pg. 3.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mark each capacitor 16 indicating its capacitance as taught by Engineering in order to make this information readily available, which would help in future diagnostics or repairs. As a result, a marking indicating capacitance would be written on the right capacitor 16 in FIG. 3A (corresponding to the second information) which is on a portion of the package base material 17, and this second information would be inside the sealing member 33 and toward the semiconductor chip 11 in the plan view but not on the surface of the semiconductor chip 11. As the second information is on 16, it would be toward 11 in plan view as compared to the first information on 14.
RE: Claim 18, Tsuchida discloses An electronic device (device in FIGs. 3A, 2) manufacturing method comprising: preparing a semiconductor package including;
a semiconductor chip (11);
a package base material (17), wherein the semiconductor chip is mounted on the package base material;
a first section (first section including 14) positioned outside an outer edge of the semiconductor chip and inside the outer edge of the package base material in a plan view, the semiconductor chip being mounted on the package base material (FIG. 3A shows 11 mounted on 17); and
a second section (second section of 17 excluding portion of 17 under 11 and portion of 17 under 14) positioned outside the outer edge of the semiconductor chip and inside the first section in the plan view;
disposing a thermally conductive material (31; 31 is a material having fluidity, [0036])) having fluidity on the surface of the semiconductor chip.
Tsuchida does not explicitly disclose:
writing first information regarding the semiconductor package on the first section of the semiconductor package and second information regarding the semiconductor package on the second section,
wherein the first information and the second information is not written on a surface of the semiconductor chip.
However, Tsuchida teaches that 14 is a stiffener, [0031]
FIG. 2 shows the stiffener 14 is outside the sealing member 33 and away from the semiconductor chip 11 in the plan view.
In the same field of endeavor, Starkston teaches Embodiments of the invention however allow each stiffener in a panel to be marked with traceability marks before the start of the package assembly process. For instance, each stiffener in a panel of stiffeners may be pre-marked with traceability marks during its manufacturing. Thus, when the panel of stiffeners is attached to the panel of package substrates, the traceability mark is already exposed and a re-mark is not needed, [0026].
Starkston teaches a traceability mark is for identification purposes, [0026].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the stiffener 14 to have traceability marks (corresponding to the claimed first information) as taught by Starkston for identification purposes such as providing identification of the chip and/or package. As a result, the traceability marks would be written on stiffener 14 which would be outside 33 and not on the surface of the chip 11.
In the same field of endeavor Chul discloses the supporting stiffener 54 is provided at the center of its upper surface with a partial mark 56 (serving as a reference point) for guiding the correct seating direction of the interposer 20 to be mounted on the supporting stiffener 52 ) Are formed in a cross shape or the like using a laser processing method or the like, [0033].
Chul further discloses the support stiffener 54 is provided at its central portion with the upper surface of the support stiffener 54 in the form of a parting mark 56. The support stiffener 54 is provided with a delivery tool (not shown) for attracting the interposer and lowering it to the adhesive material 52 Of the support stiffener 54 can be accurately positioned on the upper surface of each corner of the supporting stiffener 54 by recognizing the partial mark 56 by using the conventional vision system, [0046].
FIGs. 2-4 show the mark 56 is on a top surface of the stiffener 54.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traceability marks on the stiffener 14 to be on its top surface as taught by Chul in order to improve its readability from a top view.
Further, Tsuchida discloses 16 are capacitors, [0031].
In the same field of endeavor, Engineering discloses The image above is of an electrolytic capacitor marked with “100μF,” meaning it has a capacitance of 100 microfarads (the μ prefix indicates 10−6). Expressed differently, this is 0.0001 farads; see pg. 4 top paragraph, see image at the bottom of pg. 3.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mark each capacitor 16 indicating its capacitance as taught by Engineering in order to make this information readily available, which would help in future diagnostics or repairs. As a result, a marking indicating capacitance would be written on the right capacitor 16 in FIG. 3A (corresponding to the second information) which is on a portion of the package base material 17, and this second information would be inside the sealing member 33 and toward the semiconductor chip 11 in the plan view but not on the surface of the semiconductor chip 11.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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