DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (2020/0020587), (hereinafter, Cheng).
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RE Claim 1, Cheng discloses a method of fabricating a vertically stacked nanosheet semiconductor device including epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate and patterning a gate structure. Cheng discloses in FIGS. 1-7 a semiconductor structure comprising:
a nanosheet 22 transistor with a source/drain (S/D) region 13, wherein the S/D region 13 has a substantially flat top surface, referring to FIGS. 4B and 5 that is adjacent to a dielectric cap layer 86 “composed of flowable oxide such as HSQ solution in MIBK” [0049], the dielectric cap layer 86 being placed directly above the S/D region 13 and materially different from a dielectric layer 76 “spacer” since it is “composed of SiBCN”, that surrounds sidewalls of the S/D region 13, hence meeting the claimed limitation is met. Although FIGS. 4 and 5 show a cross-section of the device show a sideview of the spacer 76, it is implicit that in 3D orientation, the spacer 76 surrounds source/drain region 13, hence the claimed limitation is met
RE Claim 2, Cheng discloses a semiconductor structure, wherein a cross-section of the S/D region 13 has at least one vertical edge and the at least one vertical edge substantially aligns with an edge of the dielectric cap layer 86, the cross-section being perpendicular to a gate length direction of the nanosheet 22 transistor, referring to FIGS. 4B and 5.
RE Claim 3, Cheng discloses a semiconductor structure, wherein the S/D region 13 has a vertical left edge and a vertical right edge when looking in a gate length direction of the nanosheet 22 transistor, the vertical left edge and the vertical right edge being substantially aligned with, respectively, a left edge and a right edge of the dielectric cap layer 86, referring to FIGS. 4B and 5.
RE Claim 4, Cheng discloses a semiconductor structure, wherein the S/D region 13 is formed through an epitaxial growth process [0035, 0040, 0041 and 0046-0048] and the vertical left edge and the vertical right edge of the S/D region 13 intersect directly with the substantially flat top surface, referring to FIGS. 4B and 5.
RE Claim 5, Cheng discloses a semiconductor structure, wherein the nanosheet 22 transistor comprises one or more nanosheets 22 [0032, 0037] and wherein the vertical left edge and the vertical right edge 104/106 of the S/D region are horizontally asymmetric to a horizontal center of the one or more nanosheets 66. Since the nanosheet channel 66 shifted more to the left side from the center line to a horizontal center of the one or more nanosheets limitation is met.
RE Claim 6, Cheng discloses a semiconductor structure, wherein the nanosheet transistor is a first nanosheet transistor “lower pFET transistor”, referring to FIGS. 1A-1C [0036-0037], further comprising a second nanosheet transistor positioned vertically above the first nanosheet transistor “upper nFET transistor” referring to FIGS. 1A-1C [0036], wherein a S/D region 13 of the second nanosheet transistor is separated from the S/D 13 region of the first nanosheet transistor by the dielectric cap layer 20.
RE Claim 7, Cheng discloses a semiconductor structure, wherein the first nanosheet transistor “lower pFET transistor” has a first metal gate 26 and the second nanosheet transistor “upper nFET transistor” has a second metal gate 26, referring to FIG. 1A [0037], wherein the first metal gate 26 and the second metal gate 26 are connected through a common gate metal, referring to FIG. 5 [0053].
RE Claim 8, Cheng discloses a semiconductor structure, wherein the S/D region 13 of the first nanosheet transistor and the S/D region 15 of the second nanosheet transistor have different cross-sectional shapes, referring to FIG. 1C when looking in a direction along a length of respective gate of the first and the second nanosheet transistor, i.e. lower and upper transistors pFET and nFET respectively, referring to FIG. 1C [0036].
RE Claim 15, Cheng discloses in FIGS. 1A-1C, 5 and 6A-6C [0036-0039 and 0052-0060] a semiconductor structure, comprising:
a first nanosheet transistor “lower pFET transistor” having a first source/drain (S/D) region 13, referring to FIGS. 1A-1C [0036-0037]; and
a second nanosheet transistor “upper nFET transistor” on top of the first nanosheet transistor, the second nanosheet transistor having a second S/D region 15, referring to FIGS. 1A-1C [0036-0037], the second S/D region 15 being separated from the first S/D region by a dielectric cap layer 20,
wherein the first S/D region 13 of the first nanosheet transistor has a substantially flat top surface adjacent to the dielectric cap layer and a cross-section perpendicular to a gate length direction of the first nanosheet transistor,
wherein the cross-section has at least one vertical edge that substantially aligns with an edge of the dielectric cap layer 20, referring to FIG. 1A-1C [0036].
RE Claim 16, Cheng discloses a semiconductor structure, wherein the first S/D region 13 of the first nanosheet transistor and the second S/D region 15 of the second nanosheet transistor have different cross-sectional shapes, referring to FIG. 1C, when looking in a direction along a length of respective gate of the first nanosheet transistor and the second nanosheet transistor, i.e. “lower pFET and upper nFET transistors”, referring to FIGS.1A-1C [0036-0037].
RE Claim 17, Cheng discloses a semiconductor structure, wherein, when looking in the gate length direction of the first nanosheet transistor, the first S/D region 13 has a vertical left edge and a vertical right edge that are substantially aligned with, respectively, a left edge and a right edge of the dielectric cap layer 20, referring to FIG. 1A.
RE Claim 18, Cheng discloses a semiconductor structure, wherein the vertical left edge and the vertical right edge of the first S/D region 13 are directly connected by the substantially flat top surface of the first S/D region, referring to FIG. 1A.
RE Claim 19, Cheng discloses a semiconductor structure, wherein the first nanosheet transistor “lower pFET transistor” comprises one or more nanosheets 22, referring to FIGS. 1A-1C [0036-0037], wherein the first S/D region 104/106 is horizontally asymmetrical to a horizontal center of the one or more nanosheets 22, with the nanosheet stack is shifted more the left side from the center line, to a horizontal center of the one or more nanosheets
RE Claim 20, Cheng discloses a semiconductor structure, wherein the first nanosheet transistor “lower pFET transistor” has a first metal gate 26 and second nanosheet transistors “upper pFET transistor” has a second metal gate 26, wherein the first metal gate 26 and the second metal gate 26 are connected through a common gate metal 96, referring to FIGS. 1A and 5 [0037, 0039 and 0053].
Response to Arguments
Applicant's arguments filed 08/29/2205 with respect to claims 1 and 15 have been fully considered but they are not persuasive. In the instant case, Cheng clearly disclose a nanosheet 22 transistor with a source/drain (S/D) region 13, wherein the S/D region 13 has a substantially flat top surface, referring to FIGS. 4B and 5 that is adjacent to a dielectric cap layer 86 “composed of flowable oxide such as HSQ solution in MIBK” [0049], the dielectric cap layer 86 being placed directly above the S/D region 13 and materially different from a dielectric layer 76 “spacer” since it is “composed of SiBCN”, that surrounds sidewalls of the S/D region 13. Thus, meeting the claimed limitations newly added to Claim 1.
Therefore, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, XIE et al. (US 2021/0134949) disclose a nanosheet semiconductor structure and method for forming the same, where the nanosheet semiconductor structure includes a substrate and a nanosheet stack comprising vertically oriented nanosheets. A gate structure contacts and wraps around the vertically oriented nanosheets. A source layer and a drain layer are each disposed adjacent to the nanosheet stack. An inner spacer is disposed in contact with a bottom surface of the nanosheet stack. The method includes forming an alternating pattern of first spacers and second spacers on a semiconductor stack. The first spacers and one or more underlying portions of the semiconductor stack are removed thereby forming a plurality of trenches each adjacent to one or more of the second spacers. The plurality of trenches defines a plurality of vertically oriented nanosheets. A plurality of sacrificial spacers are formed each in contact with one or more vertically oriented nanosheets of the plurality of vertically oriented nanosheets..
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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