DETAILED ACTION
*** The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
*** This office action is responsive to Applicant’s Election filed April 04, 2025. Claims 1-20 are pending.
Election/Restrictions
Applicant elected Invention Group I, Species Ia of claims 1-8, with traverse, in the Election dated April 04, 2025. Applicant traversed about the restriction requirement between claim 1 of Species Ia of Group I and claim 15 of Species Ib of Group I. In view of prior arts of record, after reconsideration, the restriction requirement between Species Ia (e.g., corresponding to claims 1-8) and Species Ib (e.g., corresponding to claims 15-20) of Invention Group I is hereby withdrawn. Accordingly, Group I includes product claims 1-8 and product claims 15-20 are considered and examined for patentability.
In view of the withdrawal of the restriction requirement of Species Ia and Species Ib of Group I, applicant(s) are advised any claim(s) drawn to invention of Group I in a continuation or divisional application may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See Jn re Ziegler, 44 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claims 9-14 of Group II are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made of claims 1-8 and 15-20 of Group I invention in the Election filed April 04, 2025. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, and because the election is implicitly “without traverse”, between Group I and Group II, the election between Group I and Group II has been treated as an election without traverse (MPEP § 818.03(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-8 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (2020/0020587).
Re independent claim 1, Cheng teaches (at Figs 1A-1C; para 36-39; Figs 5,6A-6C; para 52-60) a semiconductor structure comprising: a nanosheet transistor (17,19 in Figs 1A-1C, para 37,32 for nanosheet channel 22) with a source/drain (S/D) region (13 in Figs 1A-1C; para 36; 80 in Fig 3C, para 46-47), wherein the S/D region 13 has a substantially flat top surface (as shown in Figs 1A-1C) that is adjacent to a dielectric cap layer (20 in Figs 1A-1C; para 36), the dielectric cap layer 20 being placed directly above the S/D region (13 in Figs 1A-1C).
Re-claim 2, Cheng teaches wherein the S/D region (13 in Figs 1A-1C; para 36) has at least one vertical edge (as shown in Fig 1A) and the at least one vertical edge substantially aligns with an edge of the dielectric cap layer (20 in Fig 1A).
Re-claim 3, Cheng teaches wherein the S/D region (13 as shown in Fig 1A) has a vertical left edge and a vertical right edge, the vertical left edge and the vertical right edge being substantially aligned with, respectively, a left edge and a right edge of the dielectric cap layer (20 shown in Fig 1A).
Re-claim 4, Cheng teaches wherein the S/D region (13 in Figs 1A-1C; para 36; 80 in Fig 3C; para 46-47 for epitaxially growing the S/D region) is formed through an epitaxial growth process, and the vertical left edge and the vertical right edge of the S/D region (13 in Fig 1A) intersect directly with the substantially flat top surface (as shown in Fig 1A).
Re-claim 5, Cheng teaches wherein the nanosheet transistor (17,19 in Figs 1A-1C) comprises one or more nanosheets (para 37,32 for nanosheet channel 22) and wherein the vertical left edge and the vertical right edge of the S/D region (104/106 in Fig 6E; para 56-59) are horizontally asymmetric (S/D region 104/106 in Fig 6E are horizontally asymmetric, with the nanosheet channel stack 66 shifted more to left side from a center line) to a horizontal center of the one or more nanosheets.
Re-claim 6, Cheng teaches wherein the nanosheet transistor is a first nanosheet transistor (lower transistor in Figs 1A-1C, para 36-37 for pFET), further comprising a second nanosheet transistor (upper transistor in Figs 1A-1C, para 36-37 for nFET) positioned vertically above the first nanosheet transistor, wherein a S/D region (15 in Figs 1A-1C; para 36) of the second nanosheet transistor is separated from the S/D region (13 in Figs 1A-1C; para 36) of the first nanosheet transistor by the dielectric cap layer (20 in Figs 1A-1C; para 36).
Re-claim 7, Cheng teaches wherein the first nanosheet transistor (lower transistor in Figs 1A-1C, para 36-37 for pFET) has a first metal gate (26 in Fig 1A; para 37) and the second nanosheet transistors has a second metal gate (26 in Fig 1A; para 37), wherein the first metal gate and the second metal gate are connected through a common gate metal (26 in Fig 1A; para 37 and 39 for share the same gate 26 or the common gate; and Fig 5, para 53 for metal common gate 96 shared by both first and second transistors).
Re-claim 8, Cheng teaches wherein the S/D region (13 in Figs 1A-1C; para 36) of the first nanosheet transistor and the S/D region (15 in Figs 1A-1C; para 36) of the second nanosheet transistor have different cross-sectional shapes (as shown in Fig 1C) when looking in a direction along a length of respective gate of the first and the second nanosheet transistors (lower and upper transistors in Figs 1A-1C, para 36-37 for pFET) and nFET).
Re independent claim 15, Cheng teaches (at Figs 1A-1C; para 36-39; Figs 5,6A-6C; para 52-60) a semiconductor structure comprising: a first nanosheet transistor (lower transistor in Figs 1A-1C, para 36-37 for pFET) having a first source/drain (S/D) region (13 in Figs 1A-1C; para 36); and a second nanosheet transistor (upper transistor in Figs 1A-1C, para 36-37 for nFET) on top of the first nanosheet transistor, the second nanosheet transistor having a second S/D region (15 in Figs 1A-1C; para 36), the second S/D region being separated from the first S/D region by a dielectric cap layer (20 in Figs 1A-1C; para 36), wherein the first S/D region (13 in Figs 1A-1C; para 36) of the first nanosheet transistor has a substantially flat top surface adjacent to the dielectric cap layer 20 and has at least one vertical edge (as shown in Fig 1A for vertical edge of the first S/D region 13) that substantially aligns with an edge of the dielectric cap layer 20.
Re-claim 16, Cheng teaches wherein the first S/D region (13 in Figs 1A-1C; para 36) of the first nanosheet transistor and the second S/D region (15 in Figs 1A-1C; para 36) of the second nanosheet transistor have different cross-sectional shapes (as shown in Fig 1C), when looking in a direction along a length of respective gate of the first nanosheet transistor and the second nanosheet transistor (lower and upper transistors in Figs 1A-1C, para 36-37 for pFET) and nFET).
Re-claim 17, Cheng teaches wherein the first S/D region (13 as shown in Fig 1A) has a vertical left edge and a vertical right edge that are substantially aligned with, respectively, a left edge and a right edge of the dielectric cap layer (20 shown in Fig 1A).
Re-claim 18, Cheng teaches wherein the vertical left edge and the vertical right edge of the first S/D region (13 in Fig 1A) are directly connected by the substantially flat top surface (as shown in Fig 1A) of the first S/D region.
Re-claim 19, Cheng teaches wherein the first nanosheet transistor (lower transistor in Figs 1A-1C, para 36-37 for pFET) comprises one or more nanosheets (para 37,32 for nanosheet channel 22), wherein the first S/D region (104/106 in Fig 6E; para 56-59) is horizontally asymmetrical (S/D region 104/106 in Fig 6E are horizontally asymmetric, with the nanosheet channel stack 66 shifted more to left side from a center line) to a horizontal center of the one or more nanosheets.
Re-claim 20, Cheng teaches wherein the first nanosheet transistor (lower transistor in Figs 1A-1C, para 36-37 for pFET) has a first metal gate (26 in Fig 1A; para 37) and the second nanosheet transistors has a second metal gate (26 in Fig 1A; para 37), wherein the first metal gate and the second metal gate are connected through a common gate metal (26 in Fig 1A; para 37 and 39 for share the same gate 26 or the common gate; and Fig 5, para 53 for metal common gate 96 shared by both first and second transistors).
*********************
Prior arts cited of interest below but not relied upon are pertinent to the present application:
** Hong (2023/0101171) discloses a multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor (100L in Fig 1B) and a fin field-effect transistor (FinFET) (100U in Fig 1B) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers (110LN in Fig 1B) surrounded by a lower gate structure (115L in Fig 1B) except between the nanosheet layers, the FinFET includes at least one fin structure (110U in Fig 1B), of which at least top and side surfaces are surrounded by an upper gate structure (115U), and each of the lower and upper gate structures includes: a gate oxide layer (115U1/115L1 in Fig 1B) formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer (215L0 in Fig 1D, paragraph 63) formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.
** Xie (2023/0085628) discloses a hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion (115 in Fig 2) and a second stack portion (113 in Fig 2). The first stack portion includes first channels (108 in Fig 2). The second stack portion is stacked on the first stack portion, and includes second channels (108 in Fig 2) . The all-around gate (144 in Fig 14) includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension (147 in Fig 14) contacts the first gate portion and the second gate extension (149 in Fig 14) contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.
****************
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL M TRINH whose telephone number is (571) 272-1847. The examiner can normally be reached on M-F 9Am -5:30Pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached on (571) 272-8936. The central fax phone number is (703) 872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/MICHAEL M TRINH/Primary Examiner, Art Unit 2898
Prosecution Insights