DETAILED ACTION
This application, 18046088, attorney docket 2269-16370.1(2021134719), filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Micron Technology Inc., and claims priority from Provisional Application 63266022 , filed 12/27/2021. Claims 1, 3-6, 15-17, 19-22, and 24--25 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
Applicant has amended claims 1 and 15 and correctly argues that the art of record Pachamuthu does not teach a bit line with a tungsten first portion and a copper second portion overlying the first portion.
Applicant further argues that the combination of Pachamuthu with Ishibashi does not cure the deficiency of Pachamuthu to teach both metals in the bit line. Examiner disagrees. Ishibashi teaches a bitline that comprises a tungsten-containing liner (tungsten nitride) and a metal fill that may be copper. Ishibashi [0124]. The copper is formed over the liner, and therefore reads on the amended claim 1, which requires the inclusion of tungsten, not elemental tungsten. Likewise, applicant’s argument that claim 15 is distinguishes is not persuasive because the metal of Ishibashi is in a portion formed over the liner. Examiner notes the art of record (and subsequent search results) does not teach a tungsten layer formed in the bitline trench that is recessed to form a “plug” that is covered by a copper layer that extends entirely across the bitline trench, which is the arrangement disclosed but not claimed. Therefore. the previous rejection is withdrawn and a new rejection is presented below.
Applicant has amended claim 3 to replace the relative term “rough” with nonplanar, so the §112 rejection is withdrawn.
Likewise, applicant has amended claims 4 and 20 to replace the relative terms noted, and those §112 rejections are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-6, 15-17, 19, 21, 22, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Pachamuthu (U.S. 2013/0214415) in view of Ishibashi et al. (U.S.2011/0068318).
As for claim 1,
Pachamuthu teaches in figures 2 and 8a-9f, an apparatus, comprising:
an electrically insulating material (532);
bit lines (502/504/506 [0048]), in the electrically insulating material, the electrically insulating material defining air gaps (540) between the bit lines,
strings of memory cells (208, figure 4 extending into the page) extending at least substantially perpendicularly to the bit lines; and
contacts (220/224) electrically connecting the strings of memory cells to the bit lines.
Pachamuthu does not teach that at least some of the bit lines including tungsten in a first portion and copper in a second portion overlying the first portion (Pachamuthu does teach that the fill metal can be tungsten or copper [0030]).
However, Ishibashi teaches in figure 1 a bitline of copper and a barrier that comprises tungsten.
It would have been obvious to one skilled in the art at the effective filing date of this application to add the tungsten barrier of Ishibashi to the device of Pachamuthu to reduce copper diffusion. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 3,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 1, wherein an interface between the copper and the tungsten is non-planar. (it is u-shaped, bottom and sides of the copper contacts the liner).
As for claim 4,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 1 wherein:
a first interface between the copper and the tungsten in a first bit line of the bit lines is at a first distance from a bottom surface of the electrically insulating material, and a second interface between the copper and the tungsten in a second bit line of the bit lines is at a second distance from the bottom surface of the electrically insulating material, the second distance different than the first distance. (The bottom interface and side interfaces are different distances from the bottom surface of the insulating material.
As for claim 5,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 1, and Pachamuthu teaches a liner material (530) between the electrically insulating material and the bit lines.
As for claim 6,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 5, and Pachamuthu teaches in paragraph [0047] that tantalum nitride can be used for a liner 530.
As for claim 15,
Pachamuthu teaches an apparatus, comprising:
bit lines (502/504/506 [0048]) air gaps (540) between the bit lines;
word lines (WL0-WL3);
and a memory cell array including memory cells corresponding to intersections between the bit lines and the word lines. (Bit lines are above each block of word lines.)
Pachamuthu does not teach that the bitline comprises a lower portion including tungsten and an upper portion including copper;
However, Ishibashi teaches in figure 1 a bitline (BL) of copper (upper portion) and a barrier (38) that comprises tungsten.
It would have been obvious to one skilled in the art at the effective filing date of this application to add the tungsten barrier of Ishibashi to the device of Pachamuthu to reduce copper diffusion. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 16,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 15, and teaches in figure 9B a periphery circuitry electrically connected to the memory cell array via at least the bit lines.
As for claim 17,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 16, and teaches in paragraph [0069-0070] the periphery circuitry includes one or more of a column decoder, a sense amplifier, a transfer gate, an error correction control circuit, an input/output circuit, and a row decoder.
As for claim 19,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 15, and the combination makes obvious that grains of the tungsten protrude into the copper at interfaces between the tungsten and the copper. (Because the copper is deposited on the liner, the grains must interleave.)
As for claim 21,
Pachamuthu teaches in figures 1-4,
a memory cell array including memory cells (stacks at 150); and
bit lines over the memory cell array, the bit lines electrically connected to the memory cells,
the bit lines including a second electrically conductive material (522), which may be copper or tungsten [0030])
but does not teach a first electrically conductive material, the second electrically conductive material more electrically conductive than the first electrically conductive material.
However, Ishibashi teaches in figure 1 a bitline (BL) of copper (upper portion) and a barrier (38, lower portion) that comprises tungsten, where applicant teaches that copper is more conductive than tungsten.
It would have been obvious to one skilled in the art at the effective filing date of this application to add the tungsten barrier of Ishibashi to the device of Pachamuthu to reduce copper diffusion. One skilled in the art would have combined these elements with a reasonable expectation of success.
Pachamuthu does not teach the memory array is part of a computer system.
However, Examiner takes official notice that the use of a memory array in a computer system is an obvious application of a memory array.
As for claim 22,
Pachamuthu in view of Ishibashi makes obvious the computing system of claim 21, and in the combination, Pachamuthu teaches air gaps (540) between the bit lines.
As for claim 24,
Pachamuthu in view of Ishibashi makes obvious the computing system of claim 21, and Pachamuthu teaches a memory device (200) including the memory cell array and the bit lines.
As for claim 25,
Pachamuthu in view of Ishibashi makes obvious the computing system of claim 24, and the combination makes obvious one or more processors electrically connected to the memory device; one or more non-volatile data storage devices electrically connected to the one or more processors; and one or more output devices electrically connected to the one or more processors. All the components listed are inherent in a functional computer system.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As for claim 20,
Pachamuthu in view of Ishibashi makes obvious the apparatus of claim 15, and in the combination, Pachamuthu teaches an electrically insulating material (530) including the bit lines therein,
The prior art does not teach or make obvious an interface between a lower portion and an upper portion in one of the bit lines is at a different depth within the electrically insulating material than an additional interface between an additional lower portion and an additional upper portion in an additional one of the bit lines.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893