DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 17-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pachamuthu (USPGPUB DOCUMENT: 2013/0214415, hereinafter Pachamuthu) in view of Ishibashi (USPGPUB DOCUMENT: 2011/0068318, hereinafter Ishibashi) and Simsek-Ege (USPGPUB DOCUMENT: 2020/0066729, hereinafter Simsek-Ege).
Re claim 1 Pachamuthu discloses an apparatus, comprising: bit lines(502/504/506)[0048]; a material(532) between the bit lines(502/504/506)[0048], the material(532) mechanically supporting the bit lines(502/504/506)[0048]; air gaps(540) between the bit lines(502/504/506)[0048]; strings of memory cells(208 in Fig 4) extending at least substantially perpendicularly to the bit lines(502/504/506)[0048]; and contacts(220/224) electrically connecting the strings of memory cells(208 in Fig 4) to the bit lines(502/504/506)[0048].
Pachamuthu does not disclose an apparatus, comprising: bit lines(502/504/506)[0048] comprising copper; a low-k dielectric material(532) between the bit lines(502/504/506)[0048],
Ishibashi disclose in Fig 1 an apparatus, comprising: bit lines comprising copper[0124];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ishibashi to the teachings of Pachamuthu in order to develop better high-capacity, inexpensive semiconductor memory devices [0003, Ishibashi].
Pachamuthu and Ishibashi does not disclose an apparatus, comprising: a low-k dielectric material(532) between the bit lines(502/504/506)[0048],
Simsek-Ege disclose an apparatus, comprising: a low-k dielectric material(108)[0021] between the bit lines(104),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Simsek-Ege to the teachings of Pachamuthu in order to reduce undesirable electrical coupling [0004, Simsek-Ege].
Re claim 2 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 1, further comprising a subconformal dielectric material(532) between the bit lines(502/504/506)[0048], the subconformal dielectric material(532) defining the air gaps(540).
Re claim 3 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 2, wherein the subconformal dielectric material(532) and the air gaps(540) are at least substantially surrounded by the low-k dielectric material(532).
Re claim 4 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 1, wherein at least some of the bit lines(502/504/506)[0048] comprise tungsten[0124 of Ishibashi] in a first portion and the copper[0124 of Ishibashi] in a second portion.
Re claim 5 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 4, wherein an interface between the copper[0124 of Ishibashi] and the tungsten[0124 of Ishibashi] comprises grains of the tungsten[0124 of Ishibashi] protruding into the copper[0124 of Ishibashi].
Re claim 6 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 4, wherein a first interface between the copper[0124 of Ishibashi] and the tungsten[0124 of Ishibashi] in a first bit line of the bit lines(502/504/506)[0048] is misaligned with a second interface between the copper[0124 of Ishibashi] and the tungsten[0124 of Ishibashi] in a second bit line of the bit lines(502/504/506)[0048].
Re claim 7 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 1, further comprising a liner material between the low-k dielectric material(532) and the bit lines(502/504/506)[0048].
Re claim 8 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 7, wherein the liner material comprises tantalum[0033] or tantalum[0033] nitride.
Re claim 17 Pachamuthu discloses an apparatus, comprising: bit lines(502/504/506)[0048]; a material(532) between the bit lines(502/504/506)[0048] and defining air gaps(540) between the bit lines(502/504/506)[0048]; a material(532) between the bit lines(502/504/506)[0048] and the air gaps(540); word lines(WL0-WL3); and a memory cell array comprising memory cells corresponding to intersections between the bit lines(502/504/506)[0048] and the word lines(WL0-WL3).
Pachamuthu does not discloses bit lines(502/504/506)[0048] comprising copper; a subconformal dielectric material(532) between the bit lines(502/504/506)[0048] and defining air gaps(540) between the bit lines(502/504/506)[0048]; a low-k dielectric material(532) between the bit lines(502/504/506)[0048] and the air gaps(540)
Ishibashi disclose in Fig 1 an apparatus, comprising: bit lines comprising copper[0124];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ishibashi to the teachings of Pachamuthu in order to develop better high-capacity, inexpensive semiconductor memory devices [0003, Ishibashi].
Pachamuthu and Ishibashi does not disclose a subconformal dielectric material(532) between the bit lines(502/504/506)[0048] and defining air gaps(540) between the bit lines(502/504/506)[0048]; a low-k dielectric material(532) between the bit lines(502/504/506)[0048] and the air gaps(540)
Simsek-Ege disclose a low-k dielectric material(108)[0021 of Simsek-Ege] between the bit lines(104 of Simsek-Ege) and the air gaps(148 of Simsek-Ege)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Simsek-Ege to the teachings of Pachamuthu in order to reduce undesirable electrical coupling [0004, Simsek-Ege]. In doing so, a subconformal dielectric material(108)[0021 of Simsek-Ege] between the bit lines(502/504/506)[0048] and defining air gaps(540) between the bit lines(502/504/506)[0048];
Re claim 18 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 17, further comprising periphery circuitry electrically connected to the memory cell array via at least the bit lines(502/504/506)[0048], the periphery circuitry comprising one or more of a column decoder, a sense amplifier, a transfer gate, an error correction control circuit, an input/output circuit, and a row decoder[0068].
Re claim 19 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 17, wherein the bit lines(502/504/506)[0048] comprise: a first portion comprising the copper[0124 of Ishibashi]; and a second portion comprising tungsten[0124 of Ishibashi].
Re claim 20 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 19, wherein grains of the tungsten[0124 of Ishibashi] protrude into the copper[0124 of Ishibashi] at interfaces between the tungsten[0124 of Ishibashi] and the copper[0124 of Ishibashi].
Re claim 21 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 19, wherein interfaces between the tungsten[0124 of Ishibashi] and the copper[0124 of Ishibashi] are misaligned from bit line to bit line.
Re claim 22 Pachamuthu, Ishibashi and Simsek-Ege disclose the apparatus of claim 17, wherein the subconformal dielectric material(532) is between the low-k dielectric material(532) and the air gaps(540).
Re claim 23 Pachamuthu discloses a computing system, comprising: a memory cell array comprising memory cells; bit lines(502/504/506)[0048] over the memory cell array, the bit lines(502/504/506)[0048] electrically connected to the memory cells, the bit lines(502/504/506)[0048] comprising a first electrically conductive material and a second electrically conductive material(522), and a material(532) between the bit lines(502/504/506)[0048].
Pachamuthu does not disclose the second electrically conductive material(522) more electrically conductive than the first electrically conductive material; and a low-k dielectric material
Ishibashi disclose in Fig 1 the second electrically conductive material(copper)[0124 of Ishibashi] more electrically conductive than the first electrically conductive material(tungsten)[0124 of Ishibashi];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ishibashi to the teachings of Pachamuthu in order to develop better high-capacity, inexpensive semiconductor memory devices [0003, Ishibashi].
Pachamuthu and Ishibashi does not disclose a low-k dielectric material
Simsek-Ege disclose an apparatus, comprising: a low-k dielectric material(108)[0021]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Simsek-Ege to the teachings of Pachamuthu in order to reduce undesirable electrical coupling [0004, Simsek-Ege].
Re claim 24 Pachamuthu, Ishibashi and Simsek-Ege disclose the computing system of claim 23, further comprising a subconformal dielectric material(532) between the bit lines(502/504/506)[0048], the subconformal dielectric material(532) defining air gaps(540) between the bit lines(502/504/506)[0048].
Re claim 25 Pachamuthu, Ishibashi and Simsek-Ege disclose the computing system of claim 23, wherein the second electrically conductive material(522) comprises copper[0124 of Ishibashi].
Re claim 26 Pachamuthu, Ishibashi and Simsek-Ege disclose the computing system of claim 23, further comprising: one or more processors[0073] electrically connected to a memory device comprising the memory cell array and the bit lines(502/504/506)[0048], and the low-k dielectric material(532); one or more non-volatile data storage devices electrically connected to the one or more processors[0073]; and one or more output devices electrically connected to the one or more processors[0073].
Response to Arguments
Applicant’s arguments with respect to claim 1-8, 17-26 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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