Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 01/23/2026, in which: claims 11, 24, 28 and 29 are amended; and the rejection of the claims are traversed. Claims 11-28 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments, filed 01/23/2026, with respect to the rejection(s) of claim(s) 11 and 24 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Park et al, US 20210057444.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-22 and 24-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al, US 20210327885, hereafter ‘Hossain’ in view of Yamaguchi et al, US 20210358937, hereafter ‘Yamaguchi’ in further view of Park et al, US 20210057444, hereafter ‘Park’.
Regarding claim 11, Hossain discloses : A semiconductor device, comprising: a source structure including a memory cell region and a first connection region(Fig. 2, #165 to include regions #135 and #140); a stack structure disposed on the source structure and including a first gate stack group and a second gate stack group on the first gate stack group(#110a first stack and #110B second stack), the first gate stack group including a plurality of first gate electrodes, and the second gate stack group including a plurality of second gate electrodes(#125 replaced with conductive material through replacement gate process [0035], #125 to be replaced with #190[0052]); a plurality of channel structures penetrating through the stack structure and connected to the source structure, on the memory cell region(Channel structure located in #135 connected to #165); and disposed between the plurality of channel structures and the plurality of first dummy vertical structures(Pillars #105 to pass through #110a and #110b), wherein each of the plurality of channel structures includes a lower channel structure passing through the first gate stack group and an upper channel structure passing through the second gate stack group(Pillars #105 to pass through #110a and #110b),the plurality of second dummy vertical structures penetrate through an uppermost second gate electrode among the plurality of second gate electrodes(#105b to pass through #110b), and lower ends of the plurality of second dummy vertical structures are disposed on a level higher than a level of at least one of the plurality of first gate electrodes(#105b shown to at least be higher than the bottom most gate electrode #125 of stack #110a).
Hossain does not disclose : a plurality of first dummy vertical structures passing through at least a portion of the stack structure, on the first connection region; and a plurality of second dummy vertical structures passing through the second gate stack group, on the memory cell region, and a vertical length of at least one of the plurality of first dummy vertical structures is different from a vertical length of at least one of the plurality of second dummy vertical structures.
However, in the same field of endeavor, Yamaguchi teaches : a plurality of first dummy vertical structures passing through at least a portion of the stack structure, on the first connection region(Fig. 10a, #20 shown to pass through first and second tier structures [0192]) with a first connection region #200);
Park teaches : a plurality of second dummy vertical structures passing through the second gate stack group, on the memory cell region(Fig 12b, #DCH through #GS2), and a vertical length of at least one of the plurality of first dummy vertical structures is different from a vertical length of at least one of the plurality of second dummy vertical structures(#DCH may be adjustable by adjusting #L3 [0100]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yamaguchi and Park to Hossain to have dummy structures in multiple regions throughout a memory device to that may be adjusted to different lengths to provide structural support (Park [0095] , Yamaguchi [0192]), since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). See MPEP 2144.04.
Regarding claim 12, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Yamaguchi further teaches : wherein the plurality of first(Fig. 15a, #146) and second gate electrodes(#246) extending in a first direction to provide first and second pad regions(Fig. 10a #142 and #242 shown to extend , respectively, the first and second pad regions forming a step structure on the first connection region(#146 and #246 shown to extend to provide a surface for contact with via structures #86 and forming a step structure), and the plurality of first dummy vertical structures pass through the first and second pad regions(#20 shown to pass through first tier stack (#132 and #146 ) and second tier stack (#232 and #246).
Regarding claim 13, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 12.
Hossain further teaches : wherein the plurality of second dummy vertical structures are spaced apart from the first and second pad regions(Fig. 2 , #105b are not disposed in a pad/staircase region)
Regarding claim 14, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Hossain further teaches : wherein the plurality of second dummy vertical structures are spaced apart from the plurality of first gate electrodes(Fig. 2, #105b shown to be spaced apart from a plurality of #125 of stack #110a).
Regarding claim 15, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Hossain further teaches : wherein each of the plurality of channel structures includes a bent portion provided by a difference between a width of an upper end of the lower channel structure and a width of a lower end of the upper channel structure(Fig. 2, #105a and #105b configured in region #135 to be channel structures where the width of the lower end of #105b is shown to be smaller than the upper end of #105a).
Regarding claim 16, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Hossain teaches : wherein the plurality of second dummy vertical structures include a first vertical pattern and a second vertical pattern(Fig. 2, #145b close to #105.
Park teaches : wherein the first vertical pattern is disposed closer to the plurality of channel structures than the second vertical pattern, and a vertical length of the first vertical pattern is greater than a vertical length of the second vertical pattern(The vertical length of a dummy structure through a gate stack is adjustable [0100]).
Regarding claim 17, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Hossain further teaches : The semiconductor device of Claim 11, wherein the source structure further includes a second connection region(#140), and the stack structure further includes a plurality of first sacrificial layers disposed on a same level as the plurality of first gate electrodes and a plurality of second sacrificial layers disposed on a same level as the plurality of second gate electrodes, on the second connection region(#125 is a nitride material that is replaced with conductive material by a replacement gate process which makes #125 a sacrificial layer. #125 appears in both stack #110a and #110b).
Regarding claim 18, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 17.
Hossain further teaches : further comprising, on the second connection region, a plurality of third dummy vertical structures passing through the plurality of second sacrificial layers and having lower ends disposed on a level higher than a level of at least one of the plurality of first sacrificial layers(#105b Dummy structure of region #140 to be disposed on a level of at least one of layer #125).
Regarding claim 19 Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 18.
Hossain further teaches : wherein the plurality of third dummy vertical structures are spaced apart from the plurality of first sacrificial layers(Fig. 2, Dummy structure of region #140 are spaced apart from layer #125 of stack #110a).
Regarding claim 20, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 18.
Hossain further teaches : further comprising a source contact structure penetrating through the plurality of first and second sacrificial layers and connected to the source structure, on the second connection region(Fig. 4, #175a shown to penetrate layers #110a and #110b, material of #175 may function as interconnect to the source #165 [0043]).
Regarding claim 21, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 20.
Hossain further teaches : wherein the source contact structure is disposed between the plurality of third dummy vertical structures(Fig. 5B, #175a shown to be disposed between a plurality of #105b which are dummy vertical channels in region #140 [0050]).
Regarding claim 22, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Yamaguchi further teaches : wherein each of the plurality of channel structures includes a core insulating layer(Fig. 9H, #60 includes #62), a channel layer covering side surfaces of the core insulating layer(#602 covers #62), and a gate dielectric layer between the channel layer and the plurality of first and second gate electrodes(#52 between #602 and #132 and #232) , and each of the plurality of second dummy vertical structures includes a dummy core insulating layer, a dummy channel layer covering side surfaces of the dummy core insulating layer, and a dummy gate dielectric layer between the dummy channel layer and the plurality of second gate electrodes(#20 can be the same as the formation of channel structures #58 [0170]).
Regarding claim 24, Hossain discloses : A semiconductor device, comprising: a source structure including a memory cell region(Fig. 2, #165 to include #135), a first connection region(#140); a plurality of gate electrodes stacked on the memory cell region of the source structure (#125 replaced with conductive material by replacement gate process [0035]), the plurality of gate electrodes including a first gate stack group and a second gate stack group on the first gate stack group(Stack groups to include #110a and #110b), a plurality of channel structures connected to the source structure by penetrating through the plurality of gate electrodes, on the memory cell region(#105 connected to #165 penetrating stacks #110a and #110b);
Hossain does not disclose : a second connection region; and including pad regions extending in a first direction and forming a step structure on the first connection region, a plurality of sacrificial layers stacked on the second connection region of the source structure and disposed on a same level as the gate electrodes, the plurality of sacrificial layers including a first sacrificial stack group and a second sacrificial stack group on the first sacrificial stack group, a plurality of first dummy vertical structures passing through the pad regions of the plurality of gate electrodes, on the first connection region; and a plurality of second dummy vertical structures passing through the second sacrificial stack group, on the second connection region; and a plurality of third dummy vertical structures on the memory cell region, wherein a vertical length of at least one of the plurality of first dummy vertical structures and/or at least one of the plurality of second dummy vertical structures is different from a vertical length of at least one of the plurality of third dummy vertical structures.
However, in the same field of endeavor, Yamaguchi teaches : a second connection region; and including pad regions extending in a first direction and forming a step structure on the first connection region(Fig. 10a, step structure formed by extending layers #132, #142, #232, and #242), a plurality of sacrificial layers stacked on the second connection region of the source structure and disposed on a same level as the gate electrodes(#132 and #232 are sacrificial layers), the plurality of sacrificial layers including a first sacrificial stack group and a second sacrificial stack group on the first sacrificial stack group(#132 is of the first alternating stack and #232 is of the second alternating stack [0136]), a plurality of first dummy vertical structures passing through the pad regions of the plurality of gate electrodes, on the first connection region(#20 to pass through a first stack of #132 and #142 and a second stack of #232 and #242).
Park teaches : a plurality of second dummy vertical structures passing through the second sacrificial stack group, on the second connection region(Fig. 5a #DCH through sacrificial layers #180); and a plurality of third dummy vertical structures on the memory cell region(Fig. 12b, #DCH in #CELL), wherein a vertical length of at least one of the plurality of first dummy vertical structures and/or at least one of the plurality of second dummy vertical structures is different from a vertical length of at least one of the plurality of third dummy vertical structures(Lengths of #DCH may be adjusted based on #L3 [0100]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yamaguchi and Park to Hossain to have dummy structures in multiple regions throughout a memory device to have different lengths to provide structural support (Park [0095] , Yamaguchi [0192]), since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). See MPEP 2144.04.
Regarding claim 25, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 24.
Hossain further teaches : wherein lower ends of the plurality of second dummy vertical structures are disposed on a level higher than a level of at least one of the plurality of sacrificial layers of the first sacrificial stack group(Fig. 2, #105b of #140 disposed on a stack higher than #110a).
Regarding claim 26, Hossain as modified by Yamaguchi Park discloses : The semiconductor device of Claim 24.
Hossain further teaches : further comprising a source contact structure connected to the source structure by penetrating through the first and second sacrificial stack groups, on the second connection region(Fig. 4, #175a penetrates #110a and #110b and may be configured to electrically connect to the source [0043].
Regarding claim 27, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 24.
Hossain further teaches : wherein the plurality of second dummy vertical structures are spaced apart from the plurality of sacrificial layers of the first sacrificial stack group(Pillar #105b only penetrates #110b, away from stack #110a).
Regarding claim 28, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 24.
Hossain further teaches : wherein the plurality of third dummy vertical structures is spaced apart from the pad regions and penetrates through the second gate stack group(Fig. 2, Pillar #105b shown only to penetrate one stack #110b of a two-tier stack).
Claim 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al, US 20210327885, hereafter ‘Hossain’ in view of Yamaguchi et al, US 20210358937, hereafter ‘Yamaguchi’ in further view of Park et al, US 20210057444, hereafter ‘Park’ in further view of Ravikirthi, US 9881929, hereafter ‘Ravikirthi’.
Regarding claim 23, Hossain as modified by Yamaguchi and Park discloses : The semiconductor device of Claim 11.
Hossain as modified by Yamaguchi and Park does not disclose : wherein the stack structure further includes a third gate stack group between the first gate stack group and the second gate stack group; the third gate stack group includes a plurality of third gate electrodes, and each of the plurality of channel structures further includes an intermediate channel structure passing through the third gate stack group and connected to the lower channel structure and the upper channel structure.
However, in the same field of endeavor, Ravikirthi teaches : wherein the stack structure further includes a third gate stack group between the first gate stack group and the second gate stack group(Fig. 28 method of multi-tier stack can be repeated over multiple tier to form memory stack structures [Col. 30 line 25-41]; the third gate stack group includes a plurality of third gate electrodes(third tier to include #346), and each of the plurality of channel structures further includes an intermediate channel structure passing through the third gate stack group and connected to the lower channel structure and the upper channel structure(Fig. 28, #55 shown to pass through all three stacks).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Ravikirthi to Hossain, Yamaguchi and Park to include a third memory stack structure with a channel structure passing through all three stacks.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897