DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 9-12 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Hsieh et al (US 2021/0202389).
A semiconductor assembly comprising:
a first die (Fig.9 (I1) and [0016- first interposer/0101- teaching the interposers may be chiplets- a chiplet is a die]) having a front side metallization layer (Fig.9 (CS1) and [0018]);
a second die (Fig.9 (C1) and 0029/0031]) having a front side metallization layer (Fig.9 (B1) and [0080- teaching direct bonding; see also 0030]) bonded directly to the front side metallization layer (Fig.9 (CS1) and [0018]) of the first die (Fig.9 (I1)and [ 0101- teaching the interposers may be chips]);
a third die (Fig.9 (I2) and [0021-second interposer] see also 0101- teaching the interposers may be chiplets- chiplets are dies]) co-planar with the first die (Fig.9 (I1) and [0016]) and having a front side metallization layer (Fig.9 (CS2) and [0021]);
and an interconnect die (Fig.9 (100) and [0037]) having a metallization layer (Fig.9 (B1) and [0080- teaching direct bonding; see also 0030]) coupled directly to the front side metallization layer (Fig.9 (CS1) and [0018]) of the first die (Fig.9 (I1) and [0016]), wherein the metallization layer (Fig.9 (B1) and [0080- teaching direct bonding; see also 0030]) of the interconnect die (Fig.9 (100) and [0037]) is coupled directly to the front side metallization layer of the third die (Fig.9 (CS2) and [0021]).
2. (Original) The semiconductor assembly of claim 1, wherein the first die (Fig.9 (I1) and [0016]) further includes a set of through-silicon vias (Fig.9 (TSV1) and [0017]) coupled to the front side metallization layer (Fig.9 (CS1) and [0018]) of the first die (Fig.9 (I1) and [0016]).
3. (Original) The semiconductor assembly of claim 2, wherein the first die (Fig.9 (I1) and [0016]) further includes a back side metallization layer (Fig.10 (RDL2) and [0053/0081- RDL2 is interpreted as a backside metallization layer and is connected to the TSVs in Fig.10]) and one or more of the through-silicon vias (Fig.9 (TSV1) and [0017]) are coupled to the back side metallization layer (Fig.10 (RDL2) and [0081]).
4. (Original) The semiconductor assembly of claim 3, further comprising one or more solder bumps (Fig.10 (B2) and [0053/0081]) coupled to the back side metallization layer (Fig.10 (RDL2) and [0053/0081) of the first die (Fig.9 (I1) and [0016]).
5. (Original) The semiconductor assembly of claim 2, wherein the front side metallization layer of the first die is bonded to the front side metallization layer of the second die using a hybrid bond.
6. (Original) The semiconductor assembly of claim 5, wherein a pitch of interconnections between the front side metallization layer (Fig.9 (CS1) and [0018]) of the first die (Fig.9 (I1) and [0016]) and the front side metallization layer (Fig.9 (B1) and [0080]) of the second die (Fig.9 (C1) and 0029/0031]) is different than a pitch of the through-silicon vias (Fig.9 (TSV1) and [0017]).
9. (Currently Amended) The semiconductor assembly of claim 1,wherein the metallization layer (Fig.9 (B1) and [0080 of the interconnect die (Fig.9 (100) and [0037]) is bonded to a front side metallization layer (Fig.9 (CS2) and [0021]) of the third die (Fig.9 (I2) and [0021]).
10. (Original) The semiconductor assembly of claim 1, wherein a thickness of the first die (Fig.9 (I1) and [0016]) is greater than a thickness of the second die (Fig.9 (C1) and 0029/0031]).
11. (Original) The semiconductor assembly of claim 1, wherein a portion of the front side metallization layer (Fig.9 (B1) and [0080]) of the second die (Fig.9 (C1) and 0029/0031]) is bonded to the front side metallization layer (Fig.9 (CS1) and [0018]) of the first die (Fig.9 (I1) and [0016]) and another portion of the front side metallization layer (Fig.9 (B1) and [0080]) of the second die (Fig.9 (C1) and 0029/0031]) is bonded to a front side metallization layer (Fig.9 (CS2) and [0021]) of a third die (Fig.9 (I2) and [0021]) that is co- planar with the first die (Fig.9 (I1) and [0016]).
12. (Original) The semiconductor assembly of claim 1, wherein the second die (Fig.9 (C1) and 0029/0031]) is on top of the first die (Fig.9 (I1) and [0016]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US 2021/0202389) in further view of Chen et al (US 2022/0278074).
Hsieh teaches the limitations of claims 1-2 as cited above.
Further in regards to claim 31, Hsieh teaches wherein a density of the interconnections between the front side metallization layer (Fig.9 (CS1) and [0018]) of the first die (Fig.9 (I1) and [0016]) and the front side metallization (Fig.9 (B1) and [0080]) layer of the second die (Fig.9 (C1) and 0029/0031]) is greater than a density of interconnections at a back side (Fig.10 (RDL2) and [0053/0081) of the first die (Fig.9 (I1) and [0016]).
However Hsieh fails to explicitly teach the limitations of claims 5 and 31 as recited below:
5. (Original) The semiconductor assembly of claim 2, wherein the front side metallization layer of the first die is bonded to the front side metallization layer of the second die using a hybrid bond.
31. (New) The semiconductor assembly of claim 5, wherein the hybrid bond is a permanent bond that combines a dielectric bond with embedded metal to form interconnections between the first die and the second die.
However, in regards to claim 5, Chen teaches a similar method of bonding chips and teaches wherein the front side metallization layer of the first die is bonded to the front side metallization layer of the second die using a hybrid bond [0055].
In regards to claim 31, Chen teaches:wherein the hybrid bond is a permanent bond that combines a dielectric bond with embedded metal to form interconnections between the first die and the second die [0055- implicit that hybrid bonding is permanent and includes both dielectric and metal bonding- hence hybrid bonding] .
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Hsieh’s teachings to include hybrid bonding as taught by Chen because such hybrid bonding techniques are a well-known and commonly used in chip stacking as an alternative to solder bonding as Chen discloses [0055].
Response to Arguments
Applicant’s arguments with respect to the above claims have been considered but are moot because the new ground of rejection.
The Examiner reached out to the Applicant on 3/30/26 suggesting to make a more substantial amendment to the claims in efforts to expedite prosecution on the merits (to make a more substantial amendment and place the Application closer to allowance) , the Examiner suggested the amendments as follows:
(Currently Amended) A semiconductor assembly comprising:
a first die having a front side metallization layer;
a second die having a front side metallization layer bonded directly to the front side metallization layer of the first die;
a third die co-planar with the first die and having a front side metallization layer; [and]
a fourth die co-planar with the second die and having a front side metallization layer bonded directly to the front side metallization layer of the third die;
a gap filling material formed between the first and third dies and having a top surface which is coplanar to a top surface of the front side metallization layers of the first and third dies;
an interconnect die vertically stacked over the gap filling material and between with the second and fourth dies and having a metallization layer coupled directly to the front side metallization layers of the first and third dies, and
wherein the metallization layer of the interconnect die has a reduced thickness compared to the front side metallization layers of the first and third dies. [is coupled directly to the front side metallization layer of the third die].
Cancel claims 9
21. (Withdrawn) A semiconductor assembly comprising:
a first die having a front side metallization layer;
a second die having a front side metallization layer bonded directly to the front side metallization layer of the first die; and
a third die co-planar with the first die and having a front side metallization layer; [and]
a fourth die co-planar with the second die and having a front side metallization layer bonded directly to the front side metallization layer of the third die;
a gap filling material formed between the first and third dies and having a top surface which is coplanar to a top surface of the front side metallization layers of the first and third dies;
an interconnect die vertically stacked over the gap fill material and between the second and fourth dies and having a metallization layer which is coupled directly to a portion of the front side metallization layers of the first and third dies, and
wherein the metallization layer of the interconnect die has a reduced thickness compared to the front side metallization layers of the second and fourth dies. [an interconnect die having a metallization layer coupled to the front side metallization layer of the first die].
Cancel claims 22-23; 29.
Applicant denied the opportunity to expedite prosecution. The amount of prior art in existence in chip stacking is quite substantial and the office’s time is highly valued. The Examiner humbly requests that the Applicant reconsider the above proposed amendment and assist the office in expediting prosecution on the merits.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al (US 2021/0249380) Uzoh et al (US 2017/0338214) and Yu et al (US 20180158749) teach similar stacked die structures with spacers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
11/11/25
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