DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of “Species A (claims 1-3, 6-10 and 13-20)” in the reply filed on January 14, 2026, is acknowledged. Claims 4-5 and 11-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being obvious over US 2011/0156224 A1; Rokuhara et al.; 06/2011; (“224”) in view of US 2023/0207439 A1; Elsherbini et al.; 06/2023; (“439”).
Regarding Claim 1. 224 teaches in Fig. 1 about a microelectronic assembly, comprising:
a first substrate (item 20) and at least one inductor (item L), the first substrate having a first side (bottom of item 20) and an opposing second side (top of item 20);
a second substrate (item 10) coupled to the first side of the first substrate (item 10 coupled to the bottom side of item 20); and
an IC die (first subset of the plurality of IC dies item 30) is directly coupled to the second side of the first substrate (item 30 is directly coupled to the top side of item 20).
224 does not teach about a microelectronic assembly, comprising:
a first substrate comprising glass;
a plurality of integrated circuit (IC) dies,
wherein:
a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and
a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.
439 teaches in Figs. 1 and 6A about a microelectronic assembly, comprising:
a first substrate comprising glass (Fig. 1, item 104, “glass substrate”, [0025], Ln. 4);
a plurality of integrated circuit (IC) dies (Fig 6A, items left item 620, right item 620, and item 665),
wherein:
a second subset (Fig. 6A, right item 420) of the plurality of IC dies is directly coupled to the second substrate (Fig. 6A, item 660) adjacent to the first substrate, and
a third subset (Fig. 6A, item 665) of the plurality of IC dies is embedded in the second substrate (Fig. 6A, item 665 is embedded in item 660) between the first substrate and the second subset of the plurality of IC dies.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the first glass substrate and the plurality of integrated circuit dies of 439 to provide a core glass material for the first substrate so the plurality of integrated circuit dies can be attached to the same in 224 since a “glass substrate enables finer pitched vias to be manufactured in a cost effective manner” as taught by 439 in [0025], Ln. 4-6.
Regarding Claim 9. 224 teaches in Fig. 1 about a substrate, comprising:
buildup layers (items 22 and 23) on a first side (top side) and an opposing second side (bottom side) of the core (item 21); and
outer layers on the first side (“It is to be noted that the wiring layer created on the opposite side for the insulation substrate 22 is not shown in the cross-sectional diagram of FIG. 1”, [0065]) and the opposing second side (“It is to be noted that the wiring layer created on the opposite side for the insulation substrate 23 is not shown in the cross-sectional diagram of FIG. 1”, [0067]) of the core;
an inductor (item L) in the core (item L is within core item 21),
wherein:
the buildup layers comprise an organic dielectric material (insulating material of items 22 and 23) and conductive vias (items 24) in the organic dielectric material (via items 24 within items 22 and 23),
the buildup layers are between the core and the outer layers (layer items 22 and 24 are between the core item 23 and the outer layers not shown in Fig. 1 as stated in [0065] and [0067]), and
a subset of the conductive vias (at least farthest left via item 24) in the buildup layer on the first side of the core conductively couple the inductor to the conductive bond-pads in the solder resist material on the first side of the core (“It is to be noted that the wiring layer created on the opposite side for the insulation substrate 23 is not shown in the cross-sectional diagram of FIG. 1”, [0067]).
224 does not teach about a substrate, comprising:
a core of a glass material;
wherein:
the outer layers comprise solder resist material and conductive bond-pads in the solder resist material.
439 teaches in Figs. 1, 2B and 4I about a substrate, comprising:
a core of a glass material (Fig. 1, item 104, “glass substrate”, [0025], Ln. 4);
wherein:
the outer layers comprise solder resist material (Fig. 2B, at least layer items 216 and 232) and conductive bond-pads (Fig. 4I, pad items 443) in the solder resist material.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the core of glass material substrate and the outer layers of 439 to provide a core glass material for the substrate and conductive bond-pads in the solder resist material of the core in 224 since a “glass substrate enables finer pitched vias to be manufactured in a cost effective manner” as taught by 439 in [0025], Ln. 4-6.
Claim 16 is rejected under 35 U.S.C. 103 as being obvious over US 2023/0207439 A1; Elsherbini et al.; 06/2023; (“439”) in view of US 2020/0395280 A1; Chen et al.; 12/2020; (“280”).
Regarding Claim 16. 439 teaches in Fig. 1 about a microelectronic assembly, comprising:
a first substrate (item 102) having a medial region (horizontally central region of item 102) and a peripheral region (horizontally outer edge region of item 102) around the medial region (horizontally outer edge region of item 102 is around de horizontally central region of item 102);
an interposer (item 104) coupled to the medial region of the first substrate (item 104 coupled to the medial region of item 102), a first plurality of IC dies (items 120) being coupled to a side of the interposer opposite to the first substrate (items 120 coupled to a side of item 104 opposite to item 102);
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524
731
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Fig. 1, annotated by Examiner from Elsherbini et al., “439”
439 does not teach about a microelectronic assembly, comprising:
a second plurality of IC dies in the peripheral region of the first substrate; and
a plurality of second substrates coupled to the first substrate and the second plurality of IC dies such that each second substrate is between the first substrate and a corresponding IC die in the second plurality of IC dies,
wherein:
each second substrate comprises a core of glass and at least one inductor embedded in the core, and
the inductor is part of a power management circuit in the microelectronic assembly.
280 teaches in Fig. 5 about a microelectronic assembly, comprising:
a second plurality of IC dies (upper items 220 and 230) in the peripheral region of the first substrate (substrate item FS1); and
a plurality of second substrates (lower most items 220 and 230) coupled to the first substrate and the second plurality of IC dies such that each second substrate is between the first substrate and a corresponding IC die in the second plurality of IC dies (lower most items 220 and 230 are between the item FS1 and the upper items 220 and 230),
wherein:
each second substrate comprises a core of glass and at least one inductor (“semiconductor dies 220, 230 include … inductors”, [0075], Ln. 4-7) embedded in the core, and
the inductor is part of a power management circuit in the microelectronic assembly (“semiconductor dies 220 and 230 include … power systems,”, [0075], Ln. 27-34).
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414
657
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Fig. 5, annotated by Examiner from Chen et al., “280”
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the second plurality of IC dies and the plurality of second substrates of 280 to provide a more compact and dense IC integration in 439 in order “to respond to the increasing demand for miniaturization, higher speed and better electrical performance” as taught by 280 in [0001], Ln. 9-10.
Allowable Subject Matter
Claims 2-3,6-8,10,13-15 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/ Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897