DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-14 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma (US 2021/0134705 A1, hereinafter Ma ‘705).
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With respect to Claim 1 Ma ‘705 discloses a through-silicon via (TSV)-Bump structure (Fig 1-14), comprising:
a TSV (108a, Fig 13, Para [0020]) in a semiconductor substrate (100a, Fig 13, Para [0020]), wherein
the TSV (108a) is at a position deeper than a surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a)(annotated Fig 13 of Ma ‘705 discloses TSV 108a at a position deeper than top of 100a),
the TSV (108a) includes a conductive portion (106, Fig 13, Para [0032]) vertically extending (106 vertically extending in 100a disclosed in Fig 13) in the semiconductor substrate (100a) and an insulating liner (104a, Fig 13, Para [0032]) vertically extending (104a vertically extending in 100a disclosed in Fig 13) along a side surface (104a along side surface of 106 disclosed in Para [0030] and Fig 13) of the conductive portion (106), and
the conductive portion (106) and the insulating liner (104a) are below the surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a)(106 and 104a below the top of 100a disclosed in annotated Fig 13 of Ma ‘705 and Para [0033]), and the conductive portion (106) includes a protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and Para [0031]) above a top surface (top of 104a as shown in annotated Fig 13 of Ma ‘705) of the insulating liner (104a);
a bump directly (112/114/156, Fig 13, Para [0021 and 0052]) on the TSV (108a)(114 on 108a disclosed in Fig 13), wherein
the bump (112/114/156) includes a conductive plug portion (conductive plug portion shown in annotated Fig 13 of Ma ‘705, hereinafter CPP) above the surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a) (CPP above top of 100a disclosed in annotated Fig 13 of Ma ‘750 and Para [0053]) and a step structure portion (step structure portion (comprising 114/156) shown in annotated Fig 13 of Ma ‘705, hereinafter SSP) extending from the conductive plug portion (CPP) into the semiconductor substrate (100a)(SSP extending from CPP into 100a disclosed in annotated Fig 13 of Ma ‘750 and Para [0053]),
the step structure portion (SSP) includes a bottom portion (bottom portion of SSP shown in annotated Fig 13_1 of Ma ‘750) that contacts the protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and in annotated Fig 13_1 of Ma ‘705) of the conductive portion (106) of the TSV (108a)(bottom portion of SSP contacting protruding portion of 106 shown in annotated Fig 13_1 of Ma ‘750) and electrically couples the protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and in annotated Fig 13_1 of Ma ‘705) and the conductive plug portion (CPP) with each other (114/156 (which comprises SSP) electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021]); and
an insulating film (144a, Fig 13, Para [0034]) surrounding the step structure portion (SSP) of the bump (112/114/156)(144a surrounding step structure of bump shown in Fig 13 and annotated Fig 13 of Ma ‘750), wherein
the insulating film (144a) extends from the surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a) along the step structure portion (SSP) and reaches the top surface (top of 104a as shown in annotated Fig 13 of Ma ‘705) of the insulating liner (104a)(144a extending from top of 100a along step structure portion and reaching the top of 104a disclosed in Fig 13).
With respect to Claim 2 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 1, and Ma ‘750 further discloses wherein at least part of the step structure portion (SSP) is in an opening (142, Fig 6, Para [0021]) of the semiconductor substrate (100a)(part of step structure portion in opening 142 shown in Fig 13 and Para [0044]).
With respect to Claim 3 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 2, and Ma ‘750 further discloses wherein the step structure portion (SSP) electrically couples the bump (112/114/156) to the TSV (108a) in the opening (142) (114/156 (which comprises SSP) electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021], Fig 13 discloses connection of 114/156 to 106 in opening 142).
With respect to Claim 4 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 1, and Ma ‘750 discloses further wherein the step structure portion (SSP) is narrower in width than the conductive plug portion (CPP)(SSP narrower in width than CPP shown in annotated Fig 13 of Ma ‘750).
With respect to Claim 5 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 1, and Ma ‘750 discloses further wherein the step structure portion (SSP) is conductive (Para [0076] discloses 114 as solder, Para [0046] discloses 156 comprises Cu and Au) and is integral with (Fig 13 discloses SSP with CPP) the conductive plug portion (CPP).
With respect to Claim 6 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 1, and Ma ‘750 further discloses wherein the insulating film (144a) is configured to provide insulation (Para [0036] discloses 144a as a dielectric) to the step structure portion (SSP)(annotated Fig 13 discloses 144a separating SSP from 100a) at least from the surrounding semiconductor substrate (100a).
With respect to Claim 7 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 1, and Ma ‘750 further discloses wherein the step structure portion (SSP) electrically couples (114/156 electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021]) the bump (112/114/156) to an exposed upper surface of the protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and Para [0031]) of the conductive portion (106) of the TSV (108a) to provide an electrical path (114/156 electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021]) between the bump (112/114/156) and the conductive portion (106) of the TSV (108a).
With respect to Claim 8 Ma ‘750 discloses a semiconductor device (Fig 1-14), comprising:
a semiconductor substrate (100a, Fig 13, Para [0020]);
and a through-silicon via (TSV)-Bump structure (108a/112/114/156, Fig 13, Para [0020, 0021 and 0052]) comprising:
a through-silicon via (TSV) (108a, Fig 13, Para [0020]) in a semiconductor substrate (100a); and
a bump directly (112/114/156, Fig 13, Para [0021 and 0052]) on the TSV (108a)(114 on 108a disclosed in Fig 13), wherein
the TSV (108a) is at a position deeper than a surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a),
the TSV (108a) includes a conductive portion (106, Fig 13, Para [0032]) vertically extending (106 vertically extending in 100a disclosed in Fig 13) in the semiconductor substrate (100a) and an insulating liner (104a, Fig 13, Para [0032]) vertically extending (104a vertically extending in 100a disclosed in Fig 13) along a side surface (104a along side surface of 106 disclosed in Para [0030] and Fig 13) of the conductive portion (106), and
the conductive portion (106) and the insulating liner (104a) are below the surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a)(106 and 104a below the top of 100a disclosed in annotated Fig 13 of Ma ‘705 and Para [0033]), and the conductive portion (106) includes a protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and Para [0031]) above a top surface (top of 104a as shown in annotated Fig 13 of Ma ‘705) of the insulating liner (104a), and wherein
the bump (112/114/156) includes a conductive plug portion (conductive plug portion shown in annotated Fig 13 of Ma ‘705, hereinafter CPP) above the surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a) (CPP above top of 100a disclosed in annotated Fig 13 of Ma ‘750 and Para [0053]) and a step structure portion (step structure portion shown in annotated Fig 13 of Ma ‘705, hereinafter SSP) extending from the conductive plug portion (CPP) into the semiconductor substrate (100a)(SSP extending from CPP into 100a disclosed in annotated Fig 13 of Ma ‘750 and Para [0053]),
the step structure portion (SSP) includes a bottom portion (bottom portion of SSP shown in annotated Fig 13_1 of Ma ‘750) that contacts the protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and in annotated Fig 13_1 of Ma ‘705) of the conductive portion (106) of the TSV (108a)(bottom portion of SSP contacting protruding portion of 106 shown in annotated Fig 13_1 of Ma ‘750) and electrically couples the protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and in annotated Fig 13_1 of Ma ‘705) and the conductive plug portion (CPP) with each other (114/156 electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021]), and
the step structure portion (SSP) is surrounded by (annotated Fig 13 of Ma ‘750 discloses 144a surrounds SSP) an insulating film (144a, Fig 13, Para [0034]), the insulating film (144a) extending from (Fig 13 discloses 144a extends form top of 100a) the surface (top of 100a as shown in annotated Fig 13 of Ma ‘705) of the semiconductor substrate (100a) along the step structure portion (SSP) and reaching the top surface (top of 104a) of the insulating liner (104a)(annotated Fig 13 discloses 144a along the SSP and reaching the top surface of 104a).
With respect to Claim 9 Ma ‘750 discloses all limitations of the semiconductor device according to claim 8, and Ma ‘750 further discloses wherein at least part of the step structure portion (SSP) is in an opening (142, Fig 6, Para [0021]) of the semiconductor substrate (100a)(part of step structure portion in opening 142 shown in Fig 13 and Para [0044]).
With respect to Claim 10 Ma ‘750 discloses all limitations of the semiconductor device according to claim 9, and Ma ‘750 further discloses wherein the step structure portion (SSP) is configured to electrically couple the bump (112/114/156) to the TSV (108a) in the opening (142) (114/156 (which comprises SSP) electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021], Fig 13 discloses connection of 114/156 to 106 in opening 142).
With respect to Claim 11 Ma ‘750 discloses all limitations of the semiconductor device according to claim 8, and Ma ‘750 discloses further wherein the step structure portion (SSP) is narrower in width than the conductive plug portion (CPP)(SSP narrower in width than CPP shown in annotated Fig 13 of Ma ‘750).
With respect to Claim 12 Ma ‘750 discloses all limitations of the semiconductor device according to claim 8, and Ma ‘750 discloses further wherein the step structure portion(SSP) is conductive (Para [0076] discloses 114 as solder, Para [0046] discloses 156 comprises Cu and Au) and is integral with (Fig 13 discloses SSP with CPP) the conductive plug portion (CPP).
With respect to Claim 13 Ma ‘750 discloses all limitations of the semiconductor device according to claim 8, and Ma ‘750 discloses further wherein the insulating film (144a) is configured to provide insulation (Para [0036] discloses 144a as a dielectric) to the step structure portion (SSP)(annotated Fig 13 discloses 144a separating SSP from 100a) at least from the surrounding semiconductor substrate (100a).
With respect to Claim 14 Ma ‘750 discloses all limitations of the semiconductor device according to claim 8, and Ma ‘750 further discloses wherein the step structure portion (SSP) electrically couples (114/156 electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021]) the bump (112/114/156) to an exposed upper surface of the protruding portion (protruding portion of 106 above top surface of 104a disclosed in annotated Fig 13 of Ma ‘705 and Para [0031]) of the conductive portion (106) of the TSV (108a) to provide an electrical path (114/156 electrically coupled to 106 disclosed in Abstract, Para [0005, 0007 and 0021]) between the bump (112/114/156) and the conductive portion (106) of the TSV (108a).
With respect to Claim 21 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 1, and Ma ‘750 further discloses wherein the conductive plug portion (CPP) of the bump (112/114/156) is exposed to an outside (annotated Fig 13 of Ma ‘750 discloses CPP is exposed to an outside of 100a) of the semiconductor substrate (100a).
With respect to Claim 22 Ma ‘750 discloses all limitations of the TSV-Bump structure according to claim 21, and Ma ‘750 further discloses wherein the bump (112/114/156) further comprises a conductive pad portion (112, Fig 13, Para [0021]) on the conductive plug portion (CPP), and the conductive pad portion (112) and the conductive plug portion (CPP) are exposed to the outside (annotated Fig 13 of Ma ‘750 discloses 112 and CPP are exposed to the outside of 100a) of the semiconductor substrate (100a).
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 23: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “wherein the step structure of the bump is not exposed to the outside of the semiconductor substrate” along with the rest of the limitations of said claims
Closest prior art of record Ma ‘750 teaches a through-silicon via (TSV)-Bump structure, comprising: a TSV in a semiconductor substrate, wherein the TSV is at a position deeper than a surface of the semiconductor substrate, the TSV includes a conductive portion vertically extending in the semiconductor substrate and an insulating liner vertically extending along a side surface of the conductive portion, and the conductive portion and the insulating liner are below the surface of the semiconductor substrate, and the conductive portion includes a protruding portion above a top surface of the insulating liner; a bump directly on the TSV, wherein the bump includes a conductive plug portion above the surface of the semiconductor substrate and a step structure portion extending from the conductive plug portion into the semiconductor substrate, the step structure portion includes a bottom portion that contacts the protruding portion of the conductive portion of the TSV and electrically couples the protruding portion and the conductive plug portion with each other; and an insulating film surrounding the step structure portion of the bump, wherein the insulating film extends from the surface of the semiconductor substrate along the step structure portion and reaches the top surface of the insulating liner, wherein the conductive plug portion of the bump is exposed to an outside of the semiconductor substrate. However Ma ‘750 fails to disclose the limitation “wherein the step structure of the bump is not exposed to the outside of the semiconductor substrate” as the step structure of Ma ‘750 is exposed to the outside of the semiconductor substrate.
Closest prior art of record Liu et al. (US 2023/0005817 A1, hereinafter Liu ‘817) discloses a TSV comprising a bump structure with a step structure of the bump. However Liu ‘817 fails to disclose the limitation “wherein the step structure of the bump is not exposed to the outside of the semiconductor substrate”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
