Listed by the USPTO as BERRY, PAUL ANTHONY
Tech Center 4100 • Art Units: 2898 4100
This examiner grants 91% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18464608 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME | Final Rejection | Samsung Electronics Co., Ltd. |
| 18464348 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME | Final Rejection | Samsung Electronics Co., Ltd. |
| 17742852 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME | Final Rejection | Samsung Electronics Co., Ltd. |
| 18435035 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | Final Rejection | FUJI ELECTRIC CO., LTD. |
| 18834732 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 17710837 | INTEGRATED CIRCUIT STRUCTURES WITH FULL-WRAP CONTACT STRUCTURE | Final Rejection | Intel Corporation |
| 18440348 | ASYMMETRIC TRANSISTOR DEVICES | Non-Final OA | Micron Technology, Inc. |
| 18046650 | TSV-BUMP STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD OF FORMING THE SAME | Final Rejection | Micron Technology, Inc. |
| 17848021 | MEMORY DEVICE INCLUDING HIGH-ASPECT-RATIO CONDUCTIVE CONTACTS | Final Rejection | Micron Technology, Inc. |
| 18011658 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL SUBSTRATE, AND SEMICONDUCTOR EPITAXIAL SUBSTRATE | Non-Final OA | KYOCERA Corporation |
| 18620222 | METHOD FOR SEMICONDUCTOR PROCESSING | Non-Final OA | Tokyo Electron Limited |
| 18611527 | PLASMA ASSISTED METAL OXIDE REDUCTION | Final Rejection | Tokyo Electron Limited |
| 18062034 | GATE-ALL-AROUND DEVICE WITHOUT DIELECTRIC INNER SPACER | Final Rejection | International Business Machines Corporation |
| 18440209 | GRAIN GROWTH OF SILICON BY METAL INDUCED CRYSTALLIZATION | Non-Final OA | Applied Materials, Inc. |
| 18512894 | LOW RESISTIVITY GAPFILL | Final Rejection | Applied Materials, Inc. |
| 17875535 | PATTERNING SCHEME TO IMPROVE EUV RESIST AND HARD MASK SELECTIVITY | Final Rejection | Applied Materials, Inc. |
| 18352708 | SOURCE/DRAIN FEATURES FOR STACKED MULTI-GATE DEVICE | Final Rejection | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18323179 | DIODE-CONTAINING COMPONENT AND METHOD FOR MANUFACTURING THE SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18150027 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | Final Rejection | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 17899865 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THEREOF | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18194748 | Blocking Structures on Isolation Structures | Final Rejection | Taiwan Semiconductor Manufacturing Co., Ltd. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy90.6% of resolved applications examined by Paul Anthony Berry were allowed (53 resolved cases), compared with 80.2% across Art Unit 2898 over the last five years.
This examiner's interview lift is -1.3 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Paul Anthony Berry took 1,242 days on average from filing to allowance.
Paul Anthony Berry examines applications in Art Unit 2898 in Tech Center 4100.
