DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/02/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-14 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14, 21 and 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (US 2023/0005817 A1, hereinafter Liu ‘817).
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With respect to Claim 1 Liu ‘817 discloses a through-silicon via (TSV)-Bump structure (Fig 7-25), comprising:
a TSV (30, Fig 25, Para [0034]) in a semiconductor substrate (10, Fig 25, Para [0103]); and
a bump directly (41, Fig 25, Para [0052]) on the TSV (30) (41 on 30 disclosed in Fig 25 and Para [0052]),
wherein the bump (41) includes a conductive plug portion (412, Fig 25, Para [0112]) and a step structure portion (411, Fig 25, Para [0112]) under the conductive plug portion (412)(411 under 412 disclosed in Fig 25 and Para [0112]),
the step structure portion (411) is configured to electrically couple the TSV (30) and the conductive plug portion (412) with each other (Para [0063] discloses that bump 41, of which 411 is a part of) is electrically connected to TSV 30), and
the step structure portion (411) includes a bottom portion (bottom portion of 411 as shown in annotated Fig 25 of Liu ‘817) that extends from the conductive plug portion (412) into a top portion (top of substrate 10) of the semiconductor substrate (10) and contacts the TSV (30) in the top portion (top of substrate 10)(annotated Fig 25 of Liu ‘817 discloses bottom portion of 411 extends from 412 to top portion of substrate and contacts top portion of TSV 30 in the top portion).
With respect to Claim 2 Liu ‘817 discloses all limitations of the TSV-Bump structure according to claim 1, and Liu ‘817 further discloses wherein
the conductive plug portion (412) is above a surface (top of 10 as shown in Fig 25) of the semiconductor substrate (10), and
at least part (bottom portion of step structure 411, shown in annotated Fig 25 of Liu ‘817) of the step structure portion (411) is in an opening (opening of substrate 10 where bottom portion of step structure 411 exists as shown in Fig 25) of the semiconductor substrate (10).
With respect to Claim 3 Liu ‘817 discloses all limitations of the TSV-Bump structure according to claim 2, and Liu ‘817 further discloses wherein the step structure portion (411) electrically couples (Para [0063] discloses that bump 41, of which 411 is a part of, is electrically connected to TSV 30) the bump (41) to the TSV (30) in the opening (opening of substrate 10 where bottom portion of step structure 411 exists as shown in Fig 25).
With respect to Claim 4 Liu ‘817 discloses all limitations of the TSV-Bump structure according to claim 1, and Liu ‘817 further discloses wherein the step structure portion (411) is narrower in width than the conductive plug portion (412)(Fig 25 discloses that 411 has a narrower width than the conductive plug portion 412).
With respect to Claim 5 Liu ‘817 discloses all limitations of the TSV-Bump structure according to claim 1, and Liu ‘817 further discloses wherein the step structure portion (411) is conductive (Para [0052] discloses 41, of which step structure portion 411 is a part, is conductive), and is integral with (Para [0112] discloses 411 and 412 are parts of 41 and “The first part 411 and the second part 412 are connected as a whole”) the conductive plug portion (412).
With respect to Claim 6 Liu ‘817 discloses all limitations of the TSV-Bump structure according to claim 1, and Liu ‘817 further discloses wherein at least part (underside of 411 as shown in annotated Fig 25 of Liu ‘817) of the step structure portion (411) is surrounded by an insulating film (51, Fig 25, Para [0089]), the insulating film (51) configured to provide insulation (Para [0091] discloses 51 provides dielectric protection to 41, of which 411 is a part, and 10) to the step structure portion (411) at least from the surrounding semiconductor substrate (10).
With respect to Claim 7 Liu ‘817 discloses all limitations of the TSV-Bump structure according to claim 1, and Liu ‘817 further discloses wherein the step structure portion (411) electrically couples the bump (41) to an exposed upper surface (upper surface of 30 shown in annotated Fig 25 of Liu ‘817) of a conductive film of the TSV (top conductive film of 30) to provide an electrical path between the bump (41) and the conductive film (top conductive film of 30) of the TSV (30) (Para [0063] discloses that bump 41, of which 411 is a part of, is electrically connected to TSV 30).
With respect to Claim 8 Liu ‘817 discloses a semiconductor device (Fig 7-25), comprising:
a semiconductor substrate (10, Fig 25, Para [0103]); and
a through-silicon via (TSV)-Bump structure (30 and 41, Fig 25, Para [0034 and 0052]) comprising:
a through-silicon via (TSV) (30, Fig 25, Para [0034]) in the semiconductor substrate (10); and
a bump (41, Fig 25, Para [0052]) directly on (41 on 30 disclosed in Fig 25 and Para [0052]) the TSV (30), wherein
the bump (41) includes a conductive plug portion (412, Fig 25, Para [0112]) and a step structure portion (411, Fig 25, Para [0112]) under the conductive plug portion (411) (411 under 412 disclosed in Fig 25 and Para [0112]), and
the step structure portion (411) is configured to electrically couple the TSV (30) and the conductive plug portion (412) with each other (Para [0063] discloses that bump 41, of which 411 is a part of, is electrically connected to TSV 30), and
the step structure portion (411) includes a bottom portion (bottom portion of 411 as shown in annotated Fig 25 of Liu ‘817) that extends from the conductive plug portion (412) into a top portion (top of substrate 10) of the semiconductor substrate (10) and contacts the TSV (30) in the top portion (top of substrate 10)(annotated Fig 25 of Liu ‘817 discloses bottom portion of 411 extends from 412 to top portion of substrate and contacts top portion of TSV 30 in the top portion).
With respect to Claim 9 Liu ‘817 discloses all limitations of the semiconductor device according to claim 8, and Liu ‘817 further discloses wherein the conductive plug portion (412) is above a surface (top of 10 as shown in Fig 25) of the semiconductor substrate (10), and at least part (bottom portion of step structure 411, shown in annotated Fig 25 of Liu ‘817) of the step structure portion (411) is in an opening (opening of substrate 10 where bottom portion of step structure 411 exists as shown in Fig 25) of the semiconductor substrate (10).
With respect to Claim 10 Liu ‘817 discloses all limitations of the semiconductor device according to claim 9, and Liu ‘817 further discloses wherein the step structure portion (411) is configured to electrically couple (Para [0063] discloses that bump 41, of which 411 is a part of, is electrically connected to TSV 30) the bump (41) to the TSV (30) in the opening (opening of substrate 10 where bottom portion of step structure 411 exists as shown in Fig 25).
With respect to Claim 11 Liu ‘817 discloses all limitations of the semiconductor device according to claim 8, and Liu ‘817 further discloses wherein the step structure portion (411) is narrower in width than the conductive plug portion (412)(Fig 25 discloses that 411 has a narrower width than the conductive plug portion 412).
With respect to Claim 12 Liu ‘817 discloses all limitations of the semiconductor device according to claim 8, and Liu ‘817 further discloses wherein the step structure portion (411) is conductive (Para [0052] discloses 41, of which step structure portion 411 is a part, is conductive), and is integral with (Para [0112] discloses 411 and 412 are parts of 41 and “The first part 411 and the second part 412 are connected as a whole”) the conductive plug portion (412).
With respect to Claim 13 Liu ‘817 discloses all limitations of the semiconductor device according to claim 8, and Liu ‘817 further discloses wherein at least part (underside of 411 as shown in annotated Fig 25 of Liu ‘817) of the step structure portion (411) is surrounded by an insulating film (51, Fig 25, Para [0089]), the insulating film (51) configured to provide insulation (Para [0091] discloses 51 provides dielectric protection to 41, of which 411 is a part, and 10) to the step structure portion (411) at least from the surrounding semiconductor substrate (10).
With respect to Claim 14 Liu ‘817 discloses all limitations of the semiconductor device according to claim 8, and Liu ‘817 further discloses wherein the step structure portion (411) electrically couples the bump (41) to an exposed upper surface (upper surface of 30 shown in annotated Fig 25 of Liu ‘817) of a conductive film of the TSV (top conductive film of 30) to provide an electrical path between the bump (41) and the conductive film (top conductive film of 30) of the TSV (30) (Para [0063] discloses that bump 41, of which 411 is a part of, is electrically connected to TSV 30).
With respect to Claim 21 Liu ‘817 discloses all limitations of the apparatus according to claim 1, and Liu ‘817 further discloses wherein the conductive plug portion (412) of the bump (41) is exposed to an outside (region exposed to atmosphere above substrate 10) of the semiconductor substrate (10)(Fig 25 discloses 412 is exposed in the region above substrate 10).
With respect to Claim 23 Liu ‘817 discloses all limitations of the apparatus according to claim 21, and Liu ‘817 further discloses wherein the step structure (411) of the bump (41) is not exposed to (Fig 25 discloses that 411 is protected from region exposed to atmosphere above substrate 10 by layer 51) the outside (region exposed to atmosphere above substrate 10) of the semiconductor substrate (10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Liu ‘817 in view of Mariottini et al. (US 2017/0077052 A1, hereinafter Mariottini ‘052), in view of the following arguments.
With respect to Claim 22 Liu ‘817 discloses all limitations of the apparatus according to claim 21, and Liu ‘817 further discloses wherein the bump (41) and the conductive plug portion (412) are exposed to the outside (region exposed to atmosphere above substrate 10) of the semiconductor substrate (10)(Fig 25 discloses 412 is exposed in the region above substrate 10).
But Liu ‘817 fails to explicitly disclose wherein the bump further comprises a conductive pad portion on the conductive plug portion, and the conductive pad portion and the conductive plug portion are exposed to the outside of the semiconductor substrate.
Nevertheless, in a related endeavor (Fig 1 of Mariottini ‘052), Mariottini ‘052 teaches wherein the bump (140/130/134/132, Fig 1 of Mariottini ‘052, Para [0017]) further comprises a conductive pad portion (134, Fig 1 of Mariottini ‘052, Para [0017]) on the conductive plug portion (132, Fig 1 of Mariottini ‘052, Para [0017]), and the conductive pad portion (134) and the conductive plug portion (132) are exposed to the outside of the semiconductor substrate (114/110, Fig 1 of Mariottini ‘052, Para [0016])(Fig of Mariottini ‘052 discloses conductive pad 134 and conductive plug 132 exposed outside of substrate 114/110).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Mariottini ‘052’s teaching the bump further comprises a conductive pad portion on the conductive plug portion, and the conductive pad portion and the conductive plug portion are exposed to the outside of the semiconductor substrate into Liu ‘817’s device. The ordinary artisan would have been motivated to modify Liu ‘817 in the manner set forth above, at least, because, as Mariottini ‘052 teaches in Para [0018] the pad material can function as an under bump metallization (UBM) portion. One of ordinary skill in the art would recognize the well-known advantage that the UBM helps to provide conductive connection and protection in the connection of the solder bump.
As incorporated, the conductive pad portion (134 of Mariottini ‘052) would be used on the conductive plug portion (412 of Liu ‘817), so that the conductive pad portion and the conductive plug portion are exposed to the outside of the semiconductor substrate of Liu ‘817.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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