Prosecution Insights
Last updated: April 19, 2026
Application No. 18/046,992

POWER MODULE FOR PRODUCING STRUCTURE-BORNE SOUND, DEVICE FOR DETECTING AN IC PACKAGE DELAMINATION HAVING SUCH A POWER MODULE, AND METHOD FOR DETECTING AN IC PACKAGE DELAMINATION

Final Rejection §103
Filed
Oct 17, 2022
Examiner
LIU, XIAOMING
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Robert Bosch GmbH
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
97%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
495 granted / 576 resolved
+17.9% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
39 currently pending
Career history
615
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 576 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 9/19/2025 have been fully considered but they are not persuasive. Examiner thanks Applicant for Applicant’s cooperation in the prosecution process and for Applicant’s concise analysis of the prior Office Action 6/4/2025 (Prior Office Action) found in Applicant's Remarks. The Remarks assert that: The cited references fail to show “wherein the second substrate has a piezoelectric material and the control unit is configured to excite the piezoelectric material of the second substrate so that a structure-borne sound signal is produced" in claim 1 because the piezoelectric acoustic transducer and receivers of Joshi are attached to and positioned above the electronic device 101(A). The cited references fail to show “the control unit being configured to compare the acquired structure-borne sound signal to a reference value, an IC package delamination being recognized if the acquired structure- borne sound signal exceeds the reference value” in claim 5 and 6. In regards to the first assertion, the Remarks appear to base a conclusion of non-obviousness on analysis that interprets each reference alone and requires each reference to teach all the limitations, i.e. piezoelectric acoustic transducer/receivers and location of the piezoelectric elements in this case, would appear to be a piecemeal analysis; and one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413,208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091,231 USPQ 375 (Fed. Cir. 1986). Joshi teaches piezoelectric transmitter/receivers (201-205, fig2, [36]) attached close to boding layer (102, fig1, [35]) positioned above the electronic device to detect defects ([31]). Joshi also teaches acoustic signals have larger amplitude when component is closer to the transmitter ([53]). Ozeki teaches a transmission type flaw detection unit (fig2(a)) with receiver (1b, fig2(a), [28]) on one side and transmitter (1a, fig2(a), [27]) on the other side of the structure being detected (2, fig2(a), [29]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Joshi and Ozeki to form a transmission type flaw detection structure with Piezoelectric transmitter/receiver (Joshi 201-205, [36]) formed in substrate 105 under stack structure being tested (Joshi, 102(A/B) and the other receiver/transmitter above the device 101(A). The motivation to do so is to be able to detect flaw in a wider range (Ozeki, [117]) and accurately detect defect formed on each side of the boning layer (Josh, [53]). In regards to the second assertion, when examining claims, the language of the claims must be interpreted in the broadest reasonable manner. Joshi teaches the control unit (160, fig1) being configured to compare the acquired structure-borne sound signal to a reference value (reference measurement , [58]), an IC package delamination being recognized if the acquired structure- borne sound signal exceeds the reference value ([42, 58]). Therefore, the combination reads on the broadest reasonable interpretation of the language recited by Applicant's claims. Consequently, Examiner respectfully asserts that Joshi discloses “the control unit being configured to compare the acquired structure-borne sound signal to a reference value, an IC package delamination being recognized if the acquired structure- borne sound signal exceeds the reference value,”. In light of the discussion above, Examiner respectfully submits that independent claims 1, 5 and 6 stand properly rejected and all the claims dependent on claims 1, 5 and 6 (i.e. 2-4 and 7) stand properly rejected as well. Furthermore, Examiner respectfully submits that the Remarks and Amendments have been fully considered, but found to be not persuasive. Therefore, this action is made final. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. US 2022/0102620, Littrell et al. US 2019/0289405 and Ozeki et al. US 2016/0054266. PNG media_image1.png 908 1007 media_image1.png Greyscale Re claim 1, Joshi teaches a power module for producing structure-borne sound (fig1 and 2), comprising: a control unit (170, 141, and 180, fig1, [29]) and a first substrate (substrate holding 170, 141, and 180 of controller 160, fig1, [65]), the control unit being situated on the first substrate; at least one first power semiconductor (101(A), fig1, [28]) and at least one second power semiconductor (101(B), fig1, [28, 29]), a first metal connection (102(C/D), 103 (C/D), 111(A/B), fig1, [28, 29]), a second substrate (105, fig1, [28]), and a second metal connection (106 Cu, fig1, [28]), the first metal connection (102(C/D), 103 (C/D), 111(A/B), fig1, [28, 29]) electrically connecting the first substrate (substrate of 160, fig1, [29]) and the second substrate (105, fig1, [28]), and the second metal connection (106 Cu, fig1, [28]) being situated below the second substrate (105, fig1, [28]); Joshi teaches piezoelectric transmitter/receiver (201-205, fig2, [37) attached close to boding layer (102, fig1, [35]) to detect defects ([31]) and acoustic signals have larger amplitude when component is closer to the transmitter ([53]). Joshi does not explicitly show the first substrate being situated on the at least one first power semiconductor and on the at least one second power semiconductor; wherein the second substrate has a piezoelectric material and the control unit is configured to excite the piezoelectric material of the second substrate so that a structure-borne sound signal is produced. Littrell teaches ASIC chip (16, fig1, [31]) with receiver (14, fig1, [31]) located on one side of a substrate (22, fig1, [31]). Ozeki teaches a transmission type flaw detection unit (fig2(a)) with receiver (1b, fig2(a), [28]) on one side and transmitter (1a, fig2(a), [27]) on the other side of the structure being detected (2, fig2(a), [29]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Joshi, Ozeki and Littrell to form a transmission type flaw detection structure with Piezoelectric transmitter/receiver (Joshi 201-205, [37]) formed in substrate 105 under stack structure being tested (Joshi, 102(A/B) and 103 (A/B), fig1) and bond the MEMS transmitter/receiver part with ASIC chip (Littrell fig1) above Joshi 101(A). The motivation to do so is to be able to detect flaw accurately on each side of the boning layer with a wider range (Ozeki, [117]; Josh, [53]) and improved detection efficiency (Littrell, [2, 52, 57]). Re claim 3, Joshi modified above teaches the power module as recited in claim 1, wherein the control unit includes an ASIC (Littrell, 16, fig1). Re claim 5, Joshi teaches a device configured to detect an IC package delamination (fig1), the device comprising: a control unit (170, 141, 180 and 180, fig1, [29]) and a first substrate (substrate holding 170, 141, 180 and 180 of controller 160, fig1, [65]), the control unit being situated on the first substrate, at least one first power semiconductor (101(A), fig1, [28]) and at least one second power semiconductor (101(B), fig1, [28, 29]), a first metal connection (102(C/D), 103 (C/D), 111(A/B), fig1, [28, 29]), a second substrate (105, fig1, [28]), and a second metal connection (106 Cu, fig1, [28]), the first metal connection (102(C/D), 103 (C/D), 111(A/B), fig1, [28, 29]) electrically connecting the first substrate (substrate of 160, fig1, [29]) and the second substrate (105, fig1, [28]), and the second metal connection (106 Cu, fig1, [28]) being situated below the second substrate (105, fig1, [28]). Joshi teaches piezoelectric transmitter/receiver (201-205, fig2, [37) attached close to boding layer (102, fig1, [35]) to detect defects ([31]) and acoustic signals have larger amplitude when component is closer to the transmitter ([53]). Joshi does not explicitly show detail structure of the power module for producing structure-borne sound. Littrell teaches ASIC chip (16, fig1, [31]) with receiver (14, fig1, [31]) located on one side of a substrate (22, fig1, [31]). Ozeki teaches a transmission type flaw detection unit (fig2(a)) with receiver (1b, fig2(a), [28]) on one side and transmitter (1a, fig2(a), [27]) on the other side of the structure being detected (2, fig2(a), [29]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Joshi, Ozeki and Littrell to form a transmission type flaw detection structure with Piezoelectric transmitter/receiver (Joshi 201-205, [37]) formed in substrate 105 under stack structure being tested (Joshi, 102(A/B) and 103 (A/B), fig1) and bond the MEMS transmitter/receiver part with ASIC chip (Littrell fig1) above Joshi 101(A). The motivation to do so is to be able to detect flaw accurately on each side of the boning layer with a wider range (Ozeki, [117]; Josh, [53]) and improved detection efficiency (Littrell, [2, 52, 57]). Joshi modified above teaches a power module for producing structure-borne sound (see figure above), the power module including: the first substrate (substrate with ASIC and MEMS sensor, see figure above) being situated on the at least one first power semiconductor (Joshi, 101(A), see figure above) and on the at least one second power semiconductor (Joshi, 101(B), see figure above), wherein the second substrate has a piezoelectric material (piezoelectric transmitter/receiver formed under Joshi 103 in 105, see figure above) and the control unit is configured to excite the piezoelectric material of the second substrate so that a structure-borne sound signal is produced (Joshi, fig2; Ozeki, fig2); and a MEMS sensor (piezoelectric transmitter/receiver formed above Joshi 101(A), see figure above) situated on the first substrate at a lateral distance from the control unit (see figure above), the MEMS sensor being configured to acquire the produced structure-borne sound signal (Joshi, fig2; Ozeki, fig2), and the control unit being configured to compare the acquired structure-borne sound signal to a reference value (Joshi, fig2; Ozeki, fig2), an IC package delamination being recognized if the acquired structure-borne sound signal exceeds the reference value (Joshi, fig2, [31, 42]; Ozeki, fig2). Re claim 6, Joshi teaches a method for detecting an IC package delamination using a device (fig1) including: a control unit (170, 141 and 180, fig1, [29]) and a first substrate (substrate holding 170, 141 and 180 of controller 160, fig1, [65]), the control unit being situated on the first substrate, at least one first power semiconductor (101(A), fig1, [28]) and at least one second power semiconductor (101(B), fig1, [28, 29]), a first metal connection (102(C/D), 103 (C/D), 111(A/B), fig1, [28, 29]), a second substrate (105, fig1, [28]), and a second metal connection (106 Cu, fig1, [28]), the first metal connection (102(C/D), 103 (C/D), 111(A/B), fig1, [28, 29]) electrically connecting the first substrate (substrate of 160, fig1, [29]) and the second substrate (105, fig1, [28]), and the second metal connection (106 Cu, fig1, [28]) being situated below the second substrate (105, fig1, [28]). Joshi teaches piezoelectric transmitter/receiver (201, fig2, [37) attached close to boding layer (102, fig1, [35]) to detect defects ([31]) and acoustic signals have larger amplitude when component is closer to the transmitter ([53]). Joshi does not explicitly show detail structure of the power module for producing structure-borne sound. Littrell teaches ASIC chip (16, fig1, [31]) with receiver (14, fig1, [31]) located on one side of a substrate (22, fig1, [31]). Ozeki teaches a transmission type flaw detection unit (fig2(a)) with receiver (1b, fig2(a), [28]) on one side and transmitter (1a, fig2(a), [27]) on the other side of the structure being detected (2, fig2(a), [29]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Joshi, Ozeki and Littrell to form a transmission type flaw detection structure with Piezoelectric transmitter/receiver (Joshi 201-205, [37]) formed in substrate 105 under stack structure being tested (Joshi, 102(A/B) and 103 (A/B), fig1) and bond the MEMS transmitter/receiver part with ASIC chip (Littrell fig1) above Joshi 101(A). The motivation to do so is to be able to detect flaw accurately on each side of the boning layer with a wider range (Ozeki, [117]; Josh, [53]) and improved detection efficiency (Littrell, [2, 52, 57]). Joshi modified above teaches a power module for producing structure-borne sound (see figure above), the power module including: the first substrate (substrate with ASIC and MEMS sensor, see figure above) being situated on the at least one first power semiconductor (Joshi, 101(A), see figure above) and on the at least one second power semiconductor (Joshi, 101(B), see figure above), wherein the second substrate has a piezoelectric material (piezoelectric transmitter/receiver formed under Joshi 103 in 105, see figure above) and the control unit (Joshi, 160, fig1) is configured to excite the piezoelectric material of the second substrate so that a structure-borne sound signal is produced (Joshi, fig2; Ozeki, fig2); and a MEMS sensor (piezoelectric transmitter/receiver formed above Joshi 101(A); Littrell, 14, see figure above) situated on the first substrate at a lateral distance from the control unit (Littrell, 16, fig1, [31]; Joshi, 160, fig1), the MEMS sensor being configured to acquire the produced structure-borne sound signal (Joshi, fig2; Ozeki, fig2), and the control unit being configured to compare the acquired structure-borne sound signal to a reference value (Joshi, fig2, [58]; Ozeki, fig2), an IC package delamination being recognized if the acquired structure-borne sound signal exceeds the reference value (Joshi, fig2, [31, 42, 58]; Ozeki, fig2); the method comprising the following steps: producing the structure-borne sound signal of the second substrate using a sinusoidal signal that is emitted by the control unit (Joshi, fig2, [31]; Ozeki, fig2); acquiring the structure-borne sound signal using the MEMS sensor (Joshi, fig2, [31]; Ozeki, fig2); comparing the structure-borne sound signal to the reference value using the control unit (Joshi, fig2, [31, 42, 58]; Ozeki, fig2); and recognizing the IC package delamination based on the acquired structure-borne sound signal exceeding the reference value (Joshi, fig2, [31, 42, 58]; Ozeki, fig2). Re claim 7, Joshi modified above teaches the method as recited in claim 6, wherein the sinusoidal signal has a resonant frequency of the second substrate (Joshi, fig2, [31]; Ozeki, fig2). Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. US 2022/0102620, Littrell et al. US 2019/0289405, Ozeki et al. US 2016/0054266 and Tanaka US2022/0020905 . Re claim 2, Joshi does not explicitly show the power module as recited in claim 1, wherein the second substrate includes an AMB ceramic. Tanaka teaches an active metal brazing method used to bond copper layer with substrate ([108]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Joshi modified above and Tanaka to form 104 with a AMB method. The motivation to do so is to achieve high reliability, high environmental resistance and moisture resistance (Tanaka, [13]). Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. US 2022/0102620, Littrell et al. US 2019/0289405, Ozeki et al. US 2016/0054266 and Chiou et al. US 2016/0377496. Re claim 4, Joshi does not explicitly show the power module as recited in claim 1, wherein the first substrate includes an LTCC. Chiou teaches a low temperature co-fired ceramic seal used for seal structure (330, fig3A, [28]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Joshi modified above and Chiou to form a LTCC seal on for the piezoelectric receiver structure. The motivation to do so is to achieve a hermetic seal (Chiou, [28]). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIAOMING LIU/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Oct 17, 2022
Application Filed
May 31, 2025
Non-Final Rejection — §103
Sep 19, 2025
Response Filed
Dec 17, 2025
Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
97%
With Interview (+11.0%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
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