DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 5, 8-10, 13, 15, and 17-18 filed on 03/02/2026 have been fully considered for examination based on their merits. The original claims 2-4, 6-7, 11-12, 14, 16, and 19-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-9, filed 03/02/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of HO.
Regarding Independent Claim 1. The Applicant argues (see Remarks, page 7) that no cited references teach or suggest the amended limitations to claim 1, now recites, “a microelectronic assembly comprising:… two opposing sidewalls…of the conductive via protrude,...proximate edges of the conductive trace…the width of the conductive via.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, HO teaches a microelectronic assembly (Fig. 6A, interconnect structure, [0008]), comprising: two opposing sidewalls (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias) separated by a width (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias) protrude (annotated Figure 6A), in a direction parallel (annotated Figure 6A) to the conductive trace (Fig. 6A, 114b, conductive elements), from respectively proximate edges (annotated Figure 6A) of the conductive trace (Fig. 6A, 114b, conductive elements) by a protrusion (annotated Figure 6A) that is at least ten times less (annotated Figure 6A) than the width (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias).
PNG
media_image1.png
765
1497
media_image1.png
Greyscale
Regarding Independent Claim 8. The Applicant argues (see Remarks, page 7) that no cited references teach or suggest the amended limitations to claim 1, now recites, “at least one sidewall of sidewalls of the conductive via protrudes, in a direction parallel to the conductive trace, from a nearest edge of the conductive trace.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of HO and the similar response as given above for the independent claim 1 holds good as well for the claim 8 limitations.
Regarding Independent Claim 15. The Applicant argues (see Remarks, page 7) that none of the cited references teach or suggest all limitations of amended claim 15, now recites, “a package substrate that includes: at least one sidewall of the conductive via has a concave profile.” The arguments have been fully considered, but they are not persuasive. The Examiner respectfully disagreed and further confirmed the amended limitations to claim 15 are read through with the ECTON prior art previously used for the rejection. For instance, ECTON teaches a package substrate (Fig. 6, 120) comprising: at least one sidewall (Figs. 3-4, 112, side faces, [0025]) of the conductive via (Figs. 3-4, 102, [0025]) has a concave profile (Fig. 3, the side faces, 112 of the via, 102 may be flared in an hourglass shape, [0025]), and centerlines (Fig. 1B, 108) of the conductive via (Fig. 1B, 102) and the portion of the conductive trace (Fig. 1B, 104) are mutually aligned (the via, 102 and the trace, 104 may be aligned with the centerline, [0022]).
Regarding Claims 2-7, 9-14, and 16-20: The claims 2-7, 9-14, and 16-20 depend on the independent claims 1, 8, and 15, and follow similar arguments as mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over STRONG (prior art used in the previous Office Action (hereinafter OA)), in view of Po-Kuan Ho et al, (hereinafter HO), US 20190080960 A1.
Regarding Claim 1, STRONG teaches a microelectronic assembly (Fig. 1A, 100), comprising:
a package substrate (Fig. 1A, 101, [0053]) comprising a plurality of layers (Fig. 1A, 111, layer assembly) of organic dielectric material ([0052]) and conductive traces (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) alternating with conductive vias (Fig. 1A, 112/114, first via/second via, [0047]) in alternate layers of the organic dielectric material (Fig. 1A, [0047], [0052]); and
a plurality of integrated circuit (IC) dies (Figs. 1A/13, 134/134-1/134-2, dies or IC dies, [0047], [0104]; “die” and “IC die” are synonymous, [0045]) coupled to a first side of the package substrate (annotated Figure 1A) by interconnects (Figs. 1A/11. 138/137, interconnects/first-level interconnects (FLIs), [0047], [0100]),
wherein:
the plurality of layers (Fig. 1A, 111, layer assembly) of the organic dielectric material ([0052]) comprises at least a first layer (Fig. 1A, 104, first dielectric layer) having a conductive via (Fig. 1A, 112, first via) and a second layer (Fig. 1A, 102/106, conductive layer/second dielectric layer) having a conductive trace (Fig. 1A, 116, a trace) in contact with the conductive via (annotated Figure 1A),
the second layer (Fig. 1A, 102/106, conductive layer/second dielectric layer) is not coplanar with the first layer (Fig. 1A, 104, first dielectric layer); (annotated Figure 1A),
sidewalls of the conductive via (Fig. 1A, 112/114, first via/second via) are orthogonal to the conductive trace (Fig. 1A, 116, a trace); (annotated Figure 1A), and
PNG
media_image2.png
765
903
media_image2.png
Greyscale
STRONG does not explicitly disclose a microelectronic assembly, comprising: two opposing sidewalls of the conductive via separated by a width of the conductive via protrude, in a direction parallel to the conductive trace, from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.
HO teaches a microelectronic assembly (Fig. 6A, interconnect structure, [0008]), comprising:
two opposing sidewalls (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias) separated by a width (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias) protrude (annotated Figure 6A), in a direction parallel (annotated Figure 6A) to the conductive trace (Fig. 6A, 114b, conductive elements), from respectively proximate edges (annotated Figure 6A) of the conductive trace (Fig. 6A, 114b, conductive elements) by a protrusion (annotated Figure 6A) that is at least ten times less (annotated Figure 6A) than the width (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias).
PNG
media_image1.png
765
1497
media_image1.png
Greyscale
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified STRONG to incorporate the teaches of HO such that a microelectronic assembly, comprising: two opposing sidewalls of the conductive via separated by a width of the conductive via protrude, in a direction parallel to the conductive trace, from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via, so that the vias with the lines extending substantially in a horizontal direction and the vias are located to provide electrical connection between layers of lines (HO, [0001]).
Regarding Claim 2, STRONG as modified by HO teaches the microelectronic assembly of claim 1.
STRONG further teaches the microelectronic assembly (Fig. 1A, 100), wherein another sidewall of the conductive via (Fig. 1A, 112) orthogonal to the two opposing sidewalls protrudes from a respectively proximate edge (annotated Figure 1A) of the conductive trace (Fig. 1A, 116) by the protrusion (Fig. 1B, 190, extension distance, [0048]).
PNG
media_image3.png
722
792
media_image3.png
Greyscale
Regarding Claim 3, STRONG as modified by HO teaches the microelectronic assembly of claim 1.
STRONG further teaches the microelectronic assembly (Fig. 1A, 100), wherein the first layer (Fig. 1A, 104, first dielectric layer) is under the second layer (Fig. 1A, 102/106, conductive layer/second dielectric layer).
Regarding Claim 4, STRONG as modified by HO teaches the microelectronic assembly of claim 1.
STRONG further teaches the microelectronic assembly (Fig. 1A, 100) wherein a first centerline of the conductive via (Fig. 1A, center point of the top via, 114, [0048]) is aligned (Fig. 1A, [0048]) with respect to a second centerline of the conductive trace (Fig. 1A, centerline of the trace, 116, [0048]).
Regarding Claim 5, STRONG as modified by HO teaches the microelectronic assembly of claim 4.
STRONG further teaches the microelectronic assembly (Fig. 1A, 100), wherein:
the conductive via is a first conductive via (Fig. 1A, 112, first via),
the package substrate (Fig. 1A, 101, [0053]) comprises a second conductive via (Fig. 1A, 114, second via, [0047]) in a third layer (Fig. 1A, 106, second dielectric layer) of the organic dielectric material ([0052]),
the first layer (Fig. 1A, 104, first dielectric layer), the second layer (Fig. 1A, 102, conductive layer) and the third layer (Fig. 1A, 106, second dielectric layer) are not coplanar (annotated Figure 1A),
the second conductive via (Fig. 1A, 114, second via, [0047]) has at least substantially same width (Figs. 1C, the first via, 112, the trace, 116 and the second via, 114 have a same width, 192 [0049]) as the first conductive via (Fig. 1A, 112, first via),
the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) is in contact (annotated Figure 1A) with the second conductive via (Fig. 1A, 114, second via, [0047]), and
the second centerline of the conductive trace is not aligned with a third centerline of the second conductive via (Figs. 2E/6B, alignment may not be achievable using conventional techniques in which vias and traces are separately patterned (e.g., using multiple masks, one or more masks, and/or one or more via drilling layouts, etc.) and thus are limited in their ability to achieve “perfect” alignment with each other (and therefore exhibit significant alignment offsets) [0061], [0083]).
Regarding Claim 7, STRONG as modified by HO teaches the microelectronic assembly of claim 1.
STRONG further teaches the microelectronic assembly (Fig. 1A, 100), wherein:
the package substrate (Figs. 1A/15, 101/1501, [0053]) further comprises a bridge die (Fig. 1A, 134), and
conductive pathways (Fig. 15, [0111]) through the bridge die conductively couples at least two of the plurality of IC dies (Figs. 13, 134-1/134-2, dies or IC dies, [0047], [0104]; “die” and “IC die” are synonymous, [0045]) on the package substrate (Fig. 1A, 101, [0053]).
Claim(s) 6, and 8-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over STRONG, in view of HO as applied to Claim(s) 1-5, and 7 above, and further in view of ECTON (prior art used in the previous OA).
Regarding Claim 6, STRONG as modified by HO teaches the microelectronic assembly of claim 4.
STRONG further teaches the microelectronic assembly (Fig. 1A, 100), wherein:
the conductive via is a first conductive via (Fig. 1A, 112, first via),
the package substrate (Fig. 1A, 101, [0053]) comprises a second conductive via (Fig. 1A, 114, second via, [0047]) in a third layer (Fig. 1A, 106, second dielectric layer) of the organic dielectric material ([0052]),
the first layer (Fig. 1A, 104, first dielectric layer), the second layer (Fig. 1A, 102, conductive layer) and the third layer (Fig. 1A, 106, second dielectric layer) are not coplanar (annotated Figure 1A),
the second conductive via (Fig. 1A, 114, second via, [0047]) has at least substantially same width (Figs. 1C, the first via, 112, the trace, 116 and the second via, 114 have a same width, 192 [0049]) as the first conductive via (Fig. 1A, 112, first via),
the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) is in contact (annotated Figure 1A) with the second conductive via (Fig. 1A, 114, second via, [0047]), and
STRONG as modified by HO does not explicitly disclose the microelectronic assembly, wherein: at least one sidewall of the second conductive via has concave profiles.
ECTON teaches the microelectronic assembly (Fig. 20, IC device assembly), wherein:
at least one sidewall (Fig. 3, 112, side faces, [0025]) of the second conductive via (Fig. 3, 102, [0025]) has concave profiles (Fig. 3, the side faces, 112 of the via, 102 may be flared in an hourglass shape, [0025]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have STRONG as modified by HO to incorporate the teaches of ECTON such that a microelectronic assembly, wherein: at least one sidewall of the second conductive via has concave profiles, so that to create the alignment offset between the conductive trace and the conductive via, may be less than 10 microns (ECTON, [0026], [0088]).
Regarding Claim 8, STRONG teaches a package substrate (Fig. 1A, 101, [0053]), comprising:
a plurality of layers (Fig. 1A, 111, layer assembly) of organic dielectric material ([0052]);
a conductive via (Fig. 1A, 112, first via) in a first layer (Fig. 1A, 104, first dielectric layer) of the organic dielectric material ([0052]); and
a conductive trace (Fig. 1A, 116, a trace) in a second layer (Fig. 1A, 106, second dielectric layer) of the organic dielectric material ([0052]),
wherein:
the second layer (Fig. 1A, 106, second dielectric layer) is over (annotated Figure 1A) the first layer (Fig. 1A, 104, first dielectric layer),
the conductive via (Fig. 1A, 112/114, first via/second via) is attached (annotated Figure 1A) to a portion of the conductive trace (Fig. 1A, 116, a trace),
an edge placement error (EPE) of the conductive via on the conductive trace is less than 0.1 micrometers (Figs. 2E/6B, alignment may not be achievable using conventional techniques in which vias and traces are separately patterned (e.g., using multiple masks, one or more masks, and/or one or more via drilling layouts, etc.) and thus are limited in their ability to achieve “perfect” alignment with each other (and therefore exhibit significant alignment offsets) [0061], [0083]).
STRONG does not explicitly disclose a package substrate, comprising: at least one sidewall of sidewalls of the conductive via protrudes, in a direction parallel to the conductive trace, from a nearest edge of the conductive trace.
HO teaches a package substrate (Fig. 6A, interconnect structure, [0008]), comprising:
at least one sidewall (annotated Figure 6A) of sidewalls (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias) protrudes (annotated Figure 6A), in a direction parallel (annotated Figure 6A) to the conductive trace (Fig. 6A, 114b, conductive elements), from a nearest edge (annotated Figure 6A) of the conductive trace (Fig. 6A, 114b, conductive elements).
PNG
media_image1.png
765
1497
media_image1.png
Greyscale
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified STRONG to incorporate the teaches of HO such that a package substrate, comprising: at least one sidewall of sidewalls of the conductive via protrudes, in a direction parallel to the conductive trace, from a nearest edge of the conductive trace, so that the vias with the lines extending substantially in a horizontal direction and the vias are located to provide electrical connection between layers of lines (HO, [0001]).
Though STRONG qualitatively demonstrated that the vias and traces exhibit significant alignment offsets, STRONG as modified by HO does not explicitly disclose a package substrate comprising: an edge placement error (EPE) of the conductive via on the conductive trace is less than 0.1 micrometers.
ECTON teaches a package substrate (Fig. 6, 120) comprising: an edge placement error (EPE) of the conductive via on the conductive trace is less than 0.1 micrometers (Fig. 1, 100, embodiments of the via-trace structures, 100 disclosed may have alignment offsets less than 5 microns, or approximately equal to 0 microns [0022]; Example 8: an alignment offset between conductive trace and the conductive via is less than 1 micron, [0095]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have STRONG as modified by HO to incorporate the teachings of ECTON, such that a package substrate comprising: an edge placement error (EPE) of the conductive via on the conductive trace is less than 0.1 micrometers, so that the conductive trace and the conductive via may have a required profile, for example the conductive trace may have a bell-shaped cross-section and/or the conductive via may have a flared shape desirable for the package substrate (ECTON, Figs. 2-5, [0014]).
PNG
media_image2.png
765
903
media_image2.png
Greyscale
Regarding Claim 9, STRONG as modified by HO and ECTON teaches the package substrate of claim 8.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein sidewalls of the conductive via (Fig. 1A, 112/114, first via/second via) protrude from respectively proximate edges of the portion of the conductive trace (Fig. 1A, 116, a trace) by a protrusion (Fig. 1B, 190, extension distance, [0048]) that is at least ten times less than a width of the conductive via (Fig. 1C, the first via, 112, the trace, 116 and the second via, 114 have a same width, 192 (e.g. width in the y-direction of Fig. 1C), the width 192 may be between 0.5µm and 25µm [0049]; and the extension distance, 190 from Fig. 1B, may be between 0.1 µm and 7.5 µm, [0048]; therefore, the extension distance, 190 is at least 10 times less than the width of the conductive via as claimed in Claim 1 of the instant application; For example width of conductive via 112/114 = 0.5µm/10 = 0.05µm or approximately 0.1µm as similar to the extension distance, 190; and width of conductive via 112/114 = 25µm/10 = 2.5µm which is similar to extension distance 190 within the range of 7.5µm, [0048]).
HO further teaches the package substrate (Fig. 6A, interconnect structure, [0008]), wherein the at least one sidewall (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias) protrudes (annotated Figure 6A) from the nearest edge (annotated Figure 6A) of the conductive trace (Fig. 6A, 114b, conductive elements) by a protrusion (annotated Figure 6A) that is at least ten times less (annotated Figure 6A) than the width (annotated Figure 6A) of the conductive via (Fig. 6A, 180b, bottom vias).
PNG
media_image1.png
765
1497
media_image1.png
Greyscale
Regarding Claim 10, STRONG as modified by HO and ECTON teaches the package substrate of claim 8.
HO further teaches the package substrate (Fig. 6A, interconnect structure, [0008]), wherein the conductive via (Fig. 6A, 180b, bottom vias) extends away (annotated Figure 6A) from the portion of the conductive trace (Fig. 6A, 180b, bottom vias).
PNG
media_image1.png
765
1497
media_image1.png
Greyscale
Regarding Claim 11, STRONG as modified by HO and ECTON teaches the package substrate of claim 8.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein centerlines of the conductive via (Fig. 1A, center point of the top via, 114, [0048]) and the portion of the conductive trace (Fig. 1A, centerline of the trace, 116, [0048]) are mutually aligned (Fig. 1A, [0048]).
Regarding Claim 12, STRONG as modified by HO and ECTON teaches the package substrate of claim 8.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein:
the conductive via is a first conductive via (Fig. 1A, 112, first via),
the portion of the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) is a first portion (annotated Figure 1A),
the package substrate (Fig. 1A, 101, [0053]) further comprises a second conductive via (Fig. 1A, 114, second via, [0047]) in a third layer (Fig. 1A, 106, second dielectric layer) of the organic dielectric material ([0052]),
the third layer (Fig. 1A, 106, second dielectric layer) is over the second layer (Fig. 1A, 102, conductive layer),
the second conductive via (Fig. 1A, 114, second via, [0047]) is attached to a second portion (annotated Figure 1A) of the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]), and
centerlines of the second conductive via (Fig. 1A, 114, second via, [0047]) and the second portion (annotated Figure 1A) of the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) are not mutually aligned (Figs. 2E/6B, alignment may not be achievable using conventional techniques in which vias and traces are separately patterned (e.g., using multiple masks, one or more masks, and/or one or more via drilling layouts, etc.) and thus are limited in their ability to achieve “perfect” alignment with each other (and therefore exhibit significant alignment offsets) [0061], [0083]).
PNG
media_image4.png
569
792
media_image4.png
Greyscale
Regarding Claim 13, STRONG as modified by HO and ECTON teaches the package substrate of claim 12.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein:
the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) is proximate to a surface of the package substrate (Fig. 1A, 101, [0053]).
Regarding Claim 14, STRONG as modified by HO and ECTON teaches the package substrate of claim 12.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein the organic dielectric material is at least one of a polyimide or an epoxy-based buildup film ([0052]).
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over STRONG, as applied to Claim(s) 1-5, and 7 above, and in view of ECTON (prior art used in the previous OA).
Regarding Claim 15, STRONG teaches a package substrate (Fig. 1A, 101, [0053]), comprising:
a plurality of layers (Fig. 1A, 111, layer assembly) of organic dielectric material ([0052]);
a conductive via (Fig. 1A, 112, first via, [0047]) in a first layer (Fig. 1A, 104, first dielectric layer) of the organic dielectric material ([0052]); and
a conductive trace (Fig. 1A, 116, a trace) in a second layer (Fig. 1A, 106, second dielectric layer) of the organic dielectric material ([0052]);
wherein:
the first layer (Fig. 1A, 104, first dielectric layer) is over (annotated Figure 1A) the second layer (Fig. 1A, 106, second dielectric layer),
the conductive via (Fig. 1A, 112, first via, [0047]) is attached (annotated Figure 1A) to a portion of the conductive trace (Fig. 1A, 116, a trace),
STRONG does not explicitly disclose a package substrate comprising: at least one sidewall of the conductive via has a concave profile, and centerlines of the conductive via and the portion of the conductive trace are mutually aligned.
ECTON teaches a package substrate (Fig. 6, 120) comprising: at least one sidewall (Figs. 3-4, 112, side faces, [0025]) of the conductive via (Figs. 3-4, 102, [0025]) has a concave profile (Fig. 3, the side faces, 112 of the via, 102 may be flared in an hourglass shape, [0025]), and centerlines (Fig. 1B, 108) of the conductive via (Fig. 1B, 102) and the portion of the conductive trace (Fig. 1B, 104) are mutually aligned (the via, 102 and the trace, 104 may be aligned with the centerline, [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified STRONG to incorporate the teachings of ECTON, such that a package substrate comprising: at least one sidewall of the conductive via has a scalloped profile, and centerlines of the conductive via and the portion of the conductive trace are mutually aligned. The curvature on at least one side faces (112) of the via (102) may arise due to the non-uniformity of the fabrication processes use to manufacture the via-trace structure (100), and therefore, the conductive trace and the conductive via may have a required profile, for example the conductive trace may have a bell-shaped cross-section and/or the conductive via may have a flared shape desirable for the package substrate. Additionally, the via (102) and the trace (104) may be aligned with the centerline (108), and such a via-trace structure (100) may be referred to as a “zero misalignment” structure (HO, [0022], [0025-0027]).
PNG
media_image2.png
765
903
media_image2.png
Greyscale
Regarding Claim 16, STRONG as modified by ECTON teaches the package substrate of claim 15.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein:
the at least one sidewall is a first sidewall (annotated Figure 18A),
the conductive via (Fig. 18A 115, third via, ([0048], [0115]) is located at an edge of the conductive trace (Fig. 18A, 116, trace, [0115]),
at least a second sidewall, a third sidewall and a fourth sidewall of the conductive via align exactly with corresponding edges of the conductive trace (annotated Figure 18A),
the second sidewall is opposite to the first sidewall (annotated Figure 18A), and
the third sidewall and the fourth sidewall are mutually opposite and orthogonal to the second sidewall and the first sidewall (annotated Figure 18A).
PNG
media_image5.png
802
1056
media_image5.png
Greyscale
Regarding Claim 17, STRONG as modified by ECTON teaches the package substrate of claim 15.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein:
the conductive via (Fig. 1B, 112, first via) is not located at an edge (annotated Figure 1B) of the conductive trace (Fig. 1B 116, trace), and
ECTON further teaches the package substrate (Fig. 6, 120), wherein all sidewalls (Figs. 3-5, 112, side faces, [0025]) of the conductive via (Figs. 3-4, 102, via, [0025]) have concave profile (Fig. 3, the side faces, 112 of the via, 102 may be flared in an hourglass shape, [0025]).
Regarding Claim 18, STRONG as modified by ECTON teaches the package substrate of claim 15.
ECTON further teaches the package substrate (Fig. 6, 120), wherein edges of the conductive trace (Fig. 5, 104, trace) have concave profile (Fig. 3, the side faces, 112 of the via, 102 may be flared in an hourglass shape, [0025]).
Regarding Claim 19, STRONG as modified by ECTON teaches the package substrate of claim 15.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein:
the conductive via is a first conductive via (Fig. 1A, 112, first via),
the portion of the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) is a first portion (annotated Figure 1A),
the package substrate (Fig. 1A, 101, [0053]) further comprises a second conductive via (Fig. 1A, 114, second via, [0047]) in a third layer (Fig. 1A, 106, second dielectric layer) of the organic dielectric material ([0052]),
the third layer (Fig. 9, 111-1, first two-layer assembly, and a via-trace-via structures, 110-1 and 110-2, [0099]; Fig. 1A, 106, second dielectric layer) is under (annotated Figure 1A with flip-chip or reverse the package substrate) the second layer (Fig. 9, 111-2, second two-layer assembly, and a via-trace-via structures, 110-3 and 110-4, [0099]; Fig. 1A, 102, conductive layer),
the second conductive via (Fig. 1A, 114, second via, [0047]) is attached to a second portion (annotated Figure 1A) of the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]), and
centerlines of the second conductive via (Fig. 1A, 114, second via, [0047]) and the second portion (annotated Figure 1A) of the conductive trace (Fig. 1A, 116, a trace or a line or a transmission line, [0047]) are not mutually aligned (Figs. 2E/6B, alignment may not be achievable using conventional techniques in which vias and traces are separately patterned (e.g., using multiple masks, one or more masks, and/or one or more via drilling layouts, etc.) and thus are limited in their ability to achieve “perfect” alignment with each other (and therefore exhibit significant alignment offsets) [0061], [0083]).
PNG
media_image6.png
821
1068
media_image6.png
Greyscale
Regarding Claim 20, STRONG as modified by ECTON teaches the package substrate of claim 15.
STRONG further teaches the package substrate (Fig. 1A, 101, [0053]), wherein the organic dielectric material is at least one of a polyimide or an epoxy-based buildup film ([0052]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5757077 A – Figure 6
STATEMENT OF RELEVANCE – The integrated circuit, wherein the trench/via (206) is protruded in direction parallel to the bottom metal layer (216).
US 20060180920 A1 – Figure 18B
STATEMENT OF RELEVANCE – The manufacturing method of the semiconductor device, using the conventional single damascene method, wherein the via plugs (118) are protruded in a direction parallel to the lower wiring (117).
US 5942801 A – Figure 6
STATEMENT OF RELEVANCE – The illustration of a borderless via, wherein at least one sidewall of the conductive via or hole (65) has a concave profile.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights