Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claims 1-7 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections, hence 35 U.S.C. 112(b) rejection is withdrawn for claims 1-7.
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues regarding claim 1 and claim 15, Chen’s BM0[Wingdings font/0xE0]M0 coupling is via buried transistor vias (BTVs) and that Chen nowhere discloses the added limitation, i.e., connecting the backside rail to the frontside rail through at least a source contact. Similarly, Applicant argues that Sio relies on TSVs/vias/via rails rather than “a source contact”. Applicant’s arguments regarding Chen and Sio not expressly teaching that the backside power rail is connected to the frontside power rail through at least a source contact are acknowledged.
In response to the amendment, the Examiner relies on Liu (US 20210358901 A1), which teaches source regions electrically coupled to backside metal rails through via contacts, and also teaches coupling to front side metal rails, thereby meeting the amended “through at least a source contact” connection and receipt of the power supply reference.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20220084561 A1) in the view of Sio (US 20210118805 A1) in view of Liu (US 20210358901 A1).
Re: Independent Claim 1 (Currently Amended), Chen discloses an integrated circuit comprising:
a first power rail (Chen, Fig 2, #R1) of a plurality of frontside metal layers (Chen, Fig 2, M0);
a second power rail (Chen, Fig 2, BM0 connected to R1 and R2) of a backside metal layer (Chen, Fig. 2, BM0 associated with the backside power rail),
wherein the second power rail is connected to the first power rail and receives the power supply reference from the first power rail (Chen, Fig. 2 and ¶ [0026], the backside power rail architecture is configured to provide the BTVs as coupling transitions (and/or power delivery transitions) between the backside/second power rails (BM0 of backside power rail R2) and frontside/first power rails (M0 of backside power R1. Accordingly, Chen teaches a power -delivery coupling between frontside rails and backside rails such that the backside rail can receive a supply reference delivered on the frontside rail via the disclosed coupling/transistor architecture).
Chen is silent regarding:
a plurality of frontside metal layers between an off-chip power supply reference and terminals of a plurality of transistors; and a backside metal layer on an opposite side of a silicon substrate than the plurality of frontside metal layers.
However, Sio teaches a plurality of frontside metal layers between an off-chip power supply reference and terminals of a plurality of transistors (Sio, Fig 2, ¶ [0018] - [0019], electrical power/signals are transmitted from 290; and package bumps 290 are in contact with the top frontside interconnects M1-M8. Sio teaches, in ¶ [0029], metal layer M1 is connected to terminals of semiconductor devices 220 through vias, and further teaches that the semiconductor devices 220 can include FinFETS with gate terminals and source/drain terminals).
Sio further teaches a backside metal layer on an opposite side of a silicon substrate than the plurality of frontside metal layers (Sio teaches, in ¶ [0020] - ¶ [0022], a silicon substrate 240 having a first surface 241 on which a backside power distribution network PDN 270 (including conductive power grid PG wires 274/276) is formed, and a second surface 242 opposite the first surface (Sio, ¶ [0025]) on which frontside interconnect/metal layers are formed).
Both Chen and Sio are silent regarding,
the second power rail is connected to the first power rail through at least a source contact.
However, Liu teaches the second power rail is connected to the first power rail through at least a source contact (Liu teaches, in Fig. 4 and its description ¶¶ [0025] – [0031], an integrated circuit 400 having backside metal layers BM1/BM0 and a front side metal layer M0, where source regions S (of transistor/power switches) are electrically coupled to backside metal rails 440/430 in the backside metal layers through via contacts VB/BV0 (i.e., a source-contact coupling), and where via contacts VDB electrically couple the active regions 470/475 (which include the source regions S) to front side metal rails 482 in the front side metal layer M0. Accordingly, Lit teaches a frontside rail (482) connected to backside rail (430/440) through source region S/source-contact path).
Chen, Sio and Liu disclose backside power rail architecture, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to implement the off-chip power supply of Sio in the metal layer layout of Chen in order to be electrically connected to power supplies or other packages to form package on package (PoP) structures (Sio, ¶ [0032]). Further, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Liu’s source-contact-based coupling of backside rails to device source regions in the combined Chen and Sio structure in order to realize the “through at least a source contact” connection, with the predictable benefit of reduced resistance and improved power efficiency via backside rails (Liu. ¶ [0016]).
Re: Claim 2 (Currently Amended), Chen, Sio and Liu disclose all the limitations of claim 1 on which this claim depends.
Sio further discloses,
further comprising a micro through silicon via (TSV) that traverses through silicon substrate layer between the first power rail and the second power rail (Fig 2, ¶ [0015], power distribution network formed on a backside of the IC structure (second power rail), frontside deep through silicon via for delivering power to the backside power distribution network through interconnect layer and device layer).
Re: Independent Claim 15 (Currently Amended), Chen discloses a computing system comprising:
a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks (Chen, ¶¶ [0012]- [0013], computing circuitry and related components on a single chip, which includes memory control circuitry);
an integrated circuit configured to execute the instructions using the source data (Chen, ¶¶ [0012]- [0013], integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for a physical circuit design and/or related structures),
wherein the integrated circuit comprises:
a first power rail (Chen, Fig 2, #R1) of a plurality of frontside metal layers (Chen, Fig 2, M0);
a second power rail (Chen, Fig 2, BM0 connected to R1 and R2) of a backside metal layer (Chen,
Fig. 2, BM0 associated with the backside power rail),
wherein the second power rail is connected to the first power rail and receives the power supply reference from the first power rail (Chen, Fig. 2 and ¶ [0026], the backside power rail architecture is configured to provide the BTVs as coupling transitions (and/or power delivery transitions) between the backside/second power rails (BM0 of backside power rail R2) and frontside/first power rails (M0 of backside power R1. Accordingly, Chen teaches a power -delivery coupling between frontside rails and backside rails such that the backside rail can receive a supply reference delivered on the frontside rail via the disclosed coupling/transistor architecture).
Chen is silent regarding:
a plurality of frontside metal layers between an off-chip power supply reference and terminals of a plurality of transistors; and a backside metal layer on an opposite side of a silicon substrate than the plurality of frontside metal layers.
However, Sio teaches a plurality of frontside metal layers between an off-chip power supply reference and terminals of a plurality of transistors (Sio, Fig 2, ¶ [0018] - [0019], electrical power/signals are transmitted from 290; and package bumps 290 are in contact with the top frontside interconnects M1-M8. Sio teaches, in ¶ [0029], metal layer M1 is connected to terminals of semiconductor devices 220 through vias, and further teaches that the semiconductor devices 220 can include FinFETS with gate terminals and source/drain terminals).
Sio further teaches a backside metal layer on an opposite side of a silicon substrate than the plurality of frontside metal layers (Sio teaches, in ¶ [0020] - ¶ [0022], a silicon substrate 240 having a first surface 241 on which a backside power distribution network PDN 270 (including conductive power grid PG wires 274/276) is formed, and a second surface 242 opposite the first surface (Sio, ¶ [0025]) on which frontside interconnect/metal layers are formed).
Both Chen and Sio are silent regarding,
the second power rail is connected to the first power rail through at least a source contact.
However, Liu teaches the second power rail is connected to the first power rail through at least a source contact (Liu teaches, in Fig. 4 and its description ¶¶ [0025] – [0031], an integrated circuit 400 having backside metal layers BM1/BM0 and a front side metal layer M0, where source regions S (of transistor/power switches) are electrically coupled to backside metal rails 440/430 in the backside metal layers through via contacts VB/BV0 (i.e., a source-contact coupling), and where via contacts VDB electrically couple the active regions 470/475 (which include the source regions S) to front side metal rails 482 in the front side metal layer M0. Accordingly, Lit teaches a frontside rail (482) connected to backside rail (430/440) through source region S/source-contact path).
Chen, Sio and Liu disclose backside power rail architecture, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to implement the off-chip power supply of Sio in the metal layer layout of Chen in order to be electrically connected to power supplies or other packages to form package on package (PoP) structures (Sio, ¶ [0032]). Further, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Liu’s source-contact-based coupling of backside rails to device source regions in the combined Chen and Sio structure in order to realize the “through at least a source contact” connection, with the predictable benefit of reduced resistance and improved power efficiency via backside rails (Liu. ¶ [0016]).
Re: Claim 16 (Currently Amended), Chen, Sio and Liu disclose all the limitations of claim 15 on which this claim depends.
Sio further discloses,
wherein the integrated circuit further comprises a micro through silicon via (TSV) that traverses
through the silicon substrate between the first power rail and the second power rail (Fig 2, ¶ [0015], power distribution network formed on a backside of the IC structure (second power rail), frontside deep through silicon via for delivering power to the backside power distribution network through interconnect layer and device layer).
Claims 3-7 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20220084561 A1) in the view of Sio (US 20210118805 A1) and further in view of Doornbos (US 20210082815 A1).
Re: Claim 3 (Currently Amended), Chen, Sio and Liu disclose all the limitations of claim 2 on which this claim depends.
Sio further teaches power rail connected to the off-chip power supply reference through the plurality of frontside metal layers (Sio, Fig 6 step 612 and ¶ [0044], Sio teaches a power supply in/out layer (package bumps) in contact with the top frontside interconnect (e.g., M8) and that power is transmitted from the bumps to the device through the interconnect stack. Thus, a frontside rail is connected to the off-chip reference through the plurality of frontside metal layers.)
Both Chen and Sio are silent regarding:
further comprising a power switch between the first power rail and a third power rail,
wherein the power switch is configured to: connect the third power rail to the micro TSV, responsive to the power switch being enabled; and disconnect the third power rail from the micro TSV, responsive to the power switch being disabled.
However, Doornbos teaches further comprising a power switch between the first power rail and a third power rail (Doornbos, Fig 8 and ¶ [0037], power switch configured to electrically connect and disconnect a first buried power supply wiring (local/virtual VVDD 66) and a second buried power supply wiring (real VDD 62), i.e., a switch between two rails);
wherein the power switch is configured to:
connect the third power rail to the micro TSV, responsive to the power switch being enabled; and disconnect the first power rail from the micro TSV, responsive to the power switch being disabled (Doornbos further teaches, in Fig 2C and ¶ [0036], that the second buried power supply wiring 62 is connected to first back side power supply wirings 120D by one or more TSVs 100 passing through the substrate; and the PMOS switch controls supply of the first potential from the second buried power supply wiring 62 to the first buried supply wiring 66. Accordingly, Doornbos teaches that responsive to the power switch being enabled (PMOS switch ON), the switched rail (e.g., first buried power supply wiring 66/VVDD, corresponding to the claimed third power rail) is electrically coupled to the TSV-fed rail (wiring 62) and thus connected to the TSV 100; and responsive to the power switch being disabled (PMOS switch OFF), the switched rail (wiring 66/ the claimed third power rail) is electrically isolated from the TSV-fed path and thus disconnected from the TSV 100).
All Chen, Sio. Liu and Doornbos disclose backside power supply architecture, hence analogous art.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to implement Doornbos' power switch topology between local first rail and global/third rail in the structure of Chen in view of Sio in order to provide the power switch configuration to turn on and off power supply to the logic circuit (Doornbos, para [0073]) and to combine Doornbos' power-gating topology where a header switch electively ties a first rail and third rail that is on the TSV path, thereby connecting the third rail to micro TSV when enabled and disconnecting the first rail from the micro TSV when disabled to the architecture of Chen in view of Sio in order to achieve the turning power on/off to logic the switch (Doornbos, ¶ [0071]).
Re: Claim 4 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 3 on which this claim depends.
Chen further discloses:
further comprising a first frontside metal layer of the plurality of frontside metal layers (Chen, Fig 2, ¶ [0027], front metal layer M0 for frontside power rails and backside metal BM0, with BTVs between them. This provides the plurality of frontside metal layers and a concrete first frontside metal layer M0).
Doornbos further teaches frontside metal layer connected to each of an output of the power switch and the first power rail configured to route the power supply reference from the third power rail to the first power rail (Doornbos, Fig 2A-2C, ¶¶ [0035]-[0037], power switch that connects/disconnects a second buried power supply wiring (real VDD rail 62) and first buried power supply wiring (virtual VDD rail 66), with the drain/output of the PMOS switch tied to the first buried wiring, which is continuously formed across the power-supply switch area and logic. Doornbos further makes it clear these are buried power-supply wirings embedded in a first front side insulating layer (i.e. frontside wiring/metal) and explicitly describes the switch configured to electrically connect and disconnect these rails). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to implement Doornbos' power gating structure of metal layers connected to each of an output of the power switch and the first power rail configured to route the power supply reference from the third power rail to the first power rail to the structure of Chen in view of Sio in order to enable the turning power on/off to logic the switch (Doornbos, ¶ [0071]).
Re: Claim 5 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 4 on which this claim depends.
Chen further discloses wherein the first frontside metal layer is further connected to the second power rail (Chen, Fig 2, Chen teaches R2 with a continuous M0 rail, M0 is the frontside metal layer used for the rails, i.e., the first frontside metal layer is connected to the second power rail) and
Doornbos further teaches routes the power supply reference from the first power rail to the second power rail (Doornbos, Fig 2A, ¶ [0034], enabling the switch ties 66 (first rail) to 62 (second rail), 66 is a continuous front-side wiring, so the front side layer carries (routes) the supply between rails when connected). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the front side routing taught by Doornbos to the teaching of Chen in view of Sio in order to achieve the advantage that one power switch circuit can supply the first potential Vdd to two rows of standard cells in the logic circuit (Doornbos, ¶ [0037]).
Re: Claim 6 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 4 on which this claim depends.
Sio further discloses:
wherein one or more of a thickness and a width of the backside metal layer is greater than a thickness and a width of the first frontside metal layer (Sio, ¶ [0031], backside PG wires 274 and 276 have greater lateral and vertical dimensions than metal layers frontside metal layer M1 through M8).
Re: Claim 7 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 4 on which this claim depends.
Chen discloses wherein: each of the first power rail and the second power rail is a metal layer of the plurality of frontside metal layers (Chen, Fig 2 Chen discloses that both power rails R1 and R2 are implemented on frontside metal layer M0).
Doornbos teaches: located closest to active devices of the integrated circuit (Doornbos, the front-side power supply wirings are embedded in the first front-side insulating layer adjacent to the fins i.e., the frontside metal closest to the active device; and the first frontside metal layer is a metal layer adjacent to the first power rail (Doornbos, the buried front-side rail layer with an immediately overlaying interconnect layer coupled by contacts/vias i.e., a frontside metal layer adjacent to the rail layer). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the rail placement and power switch topology taught by Doornbos to the teaching of Chen in order to provide selective turn on/off the power supply to the logic circuit by connecting/disconnecting the frontside rails (Doornbos, ¶ [0073]).
Re: Claim 17 (Currently Amended), Chen, Sio and Liu disclose all the limitations of claim 16 on which this claim depends.
Sio further teaches power rail connected to the off-chip power supply reference through the plurality of frontside metal layers (Sio, Fig 6 step 612 and ¶ [0044], Sio teaches a power supply in/out layer (package bumps) in contact with the top frontside interconnect (e.g., M8) and that power is transmitted from the bumps to the device through the interconnect stack. Thus, a frontside rail is connected to the off-chip reference through the plurality of frontside metal layers.)
Both Chen and Sio are silent regarding:
further comprising a power switch between the first power rail and a third power rail,
wherein the power switch is configured to: connect the third power rail to the micro TSV, responsive to the power switch being enabled; and disconnect the third power rail from the micro TSV, responsive to the power switch being disabled.
However, Doornbos teaches further comprising a power switch between the first power rail and a third power rail (Doornbos, Fig 8 and ¶ [0037], power switch configured to electrically connect and disconnect a first buried power supply wiring (local/virtual VVDD 66) and a second buried power supply wiring (real VDD 62), i.e., a switch between two rails);
wherein the power switch is configured to:
connect the third power rail to the micro TSV, responsive to the power switch being enabled; and disconnect the first power rail from the micro TSV, responsive to the power switch being disabled (Doornbos further teaches, in Fig 2C and ¶ [0036], that the second buried power supply wiring 62 is connected to first back side power supply wirings 120D by one or more TSVs 100 passing through the substrate; and the PMOS switch controls supply of the first potential from the second buried power supply wiring 62 to the first buried supply wiring 66. Accordingly, Doornbos teaches that responsive to the power switch being enabled (PMOS switch ON), the switched rail (e.g., first buried power supply wiring 66/VVDD, corresponding to the claimed third power rail) is electrically coupled to the TSV-fed rail (wiring 62) and thus connected to the TSV 100; and responsive to the power switch being disabled (PMOS switch OFF), the switched rail (wiring 66/ the claimed third power rail) is electrically isolated from the TSV-fed path and thus disconnected from the TSV 100).
All Chen, Sio. Liu and Doornbos disclose backside power supply architecture, hence analogous art.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to implement Doornbos' power switch topology between local first rail and global/third rail in the structure of Chen in view of Sio in order to provide the power switch configuration to turn on and off power supply to the logic circuit (Doornbos, para [0073]) and to combine Doornbos' power-gating topology where a header switch electively ties a first rail and third rail that is on the TSV path, thereby connecting the third rail to micro TSV when enabled and disconnecting the first rail from the micro TSV when disabled to the architecture of Chen in view of Sio in order to achieve the turning power on/off to logic the switch (Doornbos, ¶ [0071]).
Re: Claim 18 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 17 on which this claim depends.
Chen further discloses:
wherein the integrated circuit further comprises a first frontside metal layer of the plurality of frontside metal layers (Chen, Fig 2, ¶ [0027], front metal layer M0 for frontside power rails and backside metal BM0, with BTVs between them. This provides the plurality of frontside metal layers and a concrete first frontside metal layer M0).
Doornbos further teaches frontside metal layer connected to each of an output of the power switch and the first power rail configured to route the power supply reference from the third power rail to the first power rail (Doornbos, Fig 2A-2C, ¶¶ [0035]-[0037], power switch that connects/disconnects a second buried power supply wiring (real VDD rail 62) and first buried power supply wiring (virtual VDD rail 66), with the drain/output of the PMOS switch tied to the first buried wiring, which is continuously formed across the power-supply switch area and logic. Doornbos further makes it clear these are buried power-supply wirings embedded in a first front side insulating layer (i.e. frontside wiring/metal) and explicitly describes the switch configured to electrically connect and disconnect these rails).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to implement Doornbos' power gating structure of metal layers connected to each of an output of the power switch and the first power rail configured to route the power supply reference from the third power rail to the first power rail to the structure of Chen in view of Sio in order to enable the turning power on/off to logic the switch (Doornbos, ¶ [0071]).
Re: Claim 19 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 18 on which this claim depends.
Chen further discloses wherein the first frontside metal layer is further connected to the second power rail (Chen, Fig 2, Chen teaches R2 with a continuous M0 rail, M0 is the frontside metal layer used for the rails, i.e., the first frontside metal layer is connected to the second power rail) and
Doornbos further teaches routes the power supply reference from the first power rail to the second power rail (Doornbos, Fig 2A, ¶ [0034], enabling the switch ties 66 (first rail) to 62 (second rail), 66 is a continuous front-side wiring, so the front side layer carries (routes) the supply between rails when connected).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the front side routing taught by Doornbos to the teaching of Chen in view of Sio in order to achieve the advantage that one power switch circuit can supply the first potential Vdd to two rows of standard cells in the logic circuit (Doornbos, ¶ [0037]).
Re: Claim 20 (Original), Chen, Sio, Liu and Doornbos disclose all the limitations of claim 18 on which this claim depends.
Sio further discloses:
wherein one or more of a thickness and a width of the backside metal layer is greater than a thickness and a width of the first frontside metal layer (Sio, ¶ [0031], backside PG wires 274 and 276 have greater lateral and vertical dimensions than metal layers frontside metal layer M1 through M8).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898