DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 111-120 in the reply filed on 07/23/2025 is acknowledged.
Claims 11-110 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/23/2025.
Claim Objections
Claims 4 and 9 are objected to because of the following informalities:
Claim 4 (claim 9) recites limitation ”the transistor” which should be replaced with
“the at least one transistor”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-10, 111-116, and 118-120 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0294921 to Viswanathan et al. (hereinafter Viswanathan) (the reference US 2014/0110722 by Kub et al. (hereinafter Kub) is presented as evidence).
With respect to claims 1, 113, and 115, Viswanathan discloses a device (e.g., high power microwave transistor (AlGaN/GaN HEFT/HEMT), see the annotated Fig. 3 below) (Viswanathan, Figs. 1-3, ¶0002, ¶0009-¶0033) for transmitting or receiving signals, comprising:
a substrate (e.g., substrate 101 including a host substrate 202 and GaN-based material layer 204/206/208) (Viswanathan, Figs. 2-3, ¶0009, ¶0015) comprising a material (e.g., diamond substrate 202) having an average value of thermal conductivity greater than about 1000 W/mK (e.g., diamond has thermal conductivity of about 2000 W/mK, as evidenced by Kub, ¶0003);
at least one transistor (e.g., GaN transistor 100 in the active region 130) (Viswanathan, Figs. 2-3, ¶0021, ¶0023-¶0025, ¶0030) comprising a material layer (e.g., buffer layer 204/channel layer 206/barrier layer 208 including GaN-based materials) (Viswanathan, Figs. 2-3, ¶0016, ¶0018) and operably connected to the substrate (202); and
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a feature (e.g., substrate opening 160 and through via 143 extending through the diamond substrate 202) (Viswanathan, Fig. 3, ¶0026, ¶0030-¶0032) disposed within at least a portion of the substrate (101), the feature (160/143) having an average etch angle (e.g., a sidewall angle 349 of the through via 143) (Viswanathan, Fig. 3, ¶0031), as measured between a surface of the substrate and a sidewall of the feature.
Further, Viswanathan does not specifically disclose that the feature comprises an aspect ratio greater than or equal to about 1.25:1 (as claimed in claim 1); wherein the aspect ratio comprises a ratio of a height of the feature to a width of the feature (as claimed in claim 113); wherein the feature has a height of at least about 100 microns (as claimed in claim 115).
However, Viswanathan teaches that the lower diameter (344) (Viswanathan, Fig. 3, ¶0030) of the feature (143) is between 10 mm and 120 mm, and the thickness (1330) (Viswanathan, Fig. 13, ¶0057) of semiconductor substrate (101) including the diamond substrate (202) is between about 500 and about 20,000 micro-inches that is 12.7 mm and 508 mm; and that feature (143) (Viswanathan, Fig. 3, ¶0013, ¶0027, ¶0032) is formed in the thermal reservoir region of the diamond substrate (202) to provide heat transfer from the thermally conductive layer (170) formed on the top of the substrate (202) to the back side of the substrate (202) to effectively remove heat from the heat generating region (175) of the transistor.
Thus, a person of ordinary skill in the art would recognize that with a height of the feature (143/160) (e.g., corresponding to the thickness of the substrate 101) of about 100 mm (that is in range of the thickness of the substrate between 12.7 mm and 508 mm as taught by Viswanathan), and a width of the feature (e.g., corresponding to the lower diameter 344 of the through via in the range between 10 mm and 120 mm) of about 100 mm, an aspect ratio of the feature (e.g., corresponding to a ratio of a height of the feature to a width of the feature) would be 1:1, and with the height of the feature of about 100 mm and the width of the feature of about 20 mm, an aspect ratio of the feature would be 5:1.
Further, Viswanathan recognizes that dimensions of the through via impacts the heat transfer capabilities and the operation the high-power transistor device. Thus, dimensions of the through via including width and height are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, dimensions of the through via including width and height as Viswanathan has identified dimensions of the through via including width and height as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific dimensions of the through via including width and height to have the feature that comprises an aspect ratio greater than or equal to about 1.25:1 (as claimed in claim 1); wherein the aspect ratio comprises a ratio of a height of the feature to a width of the feature (as claimed in claim 113); wherein the feature has a height of at least about 100 microns (as claimed in claim 115), in order to provide a semiconductor device with improved heat transfer from the heat generating region of the transistor as taught by Viswanathan (¶0013, ¶0027, ¶0032) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by optimizing dimensions of the through via including width and height within the ranges of the diameter of the through via (corresponding to a width of the feature) and the height of the feature (corresponding to the thickness of the substrate) as taught by Viswanathan to have the device, wherein the feature comprises an aspect ratio greater than about 1.25:1 (as claimed in claim 1); wherein the aspect ratio comprises a ratio of a height of the feature to a width of the feature (as claimed in claim 113); wherein the feature has a height of at least about 100 microns (as claimed in claim 115), in order to provide heat transfer from the thermally conductive layer arranged on the top of the substrate to the back side of the substrate to effectively remove heat from the heat generating region of the transistor (Viswanathan, ¶0013, ¶0027, ¶0032).
Regarding limitations “for transmitting or receiving signals” in a preamble, note that the above recitation is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See MPEP § 2111.02.
Regarding claim 2, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the feature (143/160) (Viswanathan, Figs. 2-3, ¶0026, ¶0030) is disposed within at least a portion of the material layer (e.g., the substrate opening 160 is disposed within the material layer including buffer layer 204/channel layer 206/barrier layer 208 including GaN-based materials).
Regarding claim 3, Viswanathan discloses the device of claim 2. Further, Viswanathan discloses the device, wherein the feature (143/160) (Viswanathan, Figs. 2-3, ¶0030-¶0032) is a via (143).
Regarding claim 4, Viswanathan discloses the device of claim 3. Further, Viswanathan discloses the device, wherein the via (143) (Viswanathan, Figs. 2-3, ¶0030-¶0032) is configured to couple (e.g., through the interconnect 147) the transistor (e.g., GaN transistor 100 in the active region 130) (Viswanathan, Figs. 2-3, ¶0021, ¶0023-¶0025, ¶0030) to a surface (bottom surface 210) of the substrate (202) through the material layer (e.g., buffer layer 204/channel layer 206/barrier layer 208 including GaN-based materials) (Viswanathan, Figs. 2-3, ¶0016, ¶0018) and the substrate (202).the feature (143/160).
Regarding claim 7, Viswanathan discloses the device of claim 1. Further, Viswanathan does not specifically disclose that the feature comprises an aspect ratio greater than or equal to about 5:1.
However, Viswanathan teaches that the lower diameter (344) (Viswanathan, Fig. 3, ¶0030) of the feature (143) is between 10 mm and 120 mm, and the thickness (1330) (Viswanathan, Fig. 13, ¶0057) of semiconductor substrate (101) including the diamond substrate (202) is between about 500 and about 20,000 micro-inches that is 12.7 mm and 508 mm; and that feature (143) (Viswanathan, Fig. 3, ¶0013, ¶0027, ¶0032) is formed in the thermal reservoir region of the diamond substrate (202) to provide heat transfer from the thermally conductive layer (170) formed on the top of the substrate (202) to the back side of the substrate (202) to effectively remove heat from the heat generating region (175) of the transistor.
Thus, a person of ordinary skill in the art would recognize that with a height of the feature (143/160) (e.g., corresponding to the thickness of the substrate 101) of about 200 mm (that is in range of the thickness of the substrate between 12.7 mm and 508 mm as taught by Viswanathan), and a width of the feature (e.g., corresponding to the lower diameter 344 of the through via in the range between 10 mm and 120 mm) of about 20 mm, an aspect ratio of the feature (e.g., corresponding to a ratio of a height of the feature to a width of the feature) would be 10:1, and with the height of the feature of about 200 mm and the width of the feature of about 40 mm, an aspect ratio of the feature would be 5:1.
Further, Viswanathan recognizes that dimensions of the through via impacts the heat transfer capabilities and the operation the high-power transistor device. Thus, dimensions of the through via including width and height are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, dimensions of the through via including width and height as Viswanathan has identified dimensions of the through via including width and height as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific dimensions of the through via including width and height to have an aspect ratio greater than or equal to about 5:1, in order to provide a semiconductor device with improved heat transfer from the heat generating region of the transistor as taught by Viswanathan (¶0013, ¶0027, ¶0032) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by optimizing dimensions of the through via including width and height within the ranges of the diameter of the through via (corresponding to a width of the feature) and the height of the feature (corresponding to the thickness of the substrate) as taught by Viswanathan to have the device, wherein the feature comprises an aspect ratio greater than or equal to about 5:1, in order to provide heat transfer from the thermally conductive layer arranged on the top of the substrate to the back side of the substrate to effectively remove heat from the heat generating region of the transistor (Viswanathan, ¶0013, ¶0027, ¶0032).
Regarding claim 8, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the material layer (e.g., buffer layer 204/channel layer 206/barrier layer 208 including GaN-based materials) (Viswanathan, Figs. 2-3, ¶0016-¶0019) comprises a wide-bandgap semiconductor material (e.g., GaN).
Regarding claim 9, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the transistor is a high electron mobility transistor (GaN/AlGaN HEMT) (Viswanathan, Figs. 1-3, ¶0009, ¶0016-¶0019, ¶0023-¶0025).
Regarding claim 10, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the device is a chip (e.g., an active device disposed on a substrate to be bonded to a package) (Viswanathan, Figs. 1-3, ¶0009, ¶0013, ¶0016-¶0019, ¶0033).
Regarding claim 111, Viswanathan discloses the device of claim 8. Further, Viswanathan discloses the device, wherein the wide-bandgap semiconductor material (204/206/208) (Viswanathan, Figs. 2-3, ¶0015-¶0018) comprises a material (e.g., GaN, InGaN, AlGaN) selected from the group consisting of GaN, AIN, InGaN, InAIN, AIGaN, InGaAIN, Ga2O3, ScAIN, and derivatives and combinations of thereof.
Regarding claim 112, Viswanathan discloses the device of claim 8. Further, Viswanathan does not specifically disclose that the wide-bandgap semiconductor material has an average thickness within a range from about 500 Angstroms to about 1 micron.
However, Viswanathan teaches that the wide-bandgap semiconductor material (204/206/208) (Viswanathan, Figs. 2-3, ¶0015-¶0018) includes the buffer layer (204) with a thickness between 100 Angstroms and 50,000 Angstroms (5 mm), the channel layer (206) with a thickness between 50 Angstroms and 10,000 Angstroms (1 mm), and the barrier layer (208) with a thickness between 50 Angstroms and 1000 Angstroms (0.1 mm) such that the wide-bandgap semiconductor material (204/206/208) has an average thickness within a range from about 200 Angstroms to about 6.1 microns. The claimed range lies inside the range of Viswanathan between 200 Angstroms to about 6.1 microns.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by forming the wide-bandgap semiconductor material having specific thicknesses as taught by Viswanathan to have the device, wherein the wide-bandgap semiconductor material has an average thickness within a range from about 500 Angstroms to about 1 micron, in order to provide a semiconductor device with improved heat transfer from the heat generating region of the transistor (Viswanathan, ¶0013, ¶0027, ¶0032).
Regarding claim 114, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the substrate (101) comprises diamond (e.g., host substrate 202 includes diamond) (Viswanathan, Figs. 2-3, ¶0015).
Regarding claim 116, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the via (143) (Viswanathan, Figs. 2-3, ¶0030-¶0032) is normal to a plane of the substrate (202).
Regarding claim 118, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses the device, wherein the etch angle (e.g., sidewall angle 349) (Viswanathan, Fig. 3, ¶0031) on both sides of the feature (143) is substantially the same.
Regarding claim 119, Viswanathan discloses the device of claim 1. Further, Viswanathan does not specifically disclose the device, wherein the aspect ratio is from about 1.25:1 to about 5:1.
However, Viswanathan teaches that the lower diameter (344) (Viswanathan, Fig. 3, ¶0030) of the feature (143) is between 10 mm and 120 mm, and the thickness (1330) (Viswanathan, Fig. 13, ¶0057) of semiconductor substrate (101) including the diamond substrate (202) is between about 500 and about 20,000 micro-inches that is 12.7 mm and 508 mm; and that feature (143) (Viswanathan, Fig. 3, ¶0013, ¶0027, ¶0032) is formed in the thermal reservoir region of the diamond substrate (202) to provide heat transfer from the thermally conductive layer (170) formed on the top of the substrate (202) to the back side of the substrate (202) to effectively remove heat from the heat generating region (175) of the transistor.
Thus, a person of ordinary skill in the art would recognize that with a height of the feature (143/160) (e.g., corresponding to the thickness of the substrate 101) of about 100 mm (that is in range of the thickness of the substrate between 12.7 mm and 508 mm as taught by Viswanathan), and a width of the feature (e.g., corresponding to the lower diameter 344 of the through via in the range between 10 mm and 120 mm) of about 100 mm, an aspect ratio of the feature (e.g., corresponding to a ratio of a height of the feature to a width of the feature) would be 1:1, and with the height of the feature of about 100 mm and the width of the feature of about 20 mm, an aspect ratio of the feature would be 5:1.
The claimed range of 1.25:1 to about 5:1 lie inside the range of 1:1 to 5:1. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Viswanathan recognizes that dimensions of the through via impacts the heat transfer capabilities and the operation the high-power transistor device. Thus, dimensions of the through via including width and height are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, dimensions of the through via including width and height as Viswanathan has identified dimensions of the through via including width and height as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific dimensions of the through via including width and height to have the aspect ratio is from about 1.25:1 to about 5:1, in order to provide a semiconductor device with improved heat transfer from the heat generating region of the transistor as taught by Viswanathan (¶0013, ¶0027, ¶0032) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by optimizing dimensions of the through via including width and height within the ranges of the diameter of the through via (corresponding to a width of the feature) and the height of the feature (corresponding to the thickness of the substrate) as taught by Viswanathan to have the device, wherein the aspect ratio is from about 1.25:1 to about 5:1, in order to provide heat transfer from the thermally conductive layer arranged on the top of the substrate to the back side of the substrate to effectively remove heat from the heat generating region of the transistor (Viswanathan, ¶0013, ¶0027, ¶0032).
Regarding claim 120, Viswanathan discloses the device of claim 1. Further, Viswanathan does not specifically disclose that the feature has a width of less than or equal to about 40 microns. However, Viswanathan teaches that the lower diameter (344) (Viswanathan, Fig. 3, ¶0030) of the feature (143) is between 10 mm and 120 mm.
The claimed range of less than or equal to about 40 microns overlaps the range between 10 mm and 120 mm. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by forming the through via having specific width (lower diameter) as taught by Viswanathan to have the device, wherein the feature has a width of less than or equal to about 40 microns, in order to effectively remove heat from the heat generating region of the transistor (Viswanathan, ¶0013, ¶0027, ¶0032).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0294921 to Viswanathan in view of Kub et al. (US 2002/0096106, hereinafter Kub’106).
Regarding claims 5 and 6, Viswanathan discloses the device of claim 1. Further, Viswanathan discloses that the etch angle (e.g., the outer etch angle 349 to the lower surface 210 of the substrate 202 is greater than 90 degrees or substantially 90 degrees, thus the inner etch angle of the sidewall 348 is less than 90 degrees or substantially 90 degrees) (Viswanathan, Fig. 3, ¶0031) is less than 90 degrees, but does not specifically disclose that the etch angle is greater than or equal to about 80 degrees (as claimed in claim 5); wherein the etch angle is from about 86 degrees to about 90 degrees (as claimed in claim 6).
However, Viswanathan teaches forming additional high thermal conductivity backside layers on the sloped sidewall surfaces (348) of the via (143) to improve heat transfer from the thermally conductive layers (170) to the back side layer (201) (Viswanathan, Fig. 3, ¶0032).
Further, Green teaches forming a cavity (160) (Green, Fig. 2, ¶0001-¶0002, ¶0015- ¶0020, ¶0025, ¶0040) in the diamond host substrate (212) with the outer cavity wall angle (265) between about 90 degrees and about 110 degrees. Thus, the inner etch angle between the sidewall (265) of Green and lower substrate surface (21) is between 70 degrees and 90 degrees, to provide power efficient GaN RF power transistor on the diamond host substrate.
Further, Hobart teaches that forming tapered sidewall vias (Hobart, Fig. 2, ¶0030-¶0032, ¶0036- ¶0037) having specific geometry allows to more diamond deposited deeper into the vias having an aspect ratio such that the vias have a sufficient depth to penetrate deeply enough into the substrate in order to reach hot points, while having a top-side diameter small enough to permit a high packing density of the vias in the substrate.
Thus, Viswanathan recognizes that a geometry of the through via having sloped sidewalls impacts the heat transfer capabilities and the operation the high-power transistor device. Further, Green recognizes that forming through via having sloped sidewalls with specific etch angles impacts the heat transfer capabilities of the GaN RF power transistor on the diamond host substrate, and Hobart recognizes that forming tapered sidewall vias having specific geometry impacts the heat transfer capabilities of the power device. Thus, a geometry of the through via having sloped sidewalls with specific etch angle is result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a geometry of the through via having sloped sidewalls with specific etch angle as Viswanathan, Green, and Hobart have identified a geometry of the through via having sloped sidewalls with specific etch angle as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific geometry of the through via having sloped sidewalls to have etch angle that is greater than or equal to about 80 degrees (as claimed in claim 5); and the etch angle that is from about 86 degrees to about 90 degrees (as claimed in claim 6), in order to provide a semiconductor device with improved heat transfer from the heat generating region of the transistor as taught by Viswanathan (¶0013, ¶0027, ¶0032), to provide power efficient GaN RF power transistor on the diamond host substrate as taught by Green (¶0040), and to improve heat dissipation and to provide high packing density of the vias in the substrate as taught by Hobart (¶0036- ¶0037) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by optimizing a geometry of the through via having sloped sidewalls with specific etch angle as taught by Viswanathan, Green, and Hobart to have the device, wherein the etch angle is greater than or equal to about 80 degrees (as claimed in claim 5); wherein the etch angle is from about 86 degrees to about 90 degrees (as claimed in claim 6), in order to provide heat transfer from the thermally conductive layer arranged on the top of the substrate to the back side of the substrate to effectively remove heat from the heat generating region of the transistor; to provide power efficient GaN RF power transistor on the diamond substrate; and to improve heat dissipation and to provide high packing density of the vias in the substrate (Viswanathan, ¶0013, ¶0027, ¶0032; Green, ¶0001-¶0002, ¶0040; Hobart, ¶0036- ¶0037).
Claim 117 is rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0294921 to Viswanathan in view of Kub et al. (US 2002/0096106, hereinafter Kub’106).
Regarding claim 117, Viswanathan discloses the device of claim 1. Further, Viswanathan does not specifically disclose that the substrate is polycrystalline or amorphous.
However, Kub’106 teaches depositing AlN/GaN semiconductor layers (Kub’106, ¶0003, ¶0058, ¶0060) on a composite substrate comprising at least one polycrystalline layer including diamond having high thermal conductivity (1000-1500 W/mK), to improve thermal conductivity, microwave insulating characteristics, and optical transparency.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the device of Viswanathan by providing a a composite substrate comprising at least one polycrystalline layer including diamond as taught by Kub’106 to have the device, wherein the substrate is polycrystalline, in order to improve thermal conductivity, microwave insulating characteristics, and optical transparency (Kub’106, ¶0003, ¶0060).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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