DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/03/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 line 3 recited the limitation “a peripheral spacer” is unclear as the same with or different from a peripheral spacer as previously claimed in claim 1.
Claim 6 line 5 recited the limitation “a second sidewall” is unclear as the same with or different from a second sidewall as previously claimed in claim 1.
Claim 21 line 3 recites the limitation "the heating stop layer". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 12-16 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2018/0277546, as disclosed in previous office action).
As for claim 1, Wang et al. disclose in Figs. 1-9 and the related text a semiconductor memory device comprising:
a substrate 100 including a cell region 101 and a peripheral region 102 along a periphery of the cell region (Fig. 9);
a cell region isolation layer 112 in the substrate, the cell region isolation layer 112 along the periphery of the cell region and defining the cell region of the substrate (Fig. 9);
a bit line structure 160 including a cell conductive line 161/163/165 on the cell region and a cell line capping layer 167 on the cell conductive line, the bit line structure 160 including a first sidewall (inner layer of multilayers structure 301, [0028]) on the cell region isolation layer (Fig. 9);
a peripheral gate structure 180a/b including a peripheral gate conductive layer 181/183/185 on the peripheral region and a peripheral capping layer 187 on the peripheral gate conductive layer (Fig. 9), the peripheral gate structure 180a/b including a second sidewall (left 312) on the cell region isolation layer and a third sidewall (right 312/302) opposite the second sidewall (Fig. 9);
a peripheral spacer (right 330) that is not on the second sidewall and is disposed on the third sidewall (Fig. 9);
a lower etching stop layer (outer layer of multiplayer 301, [0028]) extending along a portion of a top surface of the bit line structure, a top surface of the peripheral gate structure and the peripheral spacer (Fig. 9); and
an isolation insulating layer (left 330) in contact with the first sidewall of the bit line structure and the second sidewall of the peripheral gate structure on the cell region isolation layer (Fig. 9).
As for claim 2, Wang et al. disclose the semiconductor memory device of claim 1, wherein the isolation insulating layer 330 is a single layer (Fig. 9, [0032]).
As for claim 3, Wang et al. disclose the semiconductor memory device of claim 1, wherein the first sidewall (inner layer of 301) of the bit line structure and the second sidewall (left 312) of the peripheral gate structure face each other (Fig. 9).
As for claim 4, Wang et al. disclose the semiconductor memory device of claim 1, wherein the first sidewall (inner layer of 301) of the bit line structure facing faces a direction in which the bit line structure extends (Fig. 9).
As for claim 5, Wang et al. disclose the semiconductor memory device of claim 4, further comprising: a cell line spacer 121, wherein the bit line structure further includes a fourth sidewall 115 facing a direction intersecting the direction in which the bit line structure extends (Fig. 9), and the cell line spacer 121 is on the second fourth sidewall 115 of the bit line structure and not (directly) on the first sidewall of the bit line structure (Fig. 9).
As for claim 6, Wang et al. disclose the semiconductor memory device of claim 1, further comprising: a peripheral spacer (right 330), wherein the peripheral gate structure includes a first sidewall (a portion of 301 directly adjacent to gate 180a) in contact with the isolation insulating layer (left 330) and a second sidewall (left 312) opposite the first sidewall (Fig 9), the peripheral spacer (right 330) is on the second sidewall of the peripheral gate structure (fig. 9), and the peripheral spacer is not on the first sidewall of the peripheral gate structure (Fig. 9).
As for claim 12, Wang et al. disclose the semiconductor memory device of claim 1, wherein the isolation insulating layer 330 is along the periphery of the cell region (Fig. 9).
As for claim 13, Wang et al. disclose the semiconductor memory device of claim 1, wherein a bottom surface of the isolation insulating layer 330 is below a top (upper) surface of the cell region isolation layer 112 (as view upside down of Fig. 9).
As for claim 14, Wang et al. disclose in Figs. 1-9 and the related text a semiconductor memory device comprising: a substrate 100 including a cell region 101 and a peripheral region 102 along a periphery of the cell region;
a bit line structure 160 including a cell conductive line 161/163/165 on the cell region and a cell line capping layer 167 on the cell conductive line (Fig. 9);
a peripheral gate structure 180a/b including a peripheral gate conductive layer 181/183/185 on the peripheral region and a peripheral capping layer 187 on the peripheral gate conductive layer (Fig. 9), the peripheral gate conductive layer structure including a first sidewall (left 312) opposite the cell conductive bit line structure in a first (horizontal) direction and a second sidewall (right 302/312) opposite the first sidewall in the first direction (Fig. 9);
a peripheral spacer (right 330) that is not on the first sidewall and is disposed on the second sidewall (Fig. 9);
a lower etching stop layer (301/inner layer of multilayers 301, [0028]) extending along a portion of a top surface of the bit line structure, a portion of a top surface of the peripheral gate structure and the peripheral spacer (Fig. 9); and
an isolation insulating layer (left 330/outer layer of multilayers 301, [0028]) between isolating the cell conductive line bit line structure and the first sidewall (Fig. 9).
As for claim 15, Wang et al. disclose the semiconductor memory device of claim 14, wherein the isolation insulating layer 330 is a single layer (Fig. 9, [0032]).
As for claim 16, Wang et al. disclose the semiconductor memory device of claim 14, wherein the cell conductive line 161/163/165 extends lengthwise in the first direction (Fig. 9).
As for claim 19, Wang et al. disclose in Figs. 1-9 and the related text a semiconductor memory device comprising: a substrate 100 including a cell region 101 and a peripheral region 102 defined around the cell region (Fig. 9);
a cell region isolation layer 112 defining the cell region in the substrate (Fig. 9);
a bit line structure 160 on the substrate in the cell region, the bit line structure including a cell conductive line 161/162/165 extending in a first (horizontal) direction and a cell line capping layer 167 on the cell conductive line (Fig. 9);
a cell gate electrode 123/125 in the substrate in the cell region (Fig. 9), the cell gate electrode extending in a second (vertical) direction to intersect the cell conductive line (Fig. 9), the second direction intersecting the first direction (Fig. 9);
a peripheral gate structure 180a/b on the substrate in the peripheral region (Fig. 9), the peripheral gate structure including a peripheral gate conductive layer 181/183/185 and a peripheral capping layer 187 on the peripheral gate conductive layer (Fig. 9);
an isolation insulating layer (left 330) isolating the bit line structure and the peripheral gate structure from each other (Fig. 9), the isolation insulating layer (left 330) on the cell region isolation layer 112 between the bit line structure and the peripheral gate structure, and the isolation insulating layer being a single layer (Fig. 9);
a bit line spacer 115 on sidewalls of the bit line structure facing the second direction (Fig. 9), and the bit line spacer 115 not on sidewalls of the bit line structure facing the first direction (Fig. 9);
a peripheral spacer (left 312) on a sidewall of the peripheral gate structure facing the second direction and a sidewall (right 312) of the peripheral gate structure facing the first direction in which the isolation insulating layer (left 330) is not disposed (Fig. 9), and the peripheral spacer (left 312) not on a sidewall of the peripheral gate structure facing the first direction in which the isolation insulating layer (left 330) is disposed (Fig. 9); and
a lower etching stop layer 301 extending along a portion of a top surface of the bit line structure, a portion of a top surface of the peripheral gate structure and the peripheral spacer (Fig. 9).
As for claim 20, Wang et al. disclose the semiconductor memory device of claim 19, further comprising: a peripheral interlayer insulating layer (right 330) around the peripheral gate structure on the substrate in the peripheral region (fig. 9), wherein the peripheral interlayer insulating layer (right 330) is not on a sidewall of the peripheral gate structure in which the isolation insulating layer (left 330) is disposed and the peripheral spacer (left 312) is not disposed (fig. 9).
As for claim 21, Wang et al. disclose the semiconductor memory device of claim 1, wherein the isolating insulating layer (left 330) isolates the lower etching stop layer (inner layer of multilayer 301, [0028]) extending along the portion of the top surface of the bit line structure (Fig. 9) and the lower heating stop layer (inner layer of multilayer 301, [0028]) extending along the portion of the top surface of the peripheral gate structure and the peripheral spacer (Fig. 9).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-11 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Chung et al. (US 2011/0156119 as disclosed in previous office action) and Ryu et a. (US 2020/0312852 as disclosed in previous office action).
As for claim 8, Wang et al. disclose the semiconductor memory device of claim 1, wherein the isolation insulating layer (left 330) includes a first (upper) portion and a second (lower) portion, the first portion of the isolation insulating layer is in contact with the first sidewall of the bit line structure and the second sidewall of the peripheral gate structure (fig. 9), the second portion of the isolation insulating layer extends along at least a portion of the lower etching stop layer (Fig. 9).
Wang et al. do not disclose a bit line contact plug and a peripheral gate contact plug, wherein the bit line contact plug penetrates through the second portion of the isolation insulating layer and the lower etching stop layer and is electrically connected to the cell conductive line, and the peripheral gate contact plug penetrates through the second portion of the isolation insulating layer and the lower etching stop layer and is electrically connected to the peripheral gate conductive layer.
Chung teaches in FIG. 2A and related text, a peripheral gate contact plug (182b, [0093]), wherein the peripheral gate contact plug (182b) penetrates through a portion of an isolation insulating layer (175, [0093]) and the lower etching stop layer 173 and is electrically connected to the peripheral gate conductive layer (170), in order to provide electrical signals to the peripheral gate conductive layer.
Ryu teaches in FIG. 11C and related text, a bit line contact plug (173, [0113]), wherein the bit line contact plug 173 penetrates through a portion of an isolation insulating layer (170, [0113]) and the lower etching stop layer 145 and is electrically connected to a cell conductive line (120c), in order to provide electrical signals to the bit line (120c is part of bit line 127c, [0160]).
Wang, Chung and Ryu are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang in view of Ryu and Chung because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to include the claimed peripheral gate contact plug as taught by Chung, and the claimed bit line contact plug as taught by Ryu, with the purpose of providing electrical signals to the peripheral gate and the bit line, respectively. One of ordinary skill in the art would recognize the device of Wang requires some form of contact structure to provide electrical signals to the peripheral gate and the bit line.
Regarding claim 9, Wang as modified by Chung and Ryu teaches substantially the entire claimed structure as recited in claim 8.
The combined structure of Wang, Chung and Ryu further teaches wherein the first portion of the isolation insulating layer is spaced apart from the bit line contact plug and the peripheral gate contact plug.
The bit line contact plug (173) of Ryu contacts a horizontal surface of the cell conductive line of Ryu (120c), and the peripheral gate contact plug (182b) of Chung contacts a horizontal surface of the peripheral gate contact plug (182b) of Chung. These contact regions correspond to the second portion of the isolation insulating layer (301) of Wang.
Regarding claim 10, Wang as modified by Chung and Ryu teaches substantially the entire claimed structure as recited in claim 8.
The combined structure of Wang, Chung and Ryu further teaches wherein the first portion of the isolation insulating layer is in contact with at least one of the bit line contact plug and the peripheral gate contact plug.
Since the first portion of the isolation insulating layer (301) of Wang is part of the same layer as the second portion of the isolation insulating layer (301) of Wang, anything in contact with the first portion is also in contact with the second portion (at least thermal contact).
Regarding claim 11, Wang as modified by Chung and Ryu teaches substantially the entire claimed structure as recited in claim 10.
The combined structure of Wang, Chung and Ryu further teaches wherein a portion of at least one of a bottom surface of the bit line contact plug and a bottom surface of the peripheral gate contact plug is in contact with the first portion of the isolation insulating layer.
The bit line contact plug (173) of Ryu and the peripheral gate contact plug (182b) of Chung would both have at least one surface (which could be a bottom surface) in contact with the isolation insulating layer (301) of Wang. Since the first portion of the isolation insulating layer (301) of Wang is part of the same layer as the second portion of the isolation insulating layer (301) of Wang, anything in contact with the first portion is also in contact with the second portion (at least thermal contact).
As for claim 17, Wang et al. disclose the semiconductor memory device of claim 14, further comprises the isolation insulating layer (left 330/outer layer of multilayers 301) includes a first portion (left 330) and a second portion(outer layer of multilayers 301), the first portion of the isolation insulating layer is between the bit line structure and the first sidewall (Fig. 9), the second portion of the isolation insulating layer extends along at least a portion of the lower etching stop layer (Fig. 9).
Wang et al. do not disclose a bit line contact plug and a peripheral gate contact plug, wherein the bit line contact plug penetrates through the second portion of the isolation insulating layer and the lower etching stop layer and is electrically connected to the cell conductive line, and the peripheral gate contact plug penetrates through the second portion of the isolation insulating layer and the lower etching stop layer and is electrically connected to the peripheral gate conductive layer.
Chung teaches in FIG. 2A and related text, a peripheral gate contact plug (182b, [0093]), wherein the peripheral gate contact plug (182b) penetrates through a portion of an isolation insulating layer (175, [0093]) and the lower etching stop layer 173 and is electrically connected to the peripheral gate conductive layer (170), in order to provide electrical signals to the peripheral gate conductive layer.
Ryu teaches in FIG. 11C and related text, a bit line contact plug (173, [0113]), wherein the bit line contact plug 173 penetrates through a portion of an isolation insulating layer (170, [0113]) and the lower etching stop layer 145 and is electrically connected to a cell conductive line (120c), in order to provide electrical signals to the bit line (120c is part of bit line 127c, [0160]).
Wang, Chung and Ryu are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang in view of Ryu and Chung because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to include the claimed peripheral gate contact plug as taught by Chung, and the claimed bit line contact plug as taught by Ryu, with the purpose of providing electrical signals to the peripheral gate and the bit line, respectively. One of ordinary skill in the art would recognize the device of Wang requires some form of contact structure to provide electrical signals to the peripheral gate and the bit line.
As for claim 18, Wang et al. disclose the semiconductor memory device of claim 17, wherein a top surface of the second portion (outer layer of multilayers 301) of the isolation insulating layer includes a concave portion recessed toward the substrate (Fig. 9).
Response to Arguments
Applicant's response filed on 09/24/2025 is acknowledged and is answered as follows.
Applicant’s arguments with respect to claim(s) 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see pgs. 12-14, with respect to the rejections of claims 1 and 14 that Wang et al. do not teach “a lower etching stop layer extending along a portion of a top surface of the bit line structure, a top surface of the peripheral gate structure and the peripheral spacer” have been fully considered but they are not persuasive in view of the following reasons.
Wang et al. teach in Fig. 9 and the related text a lower etching stop layer (outer layer of multiplayer 301, [0028]) extending along a portion of a top surface of the bit line structure, a top surface of the peripheral gate structure 180 and the peripheral spacer (right 330). Therefore, Wang et al. still disclose claimed invention.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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