DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 15 January 2026 is acknowledged.
Applicant's election with traverse of Species A with respect to Species B in the reply filed on 15 January 2026 is acknowledged. The traversal is on the ground(s) that Species A and B are structured in the same manner, and only represent swapping of the virtual power supply and true power supply. This is not found persuasive because swapping the power supplies represents a structural difference, with diverging interconnect routing design for each scenario.
The requirement is still deemed proper and is therefore made FINAL.
Claims 5-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species B, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 15 January 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al (US 20210202385 A1, hereinafter “Huang”).
Regarding Claim 1 - Huang discloses a method for forming a semiconductor device, the method comprising: forming a front end of line structure (RX [0029] and Fig. 7) comprising a gate (GT [0031] and Fig. 7); forming a back end of line structure on a first surface of the front end of line structure (Mx [0033] and Fig. 7); and forming a backside power delivery network on a second surface of the front end of line structure opposite the first surface (BMy [0037] and Fig. 7); wherein source and drain regions on a first side of the gate are connected to the backside power delivery network (via VB-v2 [0037] and Fig. 7) and source and drain regions on a second side of the gate are connected to the back end of line structure (via Via-v1 [0033] and Fig. 7).
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Regarding Claim 2 - Huang further discloses the method of claim 1, wherein the back end of line structure comprises a power supply (M0 supplies VddL as Vdd1 [0033] and Fig. 7).
Regarding Claim 3 - Huang further discloses the method of claim 2, further comprising forming a virtual power supply (BM0 supplies VddH as Vdd2 [0037] and Fig. 7) between the front end of line structure and the backside power delivery network (Fig. 7).
Regarding Claim 4 - Huang further discloses the method of claim 3, wherein the power supply is connected to the source and drain regions on the second side of the gate (2nd Side in annotated Fig. 7) and the virtual power supply is connected to the source and drain regions on the first side of the gate (1st Side in annotated Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 20210202385 A1, hereinafter “Huang”), in view of Akkaya et al (US 20250201281 A1, hereinafter “Akkaya”).
Regarding Claim 8 - Huang discloses all the limitations of claim 1.
Huang fails to disclose the gate is connected to a boost signal on the back end of line structure and a backside boost signal line between the backside power delivery network and the front end of line structure.
However, Akkaya discloses the gate is connected to a boost signal on the back end of line structure (by C1’ between 516 and 518 [0039] and Fig. 5) and a backside boost signal line between the backside power delivery network and the front end of line structure (304 formed as C1 between 546 and 548 [0035] and Fig. 5).
Akkaya discloses a transistor IC analogous to Huang. Akkaya teaches capacitively coupling the interconnects on the front and back sides of the IC to boost gate voltage of critical nodes for the benefit of more reliable device performance (Akkaya [0018]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Juan in a kayak to boost gate voltage by capacitively coupling interconnects for the benefit of more reliable device performance.
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Regarding Claim 9 - Huang modified by Akkaya discloses all the limitations of claim 8.
The combination of Huang and Akkaya further discloses the gate comprises a gate extension (1802 [0089] and Fig. 18A) that extends through a shallow trench isolation region of the front end of line structure (902 [0048] and Fig. 18A).
Regarding Claim 10 - Huang modified by Akkaya discloses all the limitations of claim 9.
The combination of Huang and Akkaya further discloses the gate extension is directly connected to the backside boost signal line (1804 [0090] and Fig. 18A).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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