DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges the amendment to claim 1 in the reply dated 24 July 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al (US 20230352408 A1, hereinafter “Jung”).
Regarding Claim 1 - Jung discloses a method for forming a semiconductor device, the method comprising: forming a front end of line structure comprising a gate (18 [0021] and Fig. 2B); forming a back end of line structure on a first surface of the front end of line structure (48 [0015] and Fig. 2A); and forming a backside power delivery network on a second surface of the front end of line structure opposite the first surface (60 [0027] and Fig. 2A); wherein source and drain regions on a first side of the gate are connected to the backside power delivery network (14_1 [0020] and Fig. 2A) and source and drain regions on a second side of the gate are connected to the back end of line structure (14_2 [0022] and Fig. 2A); and wherein the source and drain regions on the first side of the gate are connected to the backside power delivery network through a frontside source/drain contact that is shorted to a via-to-backside power rail (14_1 connected to 60 through 22, 22P, 52, and 54 [0027] and Fig. 2A).
PNG
media_image1.png
545
581
media_image1.png
Greyscale
PNG
media_image2.png
584
566
media_image2.png
Greyscale
Regarding Claim 2 - Jung further discloses the method of claim 1, wherein the back end of line structure comprises a power supply (BSPDN [0027] and Figs. 2A and 2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al (US 20230352408 A1, hereinafter “Jung”), in view of Huang et al (US 20240008243 A1, hereinafter “Huang”).
Regarding Claim 3 - Jung discloses all the limitations of claim 1.
Jung fails to disclose forming a virtual power supply between the front end of line structure and the backside power delivery network.
However, Huang discloses forming a virtual power supply (BM0 supplies VddH as Vdd2 [0037] and Fig. 7) between the front end of line structure and the backside power delivery network (Fig. 7).
Huang discloses an analogous MOSFET IC power delivery network to Jung. Huang teaches using a virtual power supply (VddH) for critical logic blocks, as well as an unboosted power supply (VddL) to reduce power and maintain circuit performance (Huang [0018]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Jung and Huang to form a virtual power supply between the front end of line structure and the backside power delivery network for the benefit of reducing power and maintaining circuit performance.
Regarding Claim 4 – Jung modified by Huang discloses all the limitations of claim 3.
The combination of Jung and Huang further discloses the power supply is connected to the source and drain regions on the second side of the gate (2nd Side in annotated Fig. 7) and the virtual power supply is connected to the source and drain regions on the first side of the gate (1st Side in annotated Fig. 7).
PNG
media_image3.png
504
760
media_image3.png
Greyscale
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 20210202385 A1, hereinafter “Huang”), in view of Akkaya et al (US 20250201281 A1, hereinafter “Akkaya”).
Regarding Claim 8 - Huang discloses all the limitations of claim 1.
Huang fails to disclose the gate is connected to a boost signal on the back end of line structure and a backside boost signal line between the backside power delivery network and the front end of line structure.
However, Akkaya discloses the gate is connected to a boost signal on the back end of line structure (by C1’ between 516 and 518 [0039] and Fig. 5) and a backside boost signal line between the backside power delivery network and the front end of line structure (304 formed as C1 between 546 and 548 [0035] and Fig. 5).
Akkaya discloses a transistor IC analogous to Huang. Akkaya teaches capacitively coupling the interconnects on the front and back sides of the IC to boost gate voltage of critical nodes for the benefit of more reliable device performance (Akkaya [0018]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Juan in a kayak to boost gate voltage by capacitively coupling interconnects for the benefit of more reliable device performance.
PNG
media_image4.png
490
707
media_image4.png
Greyscale
Regarding Claim 9 - Huang modified by Akkaya discloses all the limitations of claim 8.
The combination of Huang and Akkaya further discloses the gate comprises a gate extension (1802 [0089] and Fig. 18A) that extends through a shallow trench isolation region of the front end of line structure (902 [0048] and Fig. 18A).
Regarding Claim 10 - Huang modified by Akkaya discloses all the limitations of claim 9.
The combination of Huang and Akkaya further discloses the gate extension is directly connected to the backside boost signal line (1804 [0090] and Fig. 18A).
PNG
media_image5.png
444
520
media_image5.png
Greyscale
Conclusion
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights