DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see A, filed on 12/10/2025, with respect to the rejection(s) of claims 1 and 19 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of U.S. Patent Application Publication No. US 20210126120 A1 (".
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite or for failing to particularly point out distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, the term “a specified crystal quality threshold” in claim 7 is a relative term which renders the claim indefinite. The term “a specified crystal quality threshold” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purposes of compact prosecution, the examiner interprets the language of “a specified crystal quality threshold” as being a crystal quality sufficient to form a functional device.
Moreover, the claim merely discloses that a channel layer has crystallinity structure and that crystalline structure exceeds a specified crystal quality threshold. without a clear definition of the threshold, a person having ordinary skills in the art will find it difficult to determine if the claim is just merely stating crystalline characteristics of the channel layer or a specific value of the crystal quality threshold of the channel layer was considered in determining the thickness of the heterostructure. without a clear value for the crystal quality threshold and the fact that all crystalline layers would have a crystal quality threshold, the limitation is unclear.
For examination purpose, the claim would be understood such that the limitation "exceeds a specific crystal quality threshold" is considered as a mere indication of the characteristics of a crystalline channel layer.
Claim 8 is also rejected as it depends upon claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,5,6,10,19 and 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Piedra et al. (US20210126120A1).
Regarding claim 1, Fig.3 of Piedra teaches a device having a high electron mobility transistor, the device comprising:
the high electron mobility transistor, the high electron mobility transistor comprising:
a substrate layer 302 (para.0050); and
a gallium nitride (GaN) based heterostructure (heterostructure formed by layer 308 and layer 310) overlying the substrate layer 302, the GaN-based heterostructure including:
a channel layer 308 (para.0054) of a first compound semiconductor material 308 disposed proximate to the substrate layer 302; and
a barrier layer 310 (para.0056) of a second compound semiconductor material disposed adjacent to the channel layer 308 and forming a two-dimensional electron gas (2DEG) at a junction between the channel layer 308 and the barrier layer 310, the 2DEG having an electron concentration; and
a buried implant region 304 (para.0051) formed by an implanted activated dopant and disposed at least partially within the substrate layer 302 and extending laterally from a region underlying a source terminal 318 (para.0058) of the transistor to a region between a gate 316 (para.0057) and drain 320 (para.0058) terminals of the transistor, the buried implant region 304 configured to modulate an electric field (para.0053, wherein the conductive layer 304 can be configured as a back-side field plate to shape an electric field produced by compound semiconductor device of the integrated circuit 300) between the gate 316 and drain terminals 320 of the transistor, wherein a concentration of the activated dopant is matched to an electron concentration of the 2DEG (wherein, the concentrations match because the concentrations complement one another to form a functional device; wherein "match" can be defined/interpreted as to adapt or suit so that a balanced or harmonious result is achieved; cause to correspond ).
Regarding claim 5, Piedra appears not to explicitly disclose the device of claim 1 wherein the buried implant region is disposed within a vertical distance of 150 to 400 nanometers of the 2DEG.
However, Piedra discloses that the thickness of the high energy bandgap material overlaps or lies inside the claimed range (paragraphs [0041], [0042], [0050], [0054]). According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05, I), "[i]n the case where the claimed ranges 'overlap or lie inside ranges disclosed by the prior art' a prima facie case of obviousness exists." Accordingly, it would have been obvious to a person having ordinary skill in the art to which said subject matter pertains to form the high energy bandgap material to have a thickness between 150nm and 400nm.
Regarding claim 6, Fig.10 of Piedra teaches the device of claim 1, further comprising the gate terminal 316 (para.0057), wherein the gate terminal 316 includes a free-standing gate head. Applicant’s specification defines a free-standing gate as a T-gate or T-shaped gate that is not supported by a dielectric. Piedra teaches, in para.0134, wherein a compound semiconductor device has a T-shaped gate electrical contact that is surrounded by air gap.
Regarding claim 10, Piedra further teaches the device of claim 1, further comprising a nucleation layer 306 (para.0054) interposed between the channel layer 308 (para.0054) and the substrate 302 (para.0050), the nucleation layer 306 formed after a temperature ramp up with nitrogen gas. The process limitation of "the nucleation layer formed after a temperature ramp up with nitrogen gas" found in product claim 10 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Therefore, claim 10 does not require the nucleation layer to be formed by temperature ramp up with nitrogen gas, but simply that the nucleation layer interposed between the channel and the substrate.
Regarding claim 19, Fig.3 of Piedra teaches a device having a high electron mobility transistor, the device comprising:
the high electron mobility transistor, the high electron mobility transistor comprising:
a substrate layer 302 (para.0050);
a buried implant region 304 (para.0051) including first and second dopants implanted within the substrate layer 302, the buried implant region 304 extending laterally from a region underlying a source terminal 318 (para.0058) of the transistor to a region between a gate 316 (para.0057) and drain terminals 320 (para.0058) of the transistor, the buried implant region 304 (para.0053, wherein the conductive layer 304 can be configured as a back-side field plate to shape an electric field produced by compound semiconductor device of the integrated circuit 300) configured to modulate an electric field between the gate 316 and drain 320 terminals of the transistor;
a nucleation layer 306 (para.0054) overlying the substrate 302 and the buried implant region 304;
a channel layer 308 (para.0056) of a first compound semiconductor material overlying the nucleation layer 306; and
a barrier layer 310 (para.0056) of a second compound semiconductor material overlying the channel layer 308 and forming a two-dimensional electron gas (2DEG) at a first interface between the channel layer 308 and the barrier layer 310;
wherein the channel layer 308 and the nucleation layer 306 are grown to have a lattice match at a second interface between the nucleation layer 306 and the channel layer 308 that enables a height of the channel layer 308 and the nucleation layer 306 to be smaller than a threshold vertical distance between the buried implant region 304 and the 2DEG to enable the buried implant region to modulate an electric field between the gate 316 (para.0057) and drain 320 (para.0058) terminals, wherein a concentration of at least one of the first and second dopants is matched to an electron concentration of the 2DEG (wherein, the concentrations match because the concentrations complement one another to form a functional device; wherein "match" can be defined/interpreted as to adapt or suit so that a balanced or harmonious result is achieved; cause to correspond ).
Regarding claim 20, Piedra further teaches the transistor of claim 19, wherein the nucleation layer 306 (para.0054) is formed after a temperature ramp up step using nitrogen gas. The process limitation of "the nucleation layer formed after a temperature ramp up with nitrogen gas" found in product claim 10 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Therefore, claim 10 does not require the nucleation layer to be formed by temperature ramp up with nitrogen gas, but simply that the nucleation layer interposed between the channel and the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Piedra et al. (US20210126120A1) in view of IUCOLANO et al. (US20190229203A1).
Regarding claim 3, Piedra does not teach wherein the concentration of the activated dopant is matched to the electron concentration of the 2DEG so that a voltage applied between the gate and drain terminals of the transistor concurrently depletes respective concentrations of holes and electrons in overlapping regions of the implant region and the 2DEG.
IUCOLANO teaches, in para.0062, wherein HEMT achieves a good compromise between high threshold voltage and low ON resistance due to the thermal annealing to activate dopant impurities in an epitaxial layer with a high concentration of dopant impurities is carried out following upon a step of selective removal of portions of said epitaxial layer, and in particular of the portions external to a gate region of the HEMT. In doing so, the dopant impurities may diffuse only towards regions of the heterostructure underlying the gate region in order to increase the threshold voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to activate dopant impurities in an epitaxial layer with a high concentration of dopant impurities, as taught by IUCOLANO, because in doing so, doing so, the dopant impurities may diffuse only towards regions of the heterostructure underlying the gate region and thus, increases the threshold voltage (IUCOLANO, [para.0062]).
Regarding claim 4, Piedra does not teach wherein the concentration of the activated dopant decreases laterally from a region underlying the gate terminal to a region underlying the drain terminal.
IUCOLANO teaches, in the abstract, wherein thermal annealing of the doped gate region is carried out so as to cause a diffusion of the dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the diffusion of the dopant impurities towards regions of the heterostructure underlying the gate region, as taught by IUCOLANO, in order to increase the threshold voltage, whereas it may not diffuse in the regions of the heterostructure that connect the gate region to the source and drain regions, thus preventing an increase in the ON state resistance (IUCOLANO, [para.0062]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Piedra et al. (US20210126120A1) in view of Miyoshi et al. (US20050274980A1).
Regarding claim 7, Piedra does not teach wherein the channel layer has a crystalline structure that exceeds a specified crystal quality threshold to determine a thickness of the heterostructure, wherein the specified crystal quality threshold is defined by a rocking curve.
Fig.1 of Miyoshi discloses wherein providing a highly crystalline underlying layer containing AlN at an interface between a substrate and a GaN layer in a HEMT having an AlGAN/GaN/GaN heterostructure to improve the crystallinity of a channel layer and an electron supply layer which are formed on the underlying layer, thereby increasing the performance of the HEMT (Miyoshi, [para.0008]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the highly crystalline underlying layer containing AlN at an interface between a substrate and a GaN layer in a HEMT having an AlGAN/GaN heterostructure, as taught by Miyoshi, to improve the crystallinity of a channel layer and an electron supply layer which are formed on the underlying layer, thereby increasing the performance of the HEMT (Miyoshi, [para.0008]).
Moreover, the limitation is a characteristic of the claim device and not a structural limitation. Thus, a device such as that of Piedra, as modified by Miyoshi, which obviously has the same structure as the claimed invention is expected to also have the claimed characteristics (rocking curve).
Furthermore, it is noted that the claim does not specify a specific threshold, nor does it disclose variables that were considered to determine the threshold needed in determining the desired thickness. Thus, a device such as Piedra, as modified by Miyoshi, having a crystalline channel layer and thickness of the heterostructure would inherently meet the claimed limitation.
Regarding claim 8, Piedra does not explicitly disclose wherein the rocking curve includes a peak having a full width half max below 300 arc-seconds.
Miyoshi teaches, in para.0040, wherein the third semiconductor layer 7 is preferably formed so that the X-ray rocking curve FWHM for the (002) plane is not greater than 250 seconds.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Miyoshi’s third semiconductor layer 7 is preferably formed so that the X-ray rocking curve FWHM for the (002) plane is not greater than 250 seconds, in the teachings of Piedra for the purpose of providing appropriate control of the growth conditions of the semiconductor layers with high crystallinity (Miyoshi, [para.0040]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Piedra et al. (US20210126120A1) in view of Janzén et al. (US20170365469A1).
Regarding claim 9, Piedra further teaches the device of claim 1, wherein the GaN-based heterostructure (para.0022, wherein heterostructure that includes a first compound semiconductor and one or more second compound semiconductors can include an AlN layer coupled with an InAlN layer) includes an aluminum nitride nucleation layer, and
Piedra does not disclose wherein the aluminum nitride nucleation layer has a rocking curve with a peak having a full width half max below 100 arc-seconds.
Fig.3b of Janzén discloses rocking curves of the AlN (002) peak of AlN nucleation layers grown by the method disclosed herein using temperature ramp up and by the prior art method, respectively. The AlN (002) peak of the AlN nucleation layer grown by the present method has a FWHM of 42 arcsec while the AlN (002) peak of the reference AlN nucleation layer grown by the prior art method is wider and has a FWHM of 99 arcsec (para.0119).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Janzén’s AlN (002) peak of the AlN nucleation layer that has a FWHM of 42 arcsec while the AlN (002) peak of the reference AlN nucleation layer grown by the prior art method is wider and has a FWHM of 99 arcsec, in the teachings of Piedra because it improves crystallinity of the AlN nucleation layer (Janzén, [para.0120]).
ConclusionAny inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights