Prosecution Insights
Last updated: April 19, 2026
Application No. 18/049,585

ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION

Non-Final OA §102
Filed
Oct 25, 2022
Examiner
LEE, ERIC D
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Xilinx, Inc.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
523 granted / 644 resolved
+13.2% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
13 currently pending
Career history
657
Total Applications
across all art units

Statute-Specific Performance

§101
18.7%
-21.3% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 644 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma et al., hereinafter Ma, US Patent No. 8,352,229. Regarding Claim 1, Ma teaches a method, comprising: generating, using computer hardware (Ma Col. 4, Lines 38-44, see processor), a simulation database for a circuit design and processed design data for the circuit design (Ma Col. 2, Lines 17-31, Col. 5, Lines 15-31, Col. 6, Lines 18-67 and Col. 7, Lines 1-8, where source code contributions and a simulation model are generated and provided by the HLMS, source code contributions being a simulation database and the simulation model being processed design data), wherein the processed design data includes source files for the circuit design referenced by the simulation database (Ma Col. 5, Lines 15-38, wherein the simulation models are descriptions of the circuit design to be simulated, i.e. source files); exporting the simulation database and the processed design data from a host integrated development environment (IDE) (Ma Col. 5, Lines 5-14, wherein the source code contributions and the simulation model are exported by the HLMS and received by the JIT compiler, the HLMS being a host integrated development environment); providing a template writer configured to generate a simulation script for the circuit design using the simulation database (Ma Col. 5, Lines 5-14, wherein the JIT compiler is a template writer that generates a simulation engine, simulation engines including scripts as taught in Col. 1, Lines 36-41); and generating the simulation script by executing the template writer, wherein the simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported (Ma Col. 1, Lines 5-14, Col. 4, Lines 15-21, and Col. 13, Lines 32-55, wherein the simulation engine is generated by the JIT compiler using the source code contributions and the simulation model, the source code contributions including designer specified parameters, e.g. components, to be included in the simulation engine). Regarding Claim 2, Ma further teaches wherein the template writer calls one or more class library application programming interfaces that operate on the simulation database to generate the simulation script (Ma Col. 4, Lines 15-21 and Col. 6, Lines 37-50, wherein the JIT compiler generates a simulation engine that conforms to APIs). Regarding Claim 3, Ma further teaches wherein the class library application programming interfaces include one or more user-contributed application programming interfaces that extend functionality of the template writer (Ma Col. 13, Lines 32-64, wherein APIs are specified by the designer upon designating software components for inclusion in the simulation engine, extending the functionality to third party software). Regarding Claim 4, Ma further teaches wherein the simulation database includes complete information for compiling, elaborating, and simulating the circuit design (Ma Col. 5, Lines 1-4 and Col. 6, Lines 38-62, wherein the source code contributions include data that allows for compiling, elaborating, and simulation). Regarding Claim 5, Ma further teaches wherein the one or more user-specified parameters indicate a type and a number of simulation scripts to generate (Ma Col. 13, Lines 33-64, wherein the user specified software components to include indicates a type and also a number of functions or scripts to generate). Regarding Claim 6, Ma further teaches wherein the type and the number of simulation scripts are selected from a 3-step option including separate compile, elaborate, and simulate scripts (Ma Col. 9, Lines 39-53, wherein each type of third party application that is to be compatible with the simulation engine is generated and compiled separately, including compile, elaborate, and simulate functions) and a makefile option including a single script configured to perform compilation, elaboration, and simulation (Ma Col. 2, Lines 32-41, wherein a single dynamically loaded library may be generated). Regarding Claim 7, Ma further teaches wherein the one or more user-specified parameters indicate a scripting language in which to generate the simulation script (Ma Col. 1, Lines 36-41 and Col. 13, Lines 34-44, wherein a user specifies the language of the simulation model, languages including interpretive languages which are scripts or bytecodes). Regarding Claim 8, Ma further teaches wherein the one or more user-specified parameters indicate a script format of basic or advanced (Ma Col. 1, Lines 36-41 and Col. 13, Lines 34-44, wherein a user specifies the language or format of the simulation model). Regarding Claim 9, Ma further teaches wherein the generating the simulation script by executing the template writer is performed in a standalone computing environment that is independent of the host IDE (Ma Col. 7, Lines 22-30 and Col. 14, Lines 1-9, wherein the HLMS is a standalone application or a third party program, indicating that the JIT compiler is a separate computing environment independent of the HLMS). Regarding Claim 10, Ma teaches a system, comprising: one or more processors (Ma Col. 4, Lines 38-44, see processor) configured to execute operations including: generating a simulation database for a circuit design and processed design data for the circuit design (Ma Col. 2, Lines 17-31, Col. 5, Lines 15-31, Col. 6, Lines 18-67 and Col. 7, Lines 1-8, where source code contributions and a simulation model are generated and provided by the HLMS, source code contributions being a simulation database and the simulation model being processed design data), wherein the processed design data includes source files for the circuit design referenced by the simulation database (Ma Col. 5, Lines 15-38, wherein the simulation models are descriptions of the circuit design to be simulated, i.e. source files); exporting the simulation database and the processed design data from a host integrated development environment (IDE) (Ma Col. 5, Lines 5-14, wherein the source code contributions and the simulation model are exported by the HLMS and received by the JIT compiler, the HLMS being a host integrated development environment); providing a template writer configured to generate a simulation script for the circuit design using the simulation database (Ma Col. 5, Lines 5-14, wherein the JIT compiler is a template writer that generates a simulation engine, simulation engines including scripts as taught in Col. 1, Lines 36-41); and generating the simulation script by executing the template writer, wherein the simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported (Ma Col. 1, Lines 5-14, Col. 4, Lines 15-21, and Col. 13, Lines 32-55, wherein the simulation engine is generated by the JIT compiler using the source code contributions and the simulation model, the source code contributions including designer specified parameters, e.g. components, to be included in the simulation engine). Regarding Claim 11, Ma further teaches wherein the template writer calls one or more class library application programming interfaces that operate on the simulation database to generate the simulation script (Ma Col. 4, Lines 15-21 and Col. 6, Lines 37-50, wherein the JIT compiler generates a simulation engine that conforms to APIs). Regarding Claim 12, Ma further teaches wherein the class library application programming interfaces include one or more user-contributed application programming interfaces that extend functionality of the template writer (Ma Col. 13, Lines 32-64, wherein APIs are specified by the designer upon designating software components for inclusion in the simulation engine, extending the functionality to third party software). Regarding Claim 13, Ma further teaches wherein the simulation database includes complete information for compiling, elaborating, and simulating the circuit design (Ma Col. 5, Lines 1-4 and Col. 6, Lines 38-62, wherein the source code contributions include data that allows for compiling, elaborating, and simulation). Regarding Claim 14, Ma further teaches wherein the one or more user-specified parameters indicate a type and number of simulation scripts to generate (Ma Col. 13, Lines 33-64, wherein the user specified software components to include indicates a type and also a number of functions or scripts to generate). Regarding Claim 15, Ma further teaches wherein the type and number of simulation scripts are selected from a 3-step option including separate compile, elaborate, and simulate scripts (Ma Col. 9, Lines 39-53, wherein each type of third party application that is to be compatible with the simulation engine is generated and compiled separately, including compile, elaborate, and simulate functions) and a makefile option including a single script configured to perform compilation, elaboration, and simulation (Ma Col. 2, Lines 32-41, wherein a single dynamically loaded library may be generated). Regarding Claim 16, Ma further teaches wherein the one or more user-specified parameters indicate a scripting language in which to generate the simulation script (Ma Col. 1, Lines 36-41 and Col. 13, Lines 34-44, wherein a user specifies the language of the simulation model, languages including interpretive languages which are scripts or bytecodes). Regarding Claim 17, Ma further teaches wherein the one or more user-specified parameters indicate a script format of basic or advanced (Ma Col. 1, Lines 36-41 and Col. 13, Lines 34-44, wherein a user specifies the language or format of the simulation model). Regarding Claim 18, Ma further teaches wherein the generating the simulation script by executing the template writer is performed in a standalone computing environment that is independent of the host IDE (Ma Col. 7, Lines 22-30 and Col. 14, Lines 1-9, wherein the HLMS is a standalone application or a third party program, indicating that the JIT compiler is a separate computing environment independent of the HLMS). Regarding Claim 19, Ma teaches a computer program product comprising one or more computer readable storage mediums (Ma Col. 15, Lines 46-55, see computer readable medium) having program instructions embodied therewith, wherein the program instructions are executable by one or more processors to cause the one or more processors to execute operations comprising: generating a simulation database for a circuit design and processed design data for the circuit design (Ma Col. 2, Lines 17-31, Col. 5, Lines 15-31, Col. 6, Lines 18-67 and Col. 7, Lines 1-8, where source code contributions and a simulation model are generated and provided by the HLMS, source code contributions being a simulation database and the simulation model being processed design data), wherein the processed design data includes source files for the circuit design referenced by the simulation database (Ma Col. 5, Lines 15-38, wherein the simulation models are descriptions of the circuit design to be simulated, i.e. source files); exporting the simulation database and the processed design data from a host integrated development environment (IDE) (Ma Col. 5, Lines 5-14, wherein the source code contributions and the simulation model are exported by the HLMS and received by the JIT compiler, the HLMS being a host integrated development environment); providing a template writer configured to generate a simulation script for the circuit design using the simulation database (Ma Col. 5, Lines 5-14, wherein the JIT compiler is a template writer that generates a simulation engine, simulation engines including scripts as taught in Col. 1, Lines 36-41); and generating the simulation script by executing the template writer, wherein the simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported (Ma Col. 1, Lines 5-14, Col. 4, Lines 15-21, and Col. 13, Lines 32-55, wherein the simulation engine is generated by the JIT compiler using the source code contributions and the simulation model, the source code contributions including designer specified parameters, e.g. components, to be included in the simulation engine). Regarding Claim 20, Ma further teaches wherein the template writer calls one or more class library application programming interfaces that operate on the simulation database to generate the simulation script (Ma Col. 4, Lines 15-21 and Col. 6, Lines 37-50, wherein the JIT compiler generates a simulation engine that conforms to APIs). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC D LEE whose telephone number is (571)270-7098. The examiner can normally be reached Monday-Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC D LEE/Primary Examiner, Art Unit 2851
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Prosecution Timeline

Oct 25, 2022
Application Filed
Jan 21, 2026
Non-Final Rejection — §102
Mar 24, 2026
Examiner Interview Summary
Mar 24, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+19.3%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 644 resolved cases by this examiner. Grant probability derived from career allow rate.

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