DETAILED ACTION
This office action is in response to the election filed 2/3/2026.
Currently, claims 1-22 are pending.
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 16-22 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities: On p. 24, line 23 “9044” is erroneously referenced for the DRAM wafer (instead of 904). On p. 27, line 25 “1008” is erroneously referenced for the dielectric film (instead of 1006).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 16-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “analogue circuitry for supporting communications”. It is not clear what is meant by “supporting communications”. Presumably, the analogue circuitry does not actively perform the communications, as evidenced by the term “supporting”. But it is not clear what may be considered to be “supporting”. This is a broad term with numerous possibilities. Thus, the meaning of “supporting communications” cannot be clearly understood.
Furthermore, claim 1 recites “wherein one or more of the distributed capacitance units of the second silicon substrate is connected between the supply voltage connector terminal and the ground connector terminal by one or more of the set of connectors”. This limitation uses the word “connected”, but it is not clear to what it is connected by one or more of the connectors. Rather, the claim recites “connected between”. This similarly occurs in claim 16 using the term “coupled between” instead of “connected between”. Again, it is not clear what the capacitance units are coupled to. For purposes of examination, this limitation is understood to mean that one or more of the distributed capacitance units is connects the supply voltage connector terminal to the ground connector terminal, which connection is facilitated by one or more of the connectors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Felix (US 10,820,409).
Pertaining to claim 1, Felix shows, with reference to FIG. 9, a computer structure comprising:
a first silicon substrate (902) in which is formed computer circuitry configured to perform computing operations (col. 1, lines 57-60); and
a second silicon substrate (904) in which is formed a plurality of distributed capacitance units (col. 1, lines 61-62), the second silicon substrate connected to the first silicon substrate by a set of connectors (924) arranged extending depth-wise of the computer structure wherein the second silicon substrate has an outer surface on which are arranged a supply voltage connector terminal and a ground connector terminal for connecting the computer structure to a supply voltage and to ground, respectively (col. 2, lines 29-32; col. 15, lines 48-56), wherein one or more of the distributed capacitance units of the second silicon substrate is connected between the supply voltage connector terminal and the ground connector terminal by one or more of the set of connectors to provide a decoupling capacitor for the circuitry (col. 2, lines 29-32; col. 12, lines 21-23).
Felix fails to anticipate the claim by not showing the first silicon substrate includes analogue circuitry for supporting communications, that the supply voltage is for the analogue circuitry, and that the decoupling is for the analogue circuitry.
However, Felix does teach that the first silicon substrate is part of a processor chip, and that any processor chip may be used (col. 11, lines 26-31). Meanwhile, Lambert teaches in col. 8, lines 7-15 that one such processor comprises analog circuitry. As is the case for any processor, input data is manipulated and sent out as output data. The input/output describes a communication. The manipulation of data by the processor may be interpreted as support for this communication.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try a processor comprising analog circuitry, as taught by Lambert, for the processor of Felix, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Pertaining to claim 2, Felix shows the first silicon substrate has a self-supporting depth and a facing surface and wherein the second silicon substrate has a facing surface located in overlap with the facing surface of the first silicon substrate (col. 11, lines 55-56; FIG. 9).
Pertaining to claim 3, Felix shows the facing surface of the second silicon substrate has planar surface dimensions matching the planar surface dimensions of the facing surface of the first silicon substrate (col. 13, lines 8-14).
Pertaining to claim 10, Felix shows the first silicon substrate and the second silicon substrate are bonded by one or more bonding layers (col. 13, lines 48-56).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Guzy, Sr. et al. (US 11,463,524), Etscheid et al. (US 10,657,210), Longo et al. (US 8,964,818), Abts et al. (US 12,340,300) and Lambert et al. (US 10,496,580) disclose inventions similar to Applicant’s.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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