DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/08/2025 has been entered.
Claim Objections
Claim 9 is objected to because of the following informalities: lines 14-15 recite “..is the same as level of…”. It is recommended to change the limitation to “is the same as a level of…” for grammatical formality. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 11, and 15-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “wherein a lower surface of the second metal pattern contacts the upper surface of the bit line structure…”. It is unclear how a lower surface of the second metal pattern can contact the upper surface of the bit line structure since claim 1 recites “a level of a lowermost surface of the second metal pattern is the same as a level of an upper surface of a capping pattern on the bit line structure” (emphasis added).
Claim 11 recites the limitation “wherein a lower surface of the second metal pattern contacts the upper surface of the bit line structure…”. It is unclear how a lower surface of the second metal pattern can contact the upper surface of the bit line structure since claim 9 recites “a level of a lowermost surface of the second metal pattern is the same as a level of an upper surface of a capping pattern on the bit line structure” (emphasis added).
Claim 15, lines 19-20 recite the limitation “a second metal pattern contacting… upper surfaces of the bit line structure”. It is unclear how a second metal pattern can contact upper surfaces of the bit line structure since lines 24-25 recite “a level of a lowermost surface of the second metal pattern is the same as a level of an upper surface of a capping pattern on the bit line structure” (emphasis added).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, and 8, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in US 2020/0020697 A1 (hereinafter Kim) and Chen et al. in US 2023/0056204 A1 (hereinafter Chen).
Regarding claim 1, Kim teaches in FIG. 6A and related text, a semiconductor device comprising:
a bit line structure (213, [0069]) on a substrate (201, [0066]);
a lower contact plug (218, [0072]) on a portion of the substrate (201) that is adjacent to the bit line structure (213);
an upper contact plug (220/224, [0072]/[0075]) including,
a first metal pattern (220, [0072]) on the lower contact plug (218), and
a second metal pattern (224, [0075]) contacting an upper surface of the first metal pattern (220); and
a capacitor (230, [0064]) on the upper contact plug (220/224), and
wherein the upper surface of the first metal pattern (220) is above an upper surface of the bit line structure (upper surface of 213) with respect to an upper surface of the substrate (201), and
a level of a lowermost surface of the second metal pattern (224) is the same as a level of an upper surface of a capping pattern (214, [0069]) on the bit line structure (213).
Kim does not explicitly state that the second metal pattern contacts an exposed vertical upper sidewall of the first metal pattern; and a level of a lowermost surface of the second metal pattern is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate.
Chen teaches in FIG. 28 and related text, a landing pad (27, [0100]) contacting an exposed vertical upper sidewall of a first conductive pattern (25, [0100]); and a level of a lowermost surface of the landing pad (27) is lower than a level of an upper surface of the first conductive pattern (25) with respect to the upper surface of a substrate (10, see FIG. 1, [0040])
Kim and Chen are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim such that the second metal pattern contacts an exposed vertical upper sidewall of the first metal pattern; and a level of a lowermost surface of the second metal pattern is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate, as taught by Chen, in order to increase the contact area between the first metal pattern and second metal pattern and reduce contact resistance (Chen, [0098]).
Regarding claim 2, Kim as modified by Chen teaches the semiconductor device according to claim 1. Kim further teaches wherein the upper surface of the first metal pattern (220) is flat (planarization step, [0147]).
Regarding claim 6, Kim as modified by Chen teaches the semiconductor device according to claim 1, further comprising: a spacer structure on a sidewall of the bit line structure,
wherein a lower surface of the second metal pattern contacts the upper surface of the bit line structure and an upper surface of the spacer structure.
Regarding claim 8, Kim as modified by Chen teaches the semiconductor device according to claim 1, wherein the bit line structure includes a conductive structure and an insulation structure that are stacked on the substrate.
Claims 3-5, 9-11, and 13-19, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in US 2020/0020697 A1 (hereinafter Kim), Lee et al. in US 2020/0203354 A1 (hereinafter Lee), and Chen et al. in US 2023/0056204 A1 (hereinafter Chen).
Regarding claim 3, Kim as modified by Chen teaches the semiconductor device according to claim 1. Kim does not teach further comprising: a barrier pattern covering a lower surface of and a lower sidewall of the first metal pattern.
Lee teaches in FIG. 1B and related text, a barrier pattern (157, [0035]) covering a lower surface and a lower sidewall of a first metal pattern (LPa, [0069]).
Kim and Lee are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim to include a barrier pattern covering a lower surface and a lower sidewall of the first metal pattern, as taught by Lee, in order to prevent electromigration.
Regarding claim 4, Kim as modified by Chen and Lee teaches the semiconductor device according to claim 3. The combined structure of Kim, Chen and Lee further teaches wherein a lower surface of the second metal pattern contacts an upper surface of the barrier pattern.
Regarding claim 5, Kim as modified by Chen and Lee teaches the semiconductor device according to claim 3. Lee teaches wherein the upper surface of the barrier pattern (surface of 157 contacting layer 170) has a constant height (planarization step, [0069]).
Regarding claim 9, Kim teaches in FIG. 6A and related text, A semiconductor device comprising:
a bit line structure (213, [0069]) on a substrate (201, [0066]);
a lower contact plug (218, [0072]) on a portion of the substrate (201) that is adjacent to the bit line structure (213);
an upper contact plug (220/224, [0072]/[0075]) including,
a first metal pattern (220, [0072]) on the lower contact plug (218),
a second metal pattern (224, [0075]) contacting an upper surface of the first metal pattern (220); and
a capacitor (230, [0064]) on the upper contact plug (220/224),
wherein the upper surface of the first metal pattern (wherein a level of a lowermost surface of the second metal pattern (224) is the same as level of an upper surface of a capping pattern (214, [0069]) on the bit line structure.
Kim does not teach a barrier pattern covering a lower surface and a lower sidewall of the first metal pattern; the second metal pattern contacting an exposed upper vertical sidewall of the first metal pattern and an upper surface of the barrier pattern; wherein the upper surface of the barrier pattern is planar, and wherein a level of a lowermost surface of the second metal pattern is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate.
Lee teaches in FIG. 1B and related text, a barrier pattern (157, [0035]) covering a lower surface and a lower sidewall of a first metal pattern (LPa, [0069]), wherein the upper surface of the barrier pattern (surface of 157 contacting layer 170) is planar (planarization step, [0069]).
Chen teaches in FIG. 28 and related text, a landing pad (27, [0100]) contacting an exposed vertical upper sidewall of a first conductive pattern (25, [0100]); and a level of a lowermost surface of the landing pad (27) is lower than a level of an upper surface of the first conductive pattern (25) with respect to the upper surface of a substrate (10, see FIG. 1, [0040])
Kim, Lee and Chen are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim:
to include a barrier pattern covering a lower surface and a lower sidewall of the first metal pattern, wherein the upper surface of the barrier pattern is planar, as taught by Lee, in order to prevent electromigration, and
such that the second metal pattern contacts an exposed vertical upper sidewall of the first metal pattern; and a level of a lowermost surface of the second metal pattern is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate, as taught by Chen, in order to increase the contact area between the first metal pattern and second metal pattern and reduce contact resistance (Chen, [0098]).
Regarding claim 10, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 9. Kim further teaches wherein the upper surface of the first metal pattern (220) is flat (planarization step, [0147]).
Regarding claim 11, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 9, further comprising:
a spacer structure on a sidewall of the bit line structure,
wherein a lower surface of the second metal pattern contacts an upper surface of the bit line structure and an upper surface of the spacer structure.
Regarding claim 13, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 9. Kim further teaches wherein an upper surface of the first metal pattern (220) is above an upper surface of the bit line structure (upper surface of 213) with respect to an upper surface of the substrate (201).
Regarding claim 14, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 9, wherein the bit line structure includes a conductive structure and an insulation structure that are stacked on the substrate.
Regarding claim 15, Kim teaches in FIGS. 5, 6B and related text, a semiconductor device comprising:
an active pattern (203, FIG. 6B, [0066]) on a substrate (201, FIG. 6B, [0066]);
a gate structure (205/206/207, FIG. 6B, [0067]) buried in an upper portion of the active pattern (203), the gate structure (205/206/207) extending in a first direction (X, FIG. 5) that is parallel to an upper surface of the substrate (201);
a bit line structure (213/214, FIG. 6B, [0069]) on a central upper surface of the active pattern (203) and extending in a second direction (Y, FIG. 5, noting 213 is part of element BL, [0064]) that is parallel to the upper surface of the substrate (201) and perpendicular to the first direction (Y);
a spacer structure (216, FIG. 6B, [0070]) on a sidewall of the bit line (213/214) structure;
a contact plug structure (218/219/220/224, FIG. 6B, [0072]/[0072]/[0075]) on each of opposite end portions of the active pattern (203); and
a capacitor (230, FIG. 6B, [0064]) on the contact plug structure (218/219/220/224),
wherein the contact plug structure (218/219/220/224) includes,
a lower contact plug (218, [0072]),
a metal silicide pattern (219, [0072]) on the lower contact plug (218),
a first metal pattern (220, [0072]); and
a second metal pattern (224, [0075]) contacting an upper surface of the first metal pattern (220) and upper surfaces of the bit line structure (213/214) and the spacer structure (216), and
a level of a lowermost surface of the second metal pattern (224) is the same as a level of an upper surface of a capping pattern (214, [0069]) on the bit line structure.
Kim does not explicitly teach a barrier pattern on the metal silicide pattern; a lower surface and a lower sidewall of the first metal pattern are covered by the barrier pattern; the second metal pattern contacting an upper sidewall of the first metal pattern, and wherein the upper surface of the first metal pattern is above the upper surface of the bit line structure with respect to an upper surface of the substrate, and a level of a lowermost surface of the second metal pattern is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate.
Lee teaches in FIG. 1B and related text, a barrier pattern (157, [0035]) on a metal silicide pattern (155, [0037]), wherein a lower surface and a lower sidewall of a first metal pattern (LPa, [0069]) are covered by the barrier pattern (157).
Chen teaches in FIG. 28 and related text, a landing pad (27, [0100]) contacting an exposed vertical upper sidewall of a first conductive pattern (25, [0100]), wherein an upper surface of the first conductive pattern (25, [0100]) is above the upper surface of a bit line structure (21, [0053]) with respect to an upper surface of the substrate (10, see FIG. 1, [0040]); and a level of a lowermost surface of the landing pad (27) is lower than a level of an upper surface of the first conductive pattern (25) with respect to the upper surface of a substrate (10).
Kim, Lee and Chen are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim:
to include a barrier pattern on the metal silicide pattern, wherein a lower surface and a lower sidewall of the first metal pattern are covered by the barrier pattern, as taught by Lee, in order to prevent electromigration, and
such that the second metal pattern contacts an upper sidewall of the first metal pattern, and wherein the upper surface of the first metal pattern is above the upper surface of the bit line structure with respect to an upper surface of the substrate; and a level of a lowermost surface of the second metal pattern is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate, as taught by Chen, in order to increase the contact area between the first metal pattern and second metal pattern and reduce contact resistance (Chen, [0098]).
Regarding claim 16, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 15. Kim further teaches wherein the active pattern (203) is one of a plurality of active patterns (FIG. 5 shows a plurality) that are spaced apart from each other in the first (X) and second directions (Y), each of the plurality of active patterns (203) extending in a third direction (D3, annotated FIG. 5 below) parallel to the upper surface of the substrate (201) and having an acute angle with the first (X) and second directions (Y), and
the gate structure (205/206/207) is one of a plurality of gate structures (plurality shown in FIG. 5) that are spaced apart from each other in the second direction (Y), and the bit line structure (213/214) is one of a plurality of bit line structures (plurality of BL shown in FIG. 5) that are spaced apart from each other in the first direction (X).
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Annotated FIG. 5 (Kim)
Regarding claim 17, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 16. Kim further teaches wherein the contact plug structure (218/219/220/224) is one of a plurality of contact plug structures (plurality shown in FIG. 5) that are spaced apart from each other in the second direction (Y), the plurality of contact plug structures (218/219/220/224) arranged in a honeycomb pattern in a plan view (FIG. 5).
Regarding claim 18, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 15. Kim further teaches wherein the upper surface of the first metal pattern (220) is flat (planarization step, [0147]).
Regarding claim 19, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 15.
Lee teaches wherein the upper surface of the barrier pattern (surface of 157 contacting layer 170) has a constant height (planarization step, [0069]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in U.S. Patent Application Publication US 2020/0020697 A1 (hereinafter Kim) and Chen et al. in US 2023/0056204 A1 (hereinafter Chen) and in view of Han in U.S. Patent Application Publication US 2015/0035096 A1 (hereinafter Han).
Regarding claim 7, Kim as modified by Chen teaches substantially the entire claimed semiconductor device according to claim 1. Kim as modified by Chen does not explicitly teach wherein the second metal pattern has an upper portion having a first width and a lower portion having a second width greater than the first width.
Han teaches in FIG. 2B a metal pattern 40A1, [0050]), wherein the metal pattern (40A1) has an upper portion (40a, [0050]) having a first width and a lower portion (40b, [0050]) having a second width greater than the first width, in order to minimize the space between contacts in a memory device ([0103]).
Kim, Chen, and Han are analogous art to the claimed invention because they are directed at semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined structure of Kim and Chen in view of Han because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Kim and Han such that the second metal pattern has an upper portion having a first width and a lower portion having a second width greater than the first width, as taught by Han, with the purpose of minimizing the space between contacts in a memory device (Han, [0103]).
Claims 12 and 20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in U.S. Patent Application Publication US 2020/0020697 A1 (hereinafter Kim), Lee et al. in US 2020/0203354 A1 (hereinafter Lee), and Chen et al. in US 2023/0056204 A1 (hereinafter Chen), and in view of Han in U.S. Patent Application Publication US 2015/0035096 A1 (hereinafter Han).
Regarding claim 12, Kim as modified by Lee and Chen substantially teaches the entire claimed semiconductor device according to claim 9. Kim as modified by Lee and Chen does not explicitly teach wherein the second metal pattern has an upper portion having a first width and a lower portion having a second width greater than the first width.
Han teaches in FIG. 2B a metal pattern 40A1, [0050]), wherein the metal pattern (40A1) has an upper portion (40a, [0050]) having a first width and a lower portion (40b, [0050]) having a second width greater than the first width, in order to minimize the space between contacts in a memory device ([0103]).
Kim and Han are analogous art because they both are directed at semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Han because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the second metal pattern as taught by Kim such that the second metal pattern has an upper portion having a first width and a lower portion having a second width greater than the first width, as taught by Han, with the purpose of minimizing the space between contacts in a memory device (Han, [0103]).
Regarding claim 20, Kim as modified by Lee and Chen teaches the semiconductor device according to claim 15. Kim as modified by Lee and Chen does not explicitly teach wherein the second metal pattern has an upper portion having a first width and a lower portion having a second width greater than the first width.
Han teaches in FIG. 2B a metal pattern 40A1, [0050]), wherein the metal pattern (40A1) has an upper portion (40a, [0050]) having a first width and a lower portion (40b, [0050]) having a second width greater than the first width, in order to minimize the space between contacts in a memory device ([0103]).
Kim and Han are analogous art because they both are directed at semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim in view of Han because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the second metal pattern as taught by Kim such that the second metal pattern has an upper portion having a first width and a lower portion having a second width greater than the first width, as taught by Han, with the purpose of minimizing the space between contacts in a memory device (Han, [0103]).
Response to Arguments
Applicant’s remarks on page 8 regarding the status the claims and the drawings are acknowledged.
Applicant’s remarks on page 8 regarding the telephonic interview conducted on July 16, 2025 are acknowledged.
Applicant’s remarks on page 8 regarding Objections to the Claims made in the Final Office Action mailed on 06/11/2025 (hereinafter previous Office Action) are acknowledged.
In response, the Examiner finds the amendments to the claims in the Instant Application overcome the Objections. However, the Examiner notes an additional Claim Objection for minor informalities in the Instant Office Action.
Applicant’s arguments on pages 9-11 regarding the rejections under 35 USC 103 of independent claims 1, 9 and 15 made in the previous Office Action as unpatentable over Kim are acknowledged. Specifically, Applicant argues on page 10: “a level of the lowermost surface of the conductive pad 224 is the same as a level of the upper surface of the upper plug 220 with respect to the substrate 201…. Thus, Kim has not been shown to disclose or suggest at least the features of ‘a level of a lowermost surface of the second metal pattern is the same as a level of an upper surface of a capping pattern on the bit line structure and is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate’”.
In response, the Examiner notes that the Instant Office Action does not assert that Kim teaches the limitation of “a level of a lowermost surface of the second metal pattern… is lower than a level of the upper surface of the first metal pattern with respect to the upper surface of the substrate”. Instead, Chen (US 2023/0056204) is cited as teaching this limitation.
Conclusion
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/S.L.J./ Examiner, Art Unit 2811
/ORI NADAV/ Primary Examiner, Art Unit 2811
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