DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1, and 12, filed on 8/23/2026 have been fully considered for examination based on their merits. The withdrawn and amended claim(s) 18 filed on 06/17/2026 and non-elected claim (s) 19-20 have not been considered for examination in this Office Action. The previously presented claim(s) 3-11, and 14-16 have been considered. New Claim(s) 21-23 have been considered and entered. Claim(s) 2, 13 and 18 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-10, filed 06/17/2026, with respect to the rejection(s) of claim(s) 1-16 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of IHARA.
Regarding Independent Claim(s) 1, and 12. Applicant argues (see Remarks, page 8) that SHAN prior art does not disclose or suggest the amended claim features, now recites, “an electronic assembly or a computing device comprising: a binding material is adhered…corner of the semiconductor package…encapsulates…passive component array.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of IHARA teaches a semiconductor device having a conducting pattern adhered to the wiring bond at a corner of the semiconductor element and at least partially encapsulates the capacitative elements.
Regarding Claims 3-11, 14-16, and 21-23: The dependent claims 3-11, 14-16, and 21-23 follow similar arguments as Claim(s) 1, and 12, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-6, 10-12, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bok Eng Cheah et al, (hereinafter CHEAH), US 20210183776 A1, in view of Eng Huat Goh et al, (hereinafter GOH), US 20190013303 A1, and Takumi Ihara, (hereinafter IHARA), US 20110133321 A1.
Regarding Claim 1, CHEAH teaches an electronic assembly (Fig. 4, 400, circuit package) comprising:
a semiconductor package (Fig. 4, 442, IC package substrate) comprising a first surface (Fig. 4, 443, die side), an opposing second surface (Fig. 4, 441, land side), and a side wall (annotated Figure 4);
a printed circuit board (Fig. 4, 456, board) coupled to the second surface (Fig. 4, 441, land side) of the semiconductor package (Fig. 4, 442, IC package substrate); and
at least one passive component array (annotated Figure 4) comprising one or more passive components (Fig. 4, 412/476, passive device) at least partially embedded in a mold layer (Fig. 4, 420, molding layer), each passive component (Fig. 4, 412/476, passive device) further comprising a first terminal (annotated Figure 4) and a second terminal (annotated Figure 4).
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CHEAH does not explicitly disclose, an electronic assembly comprising: wherein the first terminal of the passive component is coupled to the printed circuit board, and the passive component array is attached to the side wall of the semiconductor package.
GOH teaches an electronic assembly (Fig. 1, 100, IC package assembly) comprising:
wherein the first terminal (Fig. 7, 426, second terminal) of the passive component (Fig. 7, 422, capacitor) is coupled to the printed circuit board (Fig. 7, 450, PCB), and
the passive component array (Fig. 7, 422, capacitor) is attached to the side wall (Fig. 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHEAH to incorporate the teachings of GOH, such that an electronic assembly comprising: wherein the first terminal of the passive component is coupled to the printed circuit board, and the passive component array is attached to the side wall of the semiconductor package. The above arrangement of the capacitor (422) may include a first terminal (424) electrically coupled with the conductive routing region (418) and connected to second terminal (426), therefore enabling the decoupling with PCB edge capacitors for the improvement of the device signal integrity (GOH, [0037], [0002]).
CHEAH as modified by GOH does not explicitly disclose an electronic assembly comprising: a binding material is adhered to the printed circuit board at a corner of the semiconductor package and at least partially encapsulates the passive component array.
IHARA teaches an electronic assembly (Figs. 1A/1B, 10, semiconductor device) comprising: a binding material (Fig. 3B, 26, conductive patterns) is adhered to the printed circuit board (Fig. 3B, 21, wiring board) at a corner (Fig. 3B, dotted lines of the mounting area, 21M) of the semiconductor package (Fig. 3B, 22, semiconductor element) and at least partially encapsulates the passive component array (Fig. 3B, 24, capacitative elements).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH to incorporate the teachings of IHARA, such that an electronic assembly comprising: a binding material is adhered to the printed circuit board at a corner of the semiconductor package and at least partially encapsulates the passive component array, so that the heat generated by the semiconductor element may be effectively dissipated and transferred via the conductive pattern on the principal surface of the wiring board by flip-chip mounting and manufacturing (IHARA, [0003-0005]).
Regarding Claim 3, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
GOH further teaches the electronic assembly (Fig. 1, 100, IC package assembly), wherein the semiconductor package (Fig. 7, 404, package substrate) further comprises a stiffener (Fig. 7, 402) coupled to the first surface (Fig. 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate), the stiffener (Fig. 7, 402) having a side surface (annotated Figure 7) that is proximal to the side wall (annotated Figure 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate), and wherein the second terminal (Fig. 7, 424, first terminal) of the passive component (Fig. 7, 422, capacitor) is coupled to the side surface (annotated Figure 7) of the stiffener (Fig. 7, 402).
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Regarding Claim 4, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
GOH further teaches the electronic assembly (Fig. 1, 100, IC package assembly) comprises 4 passive component arrays (annotated Figure 1).
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Regarding Claim 5, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
GOH further teaches the electronic assembly (Fig. 1, 100, IC package assembly), wherein each passive component array (annotated Figure 1) comprises 3 passive components (annotated Figure 1).
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Regarding Claim 6, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
GOH further teaches the electronic assembly (Fig. 1, 100, IC package assembly), wherein the one or more passive components (annotated Figure 1) comprise one or more capacitors (Fig. 1, 114/120/126, first/second/third capacitor).
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Regarding Claim 10, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
GOH further teaches the electronic assembly (Fig. 1, 100, IC package assembly), further comprising one or more electronic components (Fig. 7, 414, IC die) coupled to the first surface (Fig. 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate), wherein the first terminal (Fig. 7, 426, second terminal) of the passive component (Fig. 7, 422, capacitor) is coupled to the one or more electronic components (Fig. 7, 462/460, interconnect structures (e.g. solder balls)) through the second surface (Fig. 7, 408, second side) of the semiconductor package (Fig. 7, 404, package substrate).
Regarding Claim 11, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 10.
GOH further teaches the electronic assembly (Fig. 1, 100, IC package assembly), wherein the one or more electronic components (Fig. 11, 800, computing device) comprise a central processing unit (Fig. 11, 804, processor, CPU, [0050], [0057], [0059], [0062]), a system-on-chip (Fig. 11, chipset, [0094]), a graphic processing unit (Fig. 11, 804, processor, Graphics CPU, [0050], [0057], [0059], [0062]), a deep learning processor (Fig. 11, 804, processor, CPU, [0050], [0057], [0059], [0062]), or a neural network processor (Fig. 11, 804, processor, CPU, [0050], [0057], [0059], [0060], [0062]).
CHEAH further teaches the electronic assembly (Fig. 4, 400, circuit package), wherein the one or more electronic components (Fig. 6, 600, computing system) comprise a central processing unit (Fig. 6, 605/610, processor, [0092-0101]), a system-on-chip (Fig. 6, 620, chipset, [0094]), a graphic processing unit (Fig. 6, 605/610, processor, [0074], [0092-0101]), a deep learning processor (Fig. 6, 605/610, processor, [0092-0101]), or a neural network processor (Fig. 6, 666, network interface/processor, [0092-0101]).
Regarding Claim 12, CHEAH teaches a computing device (Fig. 6, 600, computing system) comprising:
a printed circuit board (Fig. 4, 456, board); and
an electronic assembly (Fig. 4, 400, circuit package) coupled to the printed circuit board (Fig. 4, 456, board), the electronic assembly (Fig. 4, 400, circuit package) comprising:
a semiconductor package (Fig. 4, 442, IC package substrate) comprising a first surface (Fig. 4, 443, die side), an opposing second surface (Fig. 4, 441, land side), and a side wall (annotated Figure 4), wherein the second surface (Fig. 4, 441, land side) of the semiconductor package (Fig. 4, 442, IC package substrate) is coupled to the printed circuit board (Fig. 4, 456, board); and
at least one passive component array (annotated Figure 4) comprising one or more passive components (Fig. 4, 412/476, passive device) at least partially embedded in a mold layer (Fig. 4, 420, molding layer), each passive component (Fig. 4, 412/476, passive device) further comprising a first terminal (annotated Figure 4) and a second terminal (annotated Figure 4).
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CHEAH does not explicitly disclose a computing device comprising: wherein the first terminal of the passive component is coupled to the printed circuit board and the passive component array is attached to the side wall of the semiconductor package.
GOH teaches a computing device (Fig. 11, 800) comprising: wherein the first terminal (Fig. 7, 426, second terminal) of the passive component (Fig. 7, 422, capacitor) is coupled to the printed circuit board (Fig. 7, 450, PCB), and
the passive component array (Fig. 7, 422, capacitor) is attached to the side wall (Fig. 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHEAH to incorporate the teachings of GOH, such that a computing device comprising: wherein the first terminal of the passive component is coupled to the printed circuit board, and the passive component array is attached to the side wall of the semiconductor package. The above arrangement of the capacitor (422) may include a first terminal (424) electrically coupled with the conductive routing region (418) and connected to second terminal (426), therefore enabling the decoupling with PCB edge capacitors for the improvement of the device signal integrity (GOH, [0037], [0002]).
CHEAH as modified by GOH does not explicitly disclose a computing device comprising: a binding material is adhered to the printed circuit board at a corner of the semiconductor package and at least partially encapsulates the passive component array.
IHARA teaches a computing device (Figs. 1A/1B, 10, semiconductor device) comprising: a binding material (Fig. 3B, 26, conductive patterns) is adhered to the printed circuit board (Fig. 3B, 21, wiring board) at a corner (Fig. 3B, dotted lines of the mounting area, 21M) of the semiconductor package (Fig. 3B, 22, semiconductor element) and at least partially encapsulates the passive component array (Fig. 3B, 24, capacitative elements).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH to incorporate the teachings of IHARA, such that a computing device comprising: a binding material is adhered to the printed circuit board at a corner of the semiconductor package and at least partially encapsulates the passive component array, so that the heat generated by the semiconductor element may be effectively dissipated and transferred via the conductive pattern on the principal surface of the wiring board by flip-chip mounting and manufacturing (IHARA, [0003-0005]).
Regarding Claim 14, CHEAH as modified by GOH and IHARA teaches the computing device of claim 12.
GOH further teaches the computing device (Fig. 11, 800), wherein the semiconductor package (Fig. 7, 404, package substrate) further comprises a stiffener (Fig. 7, 402) coupled to the first surface (Fig. 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate), the stiffener (Fig. 7, 402) having a side surface (annotated Figure 7) that is proximal to the side wall (annotated Figure 7, 406, first side) of the semiconductor package (Fig. 7, 404, package substrate), and wherein the second terminal (Fig. 7, 424, first terminal) of the passive component (Fig. 7, 422, capacitor) is coupled to the side surface (annotated Figure 7) of the stiffener (Fig. 7, 402).
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Regarding Claim 15, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 12.
GOH further teaches the computing device (Fig. 11, 800), wherein the one or more passive components (annotated Figure 1) comprise one or more capacitors (Fig. 1, 114/120/126, first/second/third capacitor).
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Claim(s) 7-8, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEAH, in view of GOH and IHARA as applied to Claim(s) 1, 3-6, 10-12, 14-15 above, and further in view of Anne Leahy et al, (hereinafter LEAHY), US 20030110452 A1.
Regarding Claim 7, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
CHEAH as modified by GOH and IHARA does not explicitly disclose the electronic assembly, further comprising a voltage regulator coupled to the printed circuit board, wherein the voltage regulator is further coupled to the first terminal of the passive component and to the second surface of the semiconductor package.
LEAHY teaches the electronic assembly (Fig. 5, 100, package assembly), further comprising a voltage regulator (Fig. 5, 51, voltage regulator module or VRM) coupled to the printed circuit board (Fig. 5, 120, PCB), wherein the voltage regulator (Fig. 5, 51, voltage regulator module or VRM) is further coupled to the first terminal (annotated Figure 5) of the passive component (Fig. 5, 128, bulk capacitor) and to the second surface (annotated Figure 5, [0022]) of the semiconductor package (Figure 5, 150, substrate).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH and IHARA to incorporate the teachings of LEAHY, such that the electronic assembly, further comprising a voltage regulator coupled to the printed circuit board, wherein the voltage regulator is further coupled to the first terminal of the passive component and to the second surface of the semiconductor package, so that a voltage regulator module (VRM) supplies the power to the package assembly through conductive pathways comprising vias, PTHs, and planes formed in the substrate and the PCB (LEAHY, [0021]).
Regarding Claim 8, CHEAH as modified by GOH, IHARA and LEAHY teaches the electronic assembly of claim 7.
LEAHY further teaches the electronic assembly (Fig. 5, 100, package assembly), wherein the voltage regulator (Fig. 5, 51, voltage regulator module or VRM) is further coupled to the first terminal (annotated Figure 5) of the passive component (Fig. 5, 128, bulk capacitor) via a board routing (annotated Figure 5) in the printed circuit board (Fig. 5, 120, PCB).
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Regarding Claim 16, CHEAH as modified by GOH and IHARA teaches the computing device of claim 12.
CHEAH as modified by GOH and IHARA does not explicitly disclose the computing device, further comprising a voltage regulator coupled to the printed circuit board, wherein the voltage regulator is further coupled to the first terminal of the passive component and to the second surface of the semiconductor package.
LEAHY teaches the computing device (Fig. 1, electronic package assembly, [0007]), further comprising a voltage regulator (Fig. 5, 51, voltage regulator module or VRM) coupled to the printed circuit board (Fig. 5, 120, PCB), wherein the voltage regulator (Fig. 5, 51, voltage regulator module or VRM) is further coupled to the first terminal (annotated Figure 5) of the passive component (Fig. 5, 128, bulk capacitor) and to the second surface (annotated Figure 5, [0022]) of the semiconductor package (Figure 5, 150, substrate).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH and IHARA to incorporate the teachings of LEAHY, such that the computing device, further comprising a voltage regulator coupled to the printed circuit board, wherein the voltage regulator is further coupled to the first terminal of the passive component and to the second surface of the semiconductor package, so that a voltage regulator module (VRM) supplies the power to the package assembly through conductive pathways comprising vias, PTHs, and planes formed in the substrate and the PCB (LEAHY, [0021]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEAH, in view of GOH, and IHARA as applied to Claim(s) 1, 3-6, 10-12, 14-15 above, and further in view of Bok Eng Cheah et al, (hereinafter CHEAH2), US 20200083170 A1.
Regarding Claim 9, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
CHEAH as modified by GOH and IHARA does not explicitly disclose the electronic assembly, wherein the first terminal of the passive component is associated to a power supply reference voltage (Vcc), and the second terminal of the passive component is associated to a ground reference voltage (Vss).
CHEAH2 teaches the electronic assembly (Fig. 1, 100, semiconductor device), wherein the first terminal (annotated Figure 1) of the passive component (Fig. 1, 140) is associated to a power supply reference voltage (Vcc) (Fig. 1, 122), and the second terminal (annotated Figure 1) of the passive component (Fig. 1, 140) is associated to a ground reference voltage (Vss) (Fig. 1, 124).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH and IHARA to incorporate the teachings of CHEAH2, such that the electronic assembly, wherein the first terminal of the passive component is associated to a power supply reference voltage (Vcc), and the second terminal of the passive component is associated to a ground reference voltage (Vss), so that the above arrangement mitigate the increase of inductance loop, and any unwanted noise due to signal jittering and further increase the device performance (CHEAH2, [0003]).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEAH, in view of GOH, and IHARA as applied to Claim(s) 1, 3-6, 10-12, 14-15 above, and further in view of Chia-Cheng Chang et al, (hereinafter CHANG), US 20200105684 A1.
Regarding Claim 21, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 1.
CHEAH as modified by GOH and IHARA does not explicitly disclose the electronic assembly, wherein the mold layer is mounted on the printed circuit board and extends along the side wall of the semiconductor package.
CHANG teaches the electronic assembly (Fig. 6, 500b, semiconductor package structure), wherein the mold layer (Fig. 6, 117, molding material) is mounted on the printed circuit board (Fig. 6, 101, substrate) and extends along the side wall of the semiconductor package (Fig. 6, 115a/115b, first/second semiconductor die).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH and IHARA to incorporate the teachings of CHANG, such that the electronic assembly, wherein the mold layer is mounted on the printed circuit board and extends along the side wall of the semiconductor package, so that the stresses due to different coefficients of thermal expansion of the various substrate and semiconductor die materials can be mitigate and thus the electrical characteristics and reliability of the semiconductor package may be enhanced (CHANG, [0003-0004]).
Claim(s) 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEAH, in view of GOH, and IHARA as applied to Claim(s) 1, 3-6, 10-12, 14-15 above, and further in view of Omkar G. Karhade et al, (hereinafter KARHADE), US 20180182718 A1.
Regarding Claim 22, CHEAH as modified by GOH and IHARA teaches the electronic assembly of claim 3.
CHEAH as modified by GOH and IHARA does not disclose the electronic assembly, wherein a connection between the first terminal of the passive component and the printed circuit board is approximately perpendicular to a connection between the second terminal of the passive component and the stiffener.
KARHADE teaches the electronic assembly (Fig. 1c, 100, package structure), wherein a connection between the first terminal (Fig. 1c, 110, contact regions) of the passive component (Fig. 1c, 108, component) and the printed circuit board (Fig. 1c, 102, substrate) is approximately perpendicular (annotated Figure 1c) to a connection between the second terminal (Fig. 1c, 110, contact regions) of the passive component (Fig. 1c, 108, component) and the stiffener (Fig. 1c, 104/104′).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH and IHARA to incorporate the teachings of KARHADE, such that the electronic assembly, wherein a connection between the first terminal of the passive component and the printed circuit board is approximately perpendicular to a connection between the second terminal of the passive component and the stiffener, so that the stiffeners, such as metal stiffeners, can be employed in semiconductor package which may reduce warpage during temperature processing (KARHADE, [0001]).
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Regarding Claim 23, CHEAH as modified by GOH and IHARA teaches the computing device of claim 14.
CHEAH as modified by GOH and IHARA does not disclose the computing device, wherein a connection between the first terminal of the passive component and the printed circuit board is approximately perpendicular to a connection between the second terminal of the passive component and the stiffener.
KARHADE teaches the computing device (Fig. 1c, 100, package structure), wherein a connection between the first terminal (Fig. 1c, 110, contact regions) of the passive component (Fig. 1c, 108, component) and the printed circuit board (Fig. 1c, 102, substrate) is approximately perpendicular (annotated Figure 1c) to a connection between the second terminal (Fig. 1c, 110, contact regions) of the passive component (Fig. 1c, 108, component) and the stiffener (Fig. 1c, 104/104′).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have CHEAH as modified by GOH and IHARA to incorporate the teachings of KARHADE, such that the computing device, wherein a connection between the first terminal of the passive component and the printed circuit board is approximately perpendicular to a connection between the second terminal of the passive component and the stiffener, so that the stiffeners, such as metal stiffeners, can be employed in semiconductor package which may reduce warpage during temperature processing (KARHADE, [0001]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20080054490 A1 - Figure 5
STATEMENT OF RELEVANCE – The encapsulation retention structure adhere to the substrate, corner to the integrated chip and encapsulated the electronic component in an integrated circuit package.
US 20180342467 A1 - Figure 5
STATEMENT OF RELEVANCE – The first terminal of the components connected with the package substrate, and the second termination of the components connected to the conductive element.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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