DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the one or more of the plurality of passive devices are coupled to the ground plane in claim 14 (Examiner notes that Figs 2 and 6j appear to show the semiconductor package and voltage regulator coupled to the ground plane but the passive devices do not appear to be similarly coupled) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 13 is objected to because of the following informalities:
Line 2 of claim 13 has the word “interposing.” Examiner believes this to be a typo and should read “interposer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites the limitation “the conductive layer” in lines 6 and 7. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will treat this to mean “the low-resistance conductive layer.”
Claims 2-11 would also be rejected as they are dependent on claim 1.
Regarding claim 12, the claim recites the limitation “the semiconductor platform” in line 1. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will treat this to mean “the semiconductor platform.”
Further, the claim recites the limitation “metal layer” in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will treat this to mean “low-resistance metal layer.”
Additionally, the claim is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are:
[0036] discloses forming openings in the non-conductive layers. Line 8 of the claim fills the vertical openings and the limitation of lines 8-9 read as though by filling the vertical openings the vertical interconnects come into existence. The non-conductive layer was not removed to expose the underlying low-resistance metal layer to form the vertical interconnects. For purposes of Examination, Examiner will interpret the limitation as having the missing step of forming openings in the non-conductive layers to produce the plurality of vertical interconnects.
Claims 13-14 are also rejected as they are dependent on claim 12.
Regarding claim 15, the claim recites the limitation “the metal layer” in lines 6 and 7. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will treat this to mean “the low-resistance metal layer.”
Claims 16-20 are also rejected as they are dependent on claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah et. al. (US 20200168559 A1), hereinafter Cheah.
Regarding claim 1, Cheah teaches a semiconductor platform (Fig 2 semiconductor device package 200, [0036]) comprising: a printed circuit board (Fig 2 wiring board 274, [0047]); an interposer (Fig 2 package substrate 201, [0036]) coupled to (Fig 2) the print circuit board (Fig 2 wiring board 274, [0047]), the interposer (Fig 2 package substrate 201, [0036]) comprising: a low-resistance conductive layer (Fig 2 conductive core 210, [0040]) with a top surface (Fig 2 core 210 top surface) and a bottom surface (Fig 2 core 210 bottom surface), the low-resistance conductive layer (Fig 2 conductive core 210, [0040]) providing a power corridor (See below) for the semiconductor platform (Fig 2 semiconductor device package 200, [0036]); a first non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the top surface (Fig 2 core 210 top surface) of the conductive layer (Fig 2 conductive core 210, [0040]) and a second non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the bottom surface (Fig 2 core 210 bottom surface) of the conductive layer (Fig 2 conductive core 210, [0040]); and a plurality of vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]), wherein the vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]) provide electrical connections (the vias provide an electrical path) through the interposer (Fig 2 package substrate 201, [0036]); and a semiconductor package (Fig 2 device 270, [0045]) coupled to (Fig 2) the interposer (Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 2 package substrate 201, [0036]) provides the power corridor for the semiconductor package (Fig 2 device 270, [0045]).
Cheah fails to teach a power corridor.
However, Cheah teaches a structure substantially identical to that of the claim. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the structure of Cheah would also be able to function as a power corridor. In support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 10, Cheah teaches a ball grid array (Fig 2 bump array 272, [0047]) with a plurality of solder balls (Fig 2 bump array 272, [0047]) for power connections, wherein the plurality of solder balls (Fig 2 bump array 272, [0047]) for power connections are coupled to the interposer (Fig 2 package substrate 201, [0036]).
Cheah fails to teach power connections.
However, Cheah teaches a structure substantially identical to that of the claim. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the structure of Cheah would also have power connections. In support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 11, Cheah teaches the low-resistance conductive layer (Fig 2 conductive core 210, [0040]) has a thickness in the range of approximately 50 to 200 µm (50 to 500 µm, [0031]). Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Cheah discloses the claimed range with sufficient specificity. MPEP 2131.03(II) ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Jain et. al. (US 20190304915 A1), hereinafter Jain.
Regarding claim 2, Cheah fails to teach a voltage regulator or power management integrated circuit device coupled to the interposer, wherein the interposer provides the power corridor for the voltage regulator or power management integrated circuit.
However, Jain teaches a voltage regulator (Fig 1 die 114, [0036]; the die may be a voltage regulator) or (optional so not considered) power management integrated circuit device coupled to (Fig 1) the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]) provides the power corridor for the voltage regulator (Fig 1 die 114, [0036]; the die may be a voltage regulator) or (optional so not considered) power management integrated circuit.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Jain by having a voltage regulator coupled to the interposer. This would allow for a power delivery network on the interposer ([0059]).
Regarding claim 3, Cheah fails to teach a first passive device coupled to the interposer, wherein the interposer provides the power corridor for the first passive device.
However, Jain teaches a first passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) coupled to the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]) provides the power corridor for the first passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Jain by having a first passive device. This would allow for a portion of a filter on the interposer ([0059]).
Regarding claim 4, Cheah as modified in claim 3 teaches the first passive device (Jain: Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) is an inductor (Jain: Fig 9 inductor 933, [0059]; not shown on surface).
Regarding claim 5, Cheah fails to teach a second passive device coupled to the interposer, wherein the interposer provides the power corridor for the second passive device.
However, Jain teaches a second passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) coupled to the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]) provides the power corridor for the second passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Jain by having a second passive device. This would allow for a portion of a filter on the interposer ([0059]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Jain et. al. (US 20190304915 A1), hereinafter Jain, in further view of Hovis et. al. (US 20200373285 A1), hereinafter Hovis.
Cheah as modified in claim 5 teaches the second passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) is an inductor (Jain: Fig 9 inductor 933, [0059]; not shown).
Cheah as modified in claim 5 fails to teach the inductor is attached to the printed circuit board and the interposer further comprises an opening for accommodating the inductor.
However, Hovis teaches the inductor (Fig 5 not labeled inductor, [0058] corresponds to Jain: Fig 9 inductor 933, [0059]; not shown) is attached to (Fig 1 connected with solder balls 375) the printed circuit board (Fig 5 circuit board 411, [0056] corresponds to Cheah: Fig 2 wiring board 274, [0047]) and the interposer (Fig 5 interposer circuit board 151, [0057] corresponds to Cheah: Fig 2 package substrate 201, [0036]) further comprises an opening (Fig 5 aperture 152, [0058]) for accommodating the inductor (Fig 5 not labeled inductor, [0058] corresponds to Jain: Fig 9 inductor 933, [0059]; not shown).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Jain to incorporate the teachings of Hovis by having an opening for accommodating the inductor. This would allow for uneven passive device heights to be compensated for when placing a die on top of the interposer ([0057]).
Claim 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing.
Regarding claim 7, Cheah teaches the plurality of vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]) comprises a first vertical interconnect (Fig 2 via 226, [0038]) through the interposer (Fig 2 package substrate 201, [0036]) coupling the semiconductor package (Fig 2 device 270, [0045]).
Cheah fails to teach a ground plane positioned in an upper layer of the printed circuit board.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 8, Cheah teaches the plurality of vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]) comprises a second vertical interconnect (Fig 2 via 222, [0038]) through the interposer (Fig 2 package substrate 201, [0036]) coupling the semiconductor package (Fig 2 device 268, [0045]).
Cheah fails to teach a signal line in the printed circuit board.
However, Kamgaing teaches a signal line (Fig 1 electrical trace 177, [0026]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having signal lines in the printed circuit board. This would allow for the transmission of signals from different components on the printed circuit board.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Jain et. al. (US 20190304915 A1), hereinafter Jain, in further view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing.
Cheah as modified in claim 2 teaches the plurality of vertical interconnects (Cheah: Fig 2 vias 220, 222, 224, 226, [0038]) comprises a third vertical interconnect (Cheah: Fig 2 via 220, [0038]) through the interposer (Cheah: Fig 2 package substrate 201, [0036]) coupling the voltage regulator (Jain: Fig 1 die 114, [0036]; the die may be a voltage regulator) or (optional so not considered) power management integrated circuit device.
Cheah as modified in claim 2 fails to teach a ground plane positioned in an upper layer of the printed circuit board.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang. Cheah teaches a method (Figs 1A-1K, [0036]) comprising: providing (Fig 1A) a low-resistance metal layer (Fig 1A reference layer 110, [0022]) with a top surface (Fig 1A top of reference layer 110) and a bottom surface (Fig 1A bottom of reference layer 110), the low-resistance metal layer (Fig 1A reference layer 110, [0022]) providing a power corridor (Similar to claim 1; the structure of Cheah is similar and this can perform a similar function) for the semiconductor platform (Fig 2 semiconductor device package 200, [0036]); forming (Fig 1A pattern, [0022]) a plurality of vertical openings (Fig 1A through-holes 112, [0022]) through the metal layer (Fig 1A reference layer 110, [0022]); forming (Fig 1B spinning on, [0024]) a first non-conductive layer (Fig 1B dielectric layer 114, [0024]) positioned (spinning on, [0024]) on the top surface (Fig 1B top of reference layer 110) of the low-resistance metal layer (Fig 1B reference layer 110, [0022]) and a second non-conductive layer (Fig 1B dielectric layer 114, [0024]) positioned on (spinning on, [0024]) the bottom surface (Fig 1B bottom of reference layer 110) of the low-resistance metal layer (Fig 1B reference layer 110, [0022]); filling (Fig 1B filling, [0024]) the plurality of vertical openings (Fig 1B through-holes 112, [0024]) to form non-conductive vertical separators (Fig 1B not labeled).
Cheah fails to each a plurality of vertical interconnects in the low-resistance metal layer, wherein the first non-conductive layer, the low-resistance metal layer, the second non-conductive layer, and the plurality of vertical interconnects form an interposer with the power corridor; and forming a first pattern of openings for solder connections in the first non-conductive layer and a second pattern of openings for solder connections in the second non-conductive layer.
However, Wang teaches forming vias (Fig 7B via V1, [0098]) in a top layer of a non-conductive material (Fig 7B adhesive material 220’, [0098]). Wang further teaches forming vias (Fig 10B via V3, [0115]) in a bottom layer of a non-conductive material (Fig 10B solder mask 260, [0115]). This forms vertical interconnects (Fig 1 conductive structure 214, [0045]) in the low-resistance material (Fig 1 interposer substrate 205, [0048]). Additionally, Cheah teaches reference vias (Fig 3 reference via 320 or 346, [0049] and [0050], respectively) that makes direct contact with the reference layer (Fig 3 reference layer 310 or 332, [0049] and [0050], respectively). One having ordinary skill in the art before the effective filing date of the claimed invention would be able to use the teachings of Wang to form the plurality of vertical interconnects in the low-resistance metal layer of Cheah with a reasonable expectation of success. MPEP 2143(I)(G)
In doing so Cheah would have a plurality of vertical interconnects (From Wang) in the low-resistance metal layer (Cheah: Fig 1B reference layer 110, [0022]), wherein the first non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]), the low-resistance metal layer (Cheah: Fig 1A reference layer 110, [0022]), the second non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]), and the plurality of vertical interconnects (From Wang) form an interposer (Cheah: Fig 2 package substrate 201, [0036]) with the power corridor (Similar to claim 1; the structure of Cheah is similar and this can perform a similar function); and forming a first pattern of openings (Wang: Fig 7B via V1, [0098]) for solder connections (Cheah: Fig 2 bump array with bump 264, [0044]) in the first non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]) and a second pattern of openings (Wang: Fig 10B via V3, [0115]) for solder connections (Cheah: Fig 2 bump array with bump 272, [0047]) in the second non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Lee et. al. (US 20200161231 A1).
Cheah as modified in claim 12 fails to teach a device opening in the interposer by forming a space in the interposing and depositing a sacrificial material in the space; and removing the sacrificial material to form the device opening.
However, Wang teaches a device opening (Fig 10C cavity 230, [0114]) in the interposer (Fig 10C interposer 200, [0114]) by forming a space (Fig 10C cavity 230, [0114]) in the interposing (Fig 10C interposer 200, [0114]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Wang by having a device opening. This would allow for effective utilization of space ([0047]).
Cheah as modified above fails to teach depositing a sacrificial material in the space; and removing the sacrificial material to form the device opening.
However, Lee teaches depositing a sacrificial material (Fig 12 dummy member 125, [0061]) in the space (not labeled; area where electronic components are not disposed, [0061] corresponds to Wang: Fig 10C cavity 230, [0114]); and removing (Fig 12 penetration hole 150H, [0061]) the sacrificial material (Fig 12 dummy member 125, [0061]) to form the device opening (Fig 12 penetration hole 150H, [0061] corresponds to Wang: Fig 10C cavity 230, [0114]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Wang to incorporate the teachings of Lee by having a sacrificial material in a space. This would prevent possible contamination at the edges of the device opening due to undulations ([0060]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing, in further view of Jain et. al. (US 20190304915 A1), hereinafter Jain.
Cheah as modified in claim 12 teaches positioning (Cheah: Fig 2 mounting with bump array 272, [0047]) and coupling (Cheah: Fig 2 mounting with bump array 272, [0047]) the interposer (Cheah: Fig 2 package substrate 201, [0036]) onto a printed circuit board (Cheah: Fig 2 board 274, [0047]); and positioning (Cheah: Fig 2 flip chip seated, [0044]) and coupling (Cheah: Fig 2 flip chip seated, [0044]) a semiconductor package (Cheah: Fig 2 devices 266, 268,270, [0045]) onto the interposer (Cheah: Fig 2 package substrate 201, [0036]), wherein the semiconductor package (Cheah: Fig 2 devices 266, 268,270, [0045]) and one or more of the plurality of passive devices are coupled to the ground plane.
Cheah as modified in claim 12 fails to teach a ground plane positioned in an upper layer of the printed circuit board; positioning and coupling a plurality of passive devices onto the interposer; wherein the one or more of the plurality of passive devices are coupled to the ground plane.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Wang to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Cheah, Wang, and Kamgaing fail to teach passive devices coupled on the surface.
However, Jain teaches surface mounted passive components (Fig 1 not shown, additional passive components, disposed on the package substrate 102, [0040]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah, Wang, and Kamgaing to incorporate the teachings of Jain by surface mounted passive components. This would allow for design flexibility ([0063]).
In doing so the modifying Cheah and Wang with the teachings of Kamgain and Jain the method for producing a semiconductor platform would have a ground plane (Kamgaing: Fig 1 ground plane 178, [0030]) positioned in an upper layer of a printed circuit board (Cheah: Fig 2 board 274, [0047]); positioning (Jain: disposed on, [0040]) and coupling (Jain: disposed on, [0040]) a plurality of passive devices (Jain: Fig 1 not shown, additional passive components, disposed on the package substrate 102, [0040]) onto the interposer (Cheah: Fig 2 package substrate 201, [0036]); wherein the semiconductor package (Cheah: Fig 2 devices 266, 268,270, [0045]) and one or more of the plurality of passive devices (Jain: Fig 1 not shown, additional passive components, disposed on the package substrate 102, [0040]) are coupled (It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to couple electronic components to a ground for operation) to the ground plane (Kamgaing: Fig 1 ground plane 178, [0030]).
Claims 15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang.
Regarding claim 15, Cheah teaches an interposer (Fig 2 package substrate 201, [0036]) comprising: a low-resistance metal layer (Fig 2 conductive core 210, [0040]) with a top surface (Fig 2 core 210 top surface) and a bottom surface (Fig 2 core 210 bottom surface), the low-resistance metal layer (Fig 2 conductive core 210, [0040]) providing a power corridor (See explanation below) between a plurality of devices device (Fig 2 devices 266, 268, 270, [0045]) coupled to the top surface (Fig 2 core 210 top surface) and a printed circuit board (Fig 2 wiring board 274, [0047]) coupled to the bottom surface (Fig 2 core 210 bottom surface); a first non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the top surface of the metal layer (Fig 2 conductive core 210, [0040]); and a second non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the bottom surface of the metal layer (Fig 2 conductive core 210, [0040]).
Cheah fails to teach a power corridor.
However, Cheah teaches a structure substantially identical to that of the claim. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the structure of Cheah would also be able to function as a power corridor. In support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Cheah fails to teach the first non-conductive layer (Fig 2 dielectric material 214, [0038]) provides a first pattern of openings for solder connections; the second non-conductive layer (Fig 2 dielectric material 214, [0038]) provides a second pattern of openings for solder connections; and a plurality of vertical interconnects formed in the low-resistance metal layer separated by non-conductive vertical separators.
However, Wang teaches forming vias (Fig 7B via V1, [0098]) in a top layer of a non-conductive material (Fig 7B adhesive material 220’, [0098]). Wang further teaches forming vias (Fig 10B via V3, [0115]) in a bottom layer of a non-conductive material (Fig 10B solder mask 260, [0115]). This forms vertical interconnects (Fig 1 conductive structure 214, [0045]) in the low-resistance material (Fig 1 interposer substrate 205, [0048]). Additionally, Cheah teaches reference vias (Fig 3 reference via 320 or 346, [0049] and [0050], respectively) that makes direct contact with the reference layer (Fig 3 reference layer 310 or 332, [0049] and [0050], respectively). One having ordinary skill in the art before the effective filing date of the claimed invention would be able to use the teachings of Wang to form the plurality of vertical interconnects in the low-resistance metal layer of Cheah with a reasonable expectation of success. MPEP 2143(I)(G)
In doing so Cheah as modified by Wang teaches the first non-conductive layer (Cheah: Fig 2 dielectric material 214, [0038]) provides a first pattern of openings (Wang: Fig 7B via V1, [0098]) for solder connections (Fig 2 bumps 264, [0044]); the second non-conductive layer (Cheah: Fig 2 dielectric material 214, [0038]) provides a second pattern of openings (Wang: Fig 10B via V3, [0115]) for solder connections (Fig 2 bumps 272, [0047]); and a plurality of vertical interconnects (Wang: Fig 1 conductive structure 214, [0045]) formed in the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) separated by non-conductive vertical separators (Wang: Fig 1 insulation structure 212, [0045]).
Regarding claim 18, Cheah as modified in claim 15 teaches the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) is copper (Cheah: copper-containing material, [0022]).
Regarding claim 19, Cheah as modified in claim 15 teaches the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) has a thickness in the range of approximately 50 to 200 µm (50 to 500 µm, [0031]). Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Cheah discloses the claimed range with sufficient specificity. MPEP 2131.03(II) ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Regarding claim 20, Cheah as modified in claim 15 teaches the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) has a thickness greater than 120 µm (50 to 500 µm, [0031]). Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Cheah discloses the claimed range with sufficient specificity. MPEP 2131.03(II) ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang in further view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing.
Cheah as modified in claim 15 fails to teach the plurality of vertical interconnects further comprises ground vertical interconnects coupling a plurality of devices to a ground plane positioned in an upper layer of a printed circuit board, and signal vertical interconnects coupling the plurality of devices to input-output traces in the printed circuit board.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
In modifying Cheah and Wang with the teachings of Kamgaing, the plurality of vertical interconnects (Wang: Fig 1 conductive structure 214, [0045]) further comprises ground vertical interconnects (Wang: Fig 1 conductive structure 214 that are connected to the ground plane) coupling a plurality of devices (Cheah: Fig 2 devices 266, 268, 270, [0045]) to a ground plane (Kamgaing: Fig 1 ground plane 178, [0030]) positioned in an upper layer of a printed circuit board (Cheah: Fig 2 wiring board 274, [0047]), and signal vertical interconnects (Wang: Fig 1 conductive structure 214 that are connected to the signal lines plane) coupling the plurality of devices(Cheah: Fig 2 devices 266, 268, 270, [0045]) to input-output traces (Kamgaing: Fig 1 electrical trace 177, [0026]) in the printed circuit board (Cheah: Fig 2 wiring board 274, [0047]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Hovis et. al. (US 20200373285 A1), hereinafter Hovis.
Cheah as modified in claim 15 fails to teach the interposer has one or more openings to accommodate tall devices coupled to a print circuit board.
However, Hovis teaches the interposer (Fig 5 interposer circuit board 151, [0057] corresponds to Cheah: Fig 2 package substrate 201, [0036]) has one or more openings (Fig 5 aperture 152, [0058]) to accommodate tall devices (Fig 5 passive components, [0058]) coupled to ([0058]) a print circuit board (Fig 5 circuit board 411, [0056] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Jain to incorporate the teachings of Hovis by having one or more openings to accommodate tall devices coupled to a print circuit board. This would allow for uneven passive device heights to be compensated for when placing a die on top of the interposer ([0057]).
Conclusion
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813