DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed March 26, 2026 has been entered. Claims 1-6, 8-13, 14-15, and 17-20 remain pending in the application. Applicant’s amendments to the Drawings have overcome each and every objection previously set forth in the Non-Final Office Action mailed November 26, 2026.
Claim Objections
Claim 15 is objected to because of the following informalities:
line 16 appears to have a typo “the plurality of device are…” should read “the plurality of devices are…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing.
Regarding claim 1, Cheah teaches a semiconductor platform (Fig 2 semiconductor device package 200, [0036]) comprising: a printed circuit board (Fig 2 wiring board 274, [0047]); an interposer (Fig 2 package substrate 201, [0036]) coupled to (Fig 2) the print circuit board (Fig 2 wiring board 274, [0047]), the interposer (Fig 2 package substrate 201, [0036]) comprising: a low-resistance conductive layer (Fig 2 conductive core 210, [0040]) with a top surface (Fig 2 core 210 top surface) and a bottom surface (Fig 2 core 210 bottom surface), the low-resistance conductive layer (Fig 2 conductive core 210, [0040]) providing a power corridor (See below) for the semiconductor platform (Fig 2 semiconductor device package 200, [0036]); a first non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the top surface (Fig 2 core 210 top surface) of the low-resistance conductive layer (Fig 2 conductive core 210, [0040]) and a second non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the bottom surface (Fig 2 core 210 bottom surface) of the low-resistance conductive layer (Fig 2 conductive core 210, [0040]); and a plurality of vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]), disposed through (Fig 2), the low-resistance conductive layer (Fig 2 conductive core 210, [0040]); one or more non-conductive vertical separators (Fig 2 vertical portion of dielectric material 214) placed between (Fig 2 vertical portion of dielectric material 214 between vias 222,224, 226 and core 210) the one more of the plurality of vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]) and the low-resistance conductive layer (Fig 2 conductive core 210, [0040]); and a semiconductor package (Fig 2 device 270, [0045]) coupled to (Fig 2) the interposer (Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 2 package substrate 201, [0036]) provides the power corridor for the semiconductor package (Fig 2 device 270, [0045]).
Cheah fails to teach a power corridor, and a printed circuit board comprising a plurality of layers, wherein a layer of the plurality of layers is a ground plane, wherein one or more of the plurality of vertical interconnects is coupled to the ground plane via a vertical interconnect of the plurality of vertical interconnects.
However, Cheah teaches a structure substantially identical to that of the claim. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the structure of Cheah would also be able to function as a power corridor. In support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
However, Kamgaing teaches a printed circuit board (Fig 1 package substrate 108, [0026] corresponds to Cheah: Fig 2 wiring board 274, [0047]) comprising a plurality of layers (Fig 1 includes layers, [0026]), wherein a layer (Fig 1 bottom most layer 174, [0029]) of the plurality of layers (Fig 1 metal layers 174, [0026]) is a ground plane (Fig 1 ground plane 178, [0030]), wherein one or more of the plurality of vertical interconnects (Fig 1 TSVs 150, [0023] corresponds to Cheah: Fig 2 vias 220, 222, 224, 226, [0038]) is coupled to the ground plane (Fig 1 ground plane 178, [0030]) via a vertical interconnect (Fig 1 left most TSV 150) of the plurality of vertical interconnects (Fig 1 TSVs 150, [0023] corresponds to Cheah: Fig 2 vias 220, 222, 224, 226, [0038]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having a printed circuit board with a plurality of layers, one of the layers being a ground plane. This would allow for proper operation of semiconductor packages and passive devices coupled to the printed circuit board through the interposer. Also, this would provide a ground for coupling with a shield ([0030]). Examiner notes the printed wiring board of Cheah also has a plurality of layers, which would need wiring layers to be able to couple the wiring board to a larger system.
Regarding claim 8, Cheah as modified in claim 1 teaches the plurality of vertical interconnects (Fig 2 vias 220, 222, 224, 226, [0038]) comprises a second vertical interconnect (Fig 2 via 222, [0038]) through the interposer (Fig 2 package substrate 201, [0036]) coupling the semiconductor package (Fig 2 device 268, [0045]).
Cheah fails to teach a signal line in the printed circuit board.
However, Kamgaing teaches a signal line (Fig 1 electrical trace 177, [0026]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having signal lines in the printed circuit board. This would allow for the transmission of signals from different components on the printed circuit board.
Regarding claim 10, Cheah as modified in claim 1 teaches a ball grid array (Cheah: Fig 2 bump array 272, [0047]) with a plurality of solder balls (Cheah: Fig 2 bump array 272, [0047]) for power connections, wherein the plurality of solder balls (Cheah: Fig 2 bump array 272, [0047]) for power connections are coupled to the interposer (Cheah: Fig 2 package substrate 201, [0036]).
Cheah fails to teach power connections.
However, Cheah teaches a structure substantially identical to that of the claim. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the structure of Cheah would also have power connections. In support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Regarding claim 11, Cheah as modified in claim 1 teaches the low-resistance conductive layer (Cheah: Fig 2 conductive core 210, [0040]) has a thickness in the range of approximately 50 to 200 µm (Cheah: 50 to 500 µm, [0031]). Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Cheah discloses the claimed range with sufficient specificity. MPEP 2131.03(II) ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Claims 2-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing, in further view of Jain et. al. (US 20190304915 A1), hereinafter Jain.
Regarding claim 2, Cheah as modified in claim 1 fails to teach a voltage regulator or power management integrated circuit device coupled to the interposer, wherein the interposer provides the power corridor for the voltage regulator or power management integrated circuit.
However, Jain teaches a voltage regulator (Fig 1 die 114, [0036]; the die may be a voltage regulator) or (optional so not considered) power management integrated circuit device coupled to (Fig 1) the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]) provides the power corridor for the voltage regulator (Fig 1 die 114, [0036]; the die may be a voltage regulator) or (optional so not considered) power management integrated circuit.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Kamgaing to incorporate the teachings of Jain by having a voltage regulator coupled to the interposer. This would allow for a power delivery network on the interposer ([0059]).
Regarding claim 3, Cheah as modified in claim 1 fails to teach a first passive device coupled to the interposer, wherein the interposer provides the power corridor for the first passive device.
However, Jain teaches a first passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) coupled to the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]) provides the power corridor for the first passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Kamgaing to incorporate the teachings of Jain by having a first passive device. This would allow for a portion of a filter on the interposer ([0059]).
Regarding claim 4, Cheah as modified in claim 3 teaches the first passive device (Jain: Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) is an inductor (Jain: Fig 9 inductor 933, [0059]; not shown on surface).
Regarding claim 5, Cheah as modified in claim 1 fails to teach a second passive device coupled to the interposer, wherein the interposer provides the power corridor for the second passive device.
However, Jain teaches a second passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) coupled to the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]), wherein the interposer (Fig 1 package substrate 102, [0036] corresponds to Cheah: Fig 2 package substrate 201, [0036]) provides the power corridor for the second passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Kamgaing to incorporate the teachings of Jain by having a second passive device. This would allow for a portion of a filter on the interposer ([0059]).
Regarding claim 9, Cheah as modified in claim 2 teaches the plurality of vertical interconnects (Cheah: Fig 2 vias 220, 222, 224, 226, [0038]) comprises a third vertical interconnect (Cheah: Fig 2 via 220, [0038]) through the interposer (Cheah: Fig 2 package substrate 201, [0036]) coupling the voltage regulator (Jain: Fig 1 die 114, [0036]; the die may be a voltage regulator) or (optional so not considered) power management integrated circuit device.
Cheah as modified in claim 2 fails to teach a ground plane positioned in an upper layer of the printed circuit board.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing, in further view of Jain et. al. (US 20190304915 A1), hereinafter Jain, in further view of Hovis et. al. (US 20200373285 A1), hereinafter Hovis.
Cheah as modified in claim 5 teaches the second passive device (Fig 9 inductor 933, [0059]; not shown on surface; however, Jain teaches the power delivery network may be on a package substrate 102 corresponds to package substrate 201 of Cheah) is an inductor (Jain: Fig 9 inductor 933, [0059]; not shown).
Cheah as modified in claim 5 fails to teach the inductor is attached to the printed circuit board and the interposer further comprises an opening for accommodating the inductor.
However, Hovis teaches the inductor (Fig 5 not labeled inductor, [0058] corresponds to Jain: Fig 9 inductor 933, [0059]; not shown) is attached to (Fig 1 connected with solder balls 375) the printed circuit board (Fig 5 circuit board 411, [0056] corresponds to Cheah: Fig 2 wiring board 274, [0047]) and the interposer (Fig 5 interposer circuit board 151, [0057] corresponds to Cheah: Fig 2 package substrate 201, [0036]) further comprises an opening (Fig 5 aperture 152, [0058]) for accommodating the inductor (Fig 5 not labeled inductor, [0058] corresponds to Jain: Fig 9 inductor 933, [0059]; not shown).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah, Kamgaing, and Jain to incorporate the teachings of Hovis by having an opening for accommodating the inductor. This would allow for uneven passive device heights to be compensated for when placing a die on top of the interposer ([0057]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing, in further view of Jain et. al. (US 20190304915 A1), hereinafter Jain.
Cheah teaches a method (Figs 1A-1K, [0036]) comprising: providing (Fig 1A) a low-resistance metal layer (Fig 1A reference layer 110, [0022]) with a top surface (Fig 1A top of reference layer 110) and a bottom surface (Fig 1A bottom of reference layer 110), the low-resistance metal layer (Fig 1A reference layer 110, [0022]) providing a power corridor (Similar to claim 1; the structure of Cheah is similar and this can perform a similar function) for a semiconductor platform (Fig 2 semiconductor device package 200, [0036]); forming (Fig 1A pattern, [0022]) a plurality of vertical openings (Fig 1A through-holes 112, [0022]) through the low-resistance metal layer (Fig 1A reference layer 110, [0022]); forming (Fig 1B spinning on, [0024]) a first non-conductive layer (Fig 1B dielectric layer 114, [0024]) positioned (spinning on, [0024]) on the top surface (Fig 1B top of reference layer 110) of the low-resistance metal layer (Fig 1B reference layer 110, [0022]) and a second non-conductive layer (Fig 1B dielectric layer 114, [0024]) positioned on (spinning on, [0024]) the bottom surface (Fig 1B bottom of reference layer 110) of the low-resistance metal layer (Fig 1B reference layer 110, [0022]); filling (Fig 1B filling, [0024]) the plurality of vertical openings (Fig 1B through-holes 112, [0024]) to form non-conductive vertical separators (Fig 1B not labeled); and positioning (Fig 2 flip chip seated, [0044]) and coupling (Fig 2 flip chip seated, [0044]) a semiconductor package (Fig 2 devices 266, 268,270, [0045]) onto the interposer (Fig 2 package substrate 201, [0036]), wherein the semiconductor package (Fig 2 devices 266, 268,270, [0045]) and one or more of the plurality of passive devices are coupled to the ground plane.
Cheah fails to each a plurality of vertical interconnects in the low-resistance metal layer, wherein the first non-conductive layer, the low-resistance metal layer, the second non-conductive layer, and the plurality of vertical interconnects form an interposer with the power corridor; and forming a first pattern of openings for solder connections in the first non-conductive layer and a second pattern of openings for solder connections in the second non-conductive layer; positioning and coupling the interposer onto a printed circuit board with a ground plane positioned in an upper layer of the printed circuit board, wherein the semiconductor package is connected to a power source via the low-resistance metal layer and is connected to the ground plane via a vertical interconnect of the plurality of vertical interconnects.
However, Wang teaches forming vias (Fig 7B via V1, [0098]) in a top layer of a non-conductive material (Fig 7B adhesive material 220’, [0098]). Wang further teaches forming vias (Fig 10B via V3, [0115]) in a bottom layer of a non-conductive material (Fig 10B solder mask 260, [0115]). This forms vertical interconnects (Fig 1 conductive structure 214, [0045]) in the low-resistance material (Fig 1 interposer substrate 205, [0048]). Additionally, Cheah teaches reference vias (Fig 3 reference via 320 or 346, [0049] and [0050], respectively) that makes direct contact with the reference layer (Fig 3 reference layer 310 or 332, [0049] and [0050], respectively). One having ordinary skill in the art before the effective filing date of the claimed invention would be able to use the teachings of Wang to form the plurality of vertical interconnects in the low-resistance metal layer of Cheah with a reasonable expectation of success. MPEP 2143(I)(G)
In doing so Cheah would have a plurality of vertical interconnects (From Wang) in the low-resistance metal layer (Cheah: Fig 1B reference layer 110, [0022]), wherein the first non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]), the low-resistance metal layer (Cheah: Fig 1A reference layer 110, [0022]), the second non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]), and the plurality of vertical interconnects (From Wang) form an interposer (Cheah: Fig 2 package substrate 201, [0036]) with the power corridor (Similar to claim 1; the structure of Cheah is similar and this can perform a similar function); and forming a first pattern of openings (Wang: Fig 7B via V1, [0098]) for solder connections (Cheah: Fig 2 bump array with bump 264, [0044]) in the first non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]) and a second pattern of openings (Wang: Fig 10B via V3, [0115]) for solder connections (Cheah: Fig 2 bump array with bump 272, [0047]) in the second non-conductive layer (Cheah: Fig 1B dielectric layer 114, [0024]); positioning (Cheah: Fig 2 mounting with bump array 272, [0047]) and coupling (Cheah: Fig 2 mounting with bump array 272, [0047]) the interposer (Cheah: Fig 2 package substrate 201, [0036]) onto a printed circuit board (Cheah: Fig 2 board 274, [0047]);.
Cheah and Wang fail to teach a ground plane positioned in an upper layer of the printed circuit board; positioning and coupling a plurality of passive devices onto the interposer; wherein the one or more of the plurality of passive devices are coupled to the ground plane; and wherein the semiconductor package is connected to a power source via the low-resistance metal layer and is connected to the ground plane via a vertical interconnect of the plurality of vertical interconnects.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Wang to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Cheah, Wang, and Kamgaing fail to teach passive devices coupled on the surface.
However, Jain teaches surface mounted passive components (Fig 1 not shown, additional passive components, disposed on the package substrate 102, [0040]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah, Wang, and Kamgaing to incorporate the teachings of Jain by surface mounted passive components. This would allow for design flexibility ([0063]).
In doing so the modifying Cheah and Wang with the teachings of Kamgain and Jain the method for producing a semiconductor platform would have a ground plane (Kamgaing: Fig 1 ground plane 178, [0030]) positioned in an upper layer of a printed circuit board (Cheah: Fig 2 board 274, [0047]); positioning (Jain: disposed on, [0040]) and coupling (Jain: disposed on, [0040]) a plurality of passive devices (Jain: Fig 1 not shown, additional passive components, disposed on the package substrate 102, [0040]) onto the interposer (Cheah: Fig 2 package substrate 201, [0036]); wherein the semiconductor package (Cheah: Fig 2 devices 266, 268,270, [0045]) and one or more of the plurality of passive devices (Jain: Fig 1 not shown, additional passive components, disposed on the package substrate 102, [0040]) are coupled (It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to couple electronic components to a ground for operation) to the ground plane (Kamgaing: Fig 1 ground plane 178, [0030]); and is connected to the ground plane (Kamgaing: Fig 1 ground plane 178, [0030]) via a vertical interconnect of the plurality of vertical interconnects (From the modification with Wang; one of the vertical interconnects would connect to the ground plane, similar to that of Kamgaing).
Cheah, Wang, Kamgaing, and Jain fail to teach the semiconductor package is connected to a power source via the low-resistance metal layer.
However, Cheah teaches a structure substantially identical to that of the claim. To connect devices and the interposer to a power source there would be two structures to which one can apply power: either the low-resistance metal layer or an interconnect. One having ordinary skill in the art would recognize that the plurality of devices could be powered either via the low-resistance metal layer or via an interconnect, regardless of which of these structures is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Thus, the semiconductor package (Cheah: Fig 2 devices 266, 268,270, [0045]) would be connected to a power source (Cheah: it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that there would be a power source connected to the board 274) via the low-resistance metal layer (Cheah: Fig 1A reference layer 110, [0022]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Lee et. al. (US 20200161231 A1).
Cheah as modified in claim 12 fails to teach a device opening in the interposer by forming a space in the interposing and depositing a sacrificial material in the space; and removing the sacrificial material to form the device opening.
However, Wang teaches a device opening (Fig 10C cavity 230, [0114]) in the interposer (Fig 10C interposer 200, [0114]) by forming a space (Fig 10C cavity 230, [0114]) in the interposer (Fig 10C interposer 200, [0114]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Wang by having a device opening. This would allow for effective utilization of space ([0047]).
Cheah as modified above fails to teach depositing a sacrificial material in the space; and removing the sacrificial material to form the device opening.
However, Lee teaches depositing a sacrificial material (Fig 12 dummy member 125, [0061]) in the space (not labeled; area where electronic components are not disposed, [0061] corresponds to Wang: Fig 10C cavity 230, [0114]); and removing (Fig 12 penetration hole 150H, [0061]) the sacrificial material (Fig 12 dummy member 125, [0061]) to form the device opening (Fig 12 penetration hole 150H, [0061] corresponds to Wang: Fig 10C cavity 230, [0114]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Wang to incorporate the teachings of Lee by having a sacrificial material in a space. This would prevent possible contamination at the edges of the device opening due to undulations ([0060]).
Claims 15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Kamgaing et. al. (US 20200219861 A1), hereinafter Kamgaing.
Regarding claim 15, Cheah teaches an interposer (Fig 2 package substrate 201, [0036]) comprising: a low-resistance metal layer (Fig 2 conductive core 210, [0040]) with a top surface (Fig 2 core 210 top surface) and a bottom surface (Fig 2 core 210 bottom surface), the low-resistance metal layer (Fig 2 conductive core 210, [0040]) providing a power corridor (See explanation below) between a plurality of devices device (Fig 2 devices 266, 268, 270, [0045]) coupled to the top surface (Fig 2 core 210 top surface) and a printed circuit board (Fig 2 wiring board 274, [0047]) coupled to the bottom surface (Fig 2 core 210 bottom surface); a first non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the top surface of the low-resistance metal layer (Fig 2 conductive core 210, [0040]); and a second non-conductive layer (Fig 2 dielectric material 214, [0038]) positioned on the bottom surface of the low-resistance metal layer (Fig 2 conductive core 210, [0040]), wherein the plurality of vertical interconnects further comprises ground vertical interconnects coupling a plurality of devices to a ground plane positioned in an upper layer of a printed circuit board, and signal vertical interconnects coupling the plurality of devices to input-output traces in the printed circuit board, and wherein the plurality of device are connected to a power source via the low-resistance metal layer.
Cheah fails to teach a power corridor.
However, Cheah teaches a structure substantially identical to that of the claim. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the structure of Cheah would also be able to function as a power corridor. In support of Examiner’s position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Cheah fails to teach the first non-conductive layer (Fig 2 dielectric material 214, [0038]) provides a first pattern of openings for solder connections; the second non-conductive layer (Fig 2 dielectric material 214, [0038]) provides a second pattern of openings for solder connections; and a plurality of vertical interconnects formed in the low-resistance metal layer separated by non-conductive vertical separators.
However, Wang teaches forming vias (Fig 7B via V1, [0098]) in a top layer of a non-conductive material (Fig 7B adhesive material 220’, [0098]). Wang further teaches forming vias (Fig 10B via V3, [0115]) in a bottom layer of a non-conductive material (Fig 10B solder mask 260, [0115]). This forms vertical interconnects (Fig 1 conductive structure 214, [0045]) in the low-resistance material (Fig 1 interposer substrate 205, [0048]). Additionally, Cheah teaches reference vias (Fig 3 reference via 320 or 346, [0049] and [0050], respectively) that makes direct contact with the reference layer (Fig 3 reference layer 310 or 332, [0049] and [0050], respectively). One having ordinary skill in the art before the effective filing date of the claimed invention would be able to use the teachings of Wang to form the plurality of vertical interconnects in the low-resistance metal layer of Cheah with a reasonable expectation of success. MPEP 2143(I)(G)
In doing so Cheah as modified by Wang teaches the first non-conductive layer (Cheah: Fig 2 dielectric material 214, [0038]) provides a first pattern of openings (Wang: Fig 7B via V1, [0098]) for solder connections (Fig 2 bumps 264, [0044]); the second non-conductive layer (Cheah: Fig 2 dielectric material 214, [0038]) provides a second pattern of openings (Wang: Fig 10B via V3, [0115]) for solder connections (Fig 2 bumps 272, [0047]); and a plurality of vertical interconnects (Wang: Fig 1 conductive structure 214, [0045]) formed in the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) separated by non-conductive vertical separators (Wang: Fig 1 insulation structure 212, [0045]).
Cheah and Wang fail to teach the plurality of vertical interconnects further comprises ground vertical interconnects coupling a plurality of devices to a ground plane positioned in an upper layer of a printed circuit board, and signal vertical interconnects coupling the plurality of devices to input-output traces in the printed circuit board, and wherein the plurality of device are connected to a power source via the low-resistance metal layer.
However, Kamgaing teaches a ground plane (Fig 1 ground plane 178, [0030]) in the printed circuit board (Fig 1 main board 108, [0024] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah to incorporate the teachings of Kamgaing by having a ground plane in a circuit board. This would provide a ground for coupling with a shield ([0030]).
Regarding the ground plane being positioned in an upper layer of the printed circuit board. Kamgaing teaches the main board needs a ground plane to couple a shield 190 to the package substrate ([0030]). In pursuing this arrangement, there are only four locations to achieve the placement of the ground plane: any of the metallization layers 174. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that a ground plane would function the same, regardless of which of the metallization layers is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
In modifying Cheah and Wang with the teachings of Kamgaing, the plurality of vertical interconnects (Wang: Fig 1 conductive structure 214, [0045]) further comprises ground vertical interconnects (Wang: Fig 1 conductive structure 214 that are connected to the ground plane) coupling a plurality of devices (Cheah: Fig 2 devices 266, 268, 270, [0045]) to a ground plane (Kamgaing: Fig 1 ground plane 178, [0030]) positioned in an upper layer of a printed circuit board (Cheah: Fig 2 wiring board 274, [0047]), and signal vertical interconnects (Wang: Fig 1 conductive structure 214 that are connected to the signal lines plane) coupling the plurality of devices (Cheah: Fig 2 devices 266, 268, 270, [0045]) to input-output traces (Kamgaing: Fig 1 electrical trace 177, [0026]) in the printed circuit board (Cheah: Fig 2 wiring board 274, [0047]).
Cheah, Wang, and Kamgaing fail to teach the plurality of devices are connected to a power source via the low-resistance metal layer.
However, Cheah teaches a structure substantially identical to that of the claim. To connect devices and the interposer to a power source there would be two structures to which one can apply power: either the low-resistance metal layer or an interconnect. One having ordinary skill in the art would recognize that the plurality of devices could be powered either via the low-resistance metal layer or via an interconnect, regardless of which of these structures is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Thus, the plurality of devices (Cheah: Fig 2 devices 266, 268, 270, [0045]) would be connected to a power source (Cheah: it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that there would be a power source connected to the board 274) via the low-resistance metal layer (Cheah: Fig 1A reference layer 110, [0022]).
Regarding claim 18, Cheah as modified in claim 15 teaches the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) is copper (Cheah: copper-containing material, [0022]).
Regarding claim 19, Cheah as modified in claim 15 teaches the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) has a thickness in the range of approximately 50 to 200 µm (50 to 500 µm, [0031]). Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Cheah discloses the claimed range with sufficient specificity. MPEP 2131.03(II) ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Regarding claim 20, Cheah as modified in claim 15 teaches the low-resistance metal layer (Cheah: Fig 2 conductive core 210, [0040]) has a thickness greater than 120 µm (50 to 500 µm, [0031]). Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Cheah discloses the claimed range with sufficient specificity. MPEP 2131.03(II) ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et. al. (US 20200168559 A1), hereinafter Cheah, in view of Wang et. al. (US 20230268257 A1), hereinafter Wang, in further view of Hovis et. al. (US 20200373285 A1), hereinafter Hovis.
Cheah as modified in claim 15 fails to teach the interposer has one or more openings to accommodate tall devices coupled to a print circuit board.
However, Hovis teaches the interposer (Fig 5 interposer circuit board 151, [0057] corresponds to Cheah: Fig 2 package substrate 201, [0036]) has one or more openings (Fig 5 aperture 152, [0058]) to accommodate tall devices (Fig 5 passive components, [0058]) coupled to ([0058]) a print circuit board (Fig 5 circuit board 411, [0056] corresponds to Cheah: Fig 2 wiring board 274, [0047]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheah and Jain to incorporate the teachings of Hovis by having one or more openings to accommodate tall devices coupled to a print circuit board. This would allow for uneven passive device heights to be compensated for when placing a die on top of the interposer ([0057]).
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 8, filed March 26, 2026, with respect to incorporation of changes suggested into claims have been fully considered and are persuasive. The 35 USC §112 of claims 1-20 has been withdrawn.
Referring to the initial matter in the second paragraph on page 9, filed March 26, 2026, with respect to Cheah559, Examiner notes that [0020] of Cheah559 discloses the reference layers as a package core. The package core being a supporting structure within a semiconductor device package, which is then "mounted on a board such as a printed wiring board." This would equate the reference layers to an interposer.
Applicant’s arguments, see 35 USC §102/103 section beginning at the second to last paragraph on page 9, filed March 26, 2026, with respect to the rejections of claims 1, 12, and 15 under 35 USC §102 and 103, respectively, have been fully considered but they are not persuasive.
In response to applicant’s argument that the low-resistance conductive layer is connected to a power source, while the cited art is connected to ground, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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