DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,4-10 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US9947804B1) in view of Chao et al. (US20180308986A1).
Regarding claim 1, Fig.14 of Frougier teaches a semiconductor structure comprising:
an isolation layer 146 (col.10, line 52, wherein portions of insulative regions are under nanosheet stack) under a nanosheet stack 114 (col.6, line 26) of a transistor, inner spacers 148 (col.11, line 29) being formed adjacent to nanosheets 116/118 (col.15, lines 7-8) of the nanosheet stack 114, wherein the inner spacers 148 are formed of inner spacer material; and
wherein the isolation layer 146 is in contact with the inner spacers 148 and in contact with a top surface of the graded layer, wherein the inner spacer material (see annotated Fig.14) is disposed under the isolation layer 146 and on the graded layer.
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Frougier does not teach a graded layer under the isolation layer, the graded layer comprising an impurity gradient of germanium.
Fig. 8B of Chao teaches a nanosheet semiconductor device that includes a buffer layer 109 that is formed between the substrate and the channel nanosheet. The buffer layer 109 can be formed from SiGe having a Ge concentration from about 20 atomic percent to less than 40 atomic percent. The buffer layer 109 can have a graded Ge content that varies throughout the buffer layer 109. An annealing process causes some of the Si in the buffer layer 109 to oxidize into the layer 200 and condenses Ge from layer 200 into the buffer layer 109, forming a modified buffer layer 300 and layer 400 (isolation layer). The layer 400 includes SiO.sub.2 and the modified buffer layer 300 includes an increased concentration of Ge as compared to the buffer layer 109. Increasing the Ge concentration of SiGe reduces the conductivity of the SiGe. Thus, the modified buffer layer 300 has a reduced conductivity relative to the buffer layer 109. (para.0047, 0056-0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the modified buffer layer of Chao in the teachings of Frougier in order to provide a lower conductivity than the channel nanosheet and thus helps when a voltage is applied to the gate of the nanosheet FET that is greater than a threshold voltage because current flows through the more conductive channel nanosheets, rather than the less conductive modified buffer layer and as result, the modified buffer layer prevents leakage current (Chao, [para.0040]).
Regarding claim 2, the combination of Frougier and Chao teaches the semiconductor structure of claim 1, wherein the graded layer comprises a tapered profile (wherein transistor sites 128 have tapered profiles as illustrated in Fig.14).
Regarding claim 4, the combination of Frougier and Chao teaches the semiconductor structure of claim 1, wherein the graded layer comprises a tapered profile in correlation with an impurity concentration in the impurity gradient. Frougier teaches wherein the transistor sites 128 have a tapered profile and Chao teaches a modified buffer layer 300 that is made from a buffer layer 109, with a graded Ge content that varies throughout the buffer layer 109. The combination of Frougier and Chao thus gives a graded layer with a tapered profile.
Regarding claim 5, Frougier further teaches the semiconductor structure of claim 1, wherein the isolation layer 146 (col.10, line 52) is under a gate region 120 (col.12, line 6) of the transistor.
Regarding claim 6, Frougier further teaches the semiconductor structure of claim 1, wherein at least a portion of a buried inner spacer layer (see annotated Fig.14) extends under a gate region 120 (col.12, line 6) of the transistor.
Regarding claim 7, combination of Frougier and Chao teaches the semiconductor structure of claim 1, wherein a buried inner spacer layer (Frougier, see annotated Fig.14) is adjacent to both the isolation layer 146 (Frougier, col.10, line 52) and the graded layer 300 (Chao, para.0056).
Regarding claim 8, Frougier further teaches the semiconductor structure of claim 1, wherein a buried inner spacer layer (see annotated Fig.14) is under the isolation layer 146 (col.10, line 52) and comprises a tapered profile.
Regarding claim 9, Frougier further teaches the semiconductor structure of claim 1, wherein the isolation layer 146 (col.10, line 52) and a buried inner spacer layer (see annotated Fig.14) are under the inner spacers 148 (col.11, line 29), the inner spacers 148 being adjacent to a gate region 120 (col.12, line 6).
Regarding claim 10, the combination of Frougier and Chao teaches the semiconductor structure of claim 1, wherein another isolation layer (Frougier, see annotated Fig.14) is under a source/drain region 150 (Frougier, col.12 lines 11-12) of the transistor, the another isolation layer being adjacent to the isolation layer 146 (col.10, line 52) and a buried inner spacer layer (Frougier, see annotated Fig.14).
Regarding claim 21, Fig.14 of Frougier teaches a semiconductor structure comprising:
an isolation layer 146 (col.10, line 52, wherein portions of insulative regions are under nanosheet stack) under a nanosheet stack 114 (col.6, line 26) of a transistor, the transistor comprising a source/drain region 150 (col.12, line 11) and inner spacers 148 (col.11, line 29) adjacent to nanosheets 116/118 (col.15, lines 7-8) of the nanosheet stack 114;
Frougier does not teach a graded layer under the isolation layer, the graded layer comprising an impurity gradient of germanium, wherein the isolation layer is in contact with the inner spacers and in contact with a top surface of the graded layer; and
a sublayer under the graded layer and adjacent to the source/drain region.
Fig. 8B of Chao teaches a nanosheet semiconductor device that includes a buffer layer 109 that is formed between the substrate and the channel nanosheet. The buffer layer 109 can be formed from SiGe having a Ge concentration from about 20 atomic percent to less than 40 atomic percent. The buffer layer 109 can have a graded Ge content that varies throughout the buffer layer 109. An annealing process causes some of the Si in the buffer layer 109 to oxidize into the layer 200 and condenses Ge from layer 200 into the buffer layer 109, forming a modified buffer layer 300 and layer 400 (isolation layer). The layer 400 includes SiO.sub.2 and the modified buffer layer 300 includes an increased concentration of Ge as compared to the buffer layer 109. Increasing the Ge concentration of SiGe reduces the conductivity of the SiGe. Thus, the modified buffer layer 300 has a reduced conductivity relative to the buffer layer 109. (para.0047, 0056-0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the modified buffer layer of Chao in the teachings of Frougier in order to provide a lower conductivity than the channel nanosheet and thus helps when a voltage is applied to the gate of the nanosheet FET that is greater than a threshold voltage because current flows through the more conductive channel nanosheets, rather than the less conductive modified buffer layer and as result, the modified buffer layer prevents leakage current (Chao, [para.0040]).
Regarding claim 22, the combination of Frougier and Chao teaches the semiconductor structure of claim 21, wherein: the graded layer 300 (Chao, para.0056) comprises a tapered profile (wherein transistor sites 128 have tapered profiles as illustrated in Fig.14 of Frougier); and a buried inner spacer layer see annotated Fig.14) is under the isolation layer 146 (Frougier, col.10, line 52) and adjacent to the graded layer 300.
Regarding claim 23, Frougier further teaches the semiconductor structure of claim 21, wherein the sublayer 108 (para.0043) comprises a super steep retrograde well (SSRW) region (para.0038, wherein a surface portion of the substrate is doped).
Regarding claim 24, Frougier further teaches the semiconductor structure of claim 21, wherein the sublayer 108 (para.0043, wherein suitable materials for the substrate 108 include SiGeC (silicon-germanium-carbon)) comprises silicon doped with carbon.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US9947804B1) in view of Chao et al. (US20180308986A1) and in further view of He et al. (US20230178420A1).
Regarding claim 3, the combination of Frougier and Chao does not disclose wherein the graded layer comprises a higher concentration of the germanium in the impurity gradient at a region nearest the isolation layer and comprises a lower concentration of the germanium at another region farthest away from the isolation layer.
Fig.2V of He teaches a transistor device that includes a plurality of nanosheet stack on a substrate 110 and a buffer layer 245 is formed on the upper surface of the substrate 110. The buffer layer 245 may have a gradient Ge distribution in which a concentration of Ge is lower adjacent the substrate 110 and gradually increases along the direction Z to about 30% near the top surface of the buffer layer 245 (para.0047).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the buffer layer of He in the teachings of Frougier, as modified by Chao, because instead of performing substitutional carbon doping to reduce lattice strain, the buffer layer 245 may support deposition of the bottom sacrificial layer SL-B without relaxation (He, [para.0047]).
Claims 11,12,14-20 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chao et al. (US20180308986A1) in view of Frougier et al. (US9947804B1).
Regarding claim 11, Fig.8B of Chao teaches a method comprising: providing a graded layer 300 (para.0056, wherein layer 300 is made from layer 109 which can have a graded Ge content that varies throughout the buffer layer (para.0047)) comprising an impurity gradient of germanium; and forming an isolation layer 400 (para.0057) above the graded layer 300 and under a nanosheet stack 102/104/106 (para.0058) of a transistor,
Chao does not teach inner spacers being formed adjacent to nanosheets of the nanosheet stack, wherein the inner spacers are formed of inner spacer material, wherein the isolation layer is in contact with the inner spacers and in contact with a top surface of the graded layer, wherein the inner spacer material is disposed under the isolation layer and on the graded layer.
Fig.14 of Frougier teaches a nanosheet transistor that includes a plurality of stacked nanosheets extending between a pair of source/drain epitaxial regions; inner spacers 148 are positioned between alternating nanosheets in nanosheet stack 114. Portions of isolation regions 146 are in contact with the inner spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the inners spacers of Frougier in the teachings of Chao in order to provide insulation to the transistor.
Regarding claim 12, the combination of Frougier and Chao teaches the method of claim 11, wherein the graded layer comprises a tapered profile (wherein transistor sites 128 have tapered profiles as illustrated in Fig.14 of Frougier).
Regarding claim 14, the combination of Frougier and Chao teaches the method of claim 11, wherein the graded layer comprises a tapered profile in correlation with an impurity concentration in the impurity gradient. Frougier teaches wherein the transistor sites 128 have a tapered profile and Chao teaches a modified buffer layer 300 that is made from a buffer layer 109, with a graded Ge content that varies throughout the buffer layer 109. The combination of Frougier and Chao, thus, gives a graded layer with a tapered profile.
Regarding claim 15, Frougier further teaches the method of claim 11, wherein the isolation layer 146 (col.10, line 52) is under a gate region 120 (col.12, line 6) of the transistor.
Regarding claim 16, Frougier further teaches the method of claim 11, wherein at least a portion of a buried inner spacer layer (see annotated Fig.14) extends under a gate region 120 (col.12, line 6) of the transistor.
Regarding claim 17, the combination of Frougier and Chao teaches the method of claim 11, wherein a buried inner spacer layer (Frougier, see annotated Fig.14) is adjacent to both the isolation layer 146 (Frougier, col.10, line 52) and the graded layer 300 (Chao, para.0056).
Regarding claim 18, Frougier further teaches the method of claim 11, wherein a buried inner spacer layer (Frougier, see annotated Fig.14) is under the isolation layer 146 (Frougier, col.10, line 52) and comprises a tapered profile.
Regarding claim 19, Frougier further teaches the method of claim 11, wherein the isolation layer 146 (Frougier, col.10, line 52) and a buried inner spacer layer (Frougier, see annotated Fig.14) are under the inner spacers 148 (col.11, line 29), the inner spacers 148 being adjacent to a gate region 120 (col.12, line 6).
Regarding claim 20, the combination of Frougier and Chao teaches the method of claim 11, wherein another isolation layer (see annotated Fig.14) is under a source/drain region 150 (col.12 lines 11-12) of the transistor, the another isolation layer being adjacent to the isolation layer and a buried inner spacer layer (see annotated Fig.14).
Regarding claim 25, Fig.8B of Chao teaches a method comprising:
providing a graded layer 300 (para.0056) comprising an impurity gradient of germanium, wherein a sublayer is under the graded layer 300; and
forming an isolation layer 400 (para.0057) above the graded layer 300 and under a nanosheet stack 102/104/106 (para.0058) of a transistor, the transistor comprising a source/drain region 20 (para.0053) adjacent to the graded layer 300.
Chao does not teach inner spacers being formed adjacent to nanosheets of the nanosheet stack, wherein the isolation layer is in contact with the inner spacers and in contact with a top surface of the graded layer.
Fig.14 of Frougier teaches a nanosheet transistor that includes a plurality of stacked nanosheets extending between a pair of source/drain epitaxial regions; inner spacers 148 are positioned between alternating nanosheets in nanosheet stack 114. Portions of isolation regions 146 are in contact with the inner spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the inners spacers of Frougier in the teachings of Chao in order to provide insulation to the transistor.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chao et al. (US20180308986A1) in view of Frougier et al. (US9947804B1) and in further view of He et al. (US20230178420A1).
Regarding claim 13, the combination of Frougier and Chao does not disclose wherein the graded layer comprises a higher concentration of the germanium in the impurity gradient at a region nearest the isolation layer and comprises a lower concentration of the germanium at another region farthest away from the isolation layer.
Fig.2V of He teaches a transistor device that includes a plurality of nanosheet stack on a substrate 110 and a buffer layer 245 is formed on the upper surface of the substrate 110. The buffer layer 245 may have a gradient Ge distribution in which a concentration of Ge is lower adjacent the substrate 110 and gradually increases along the direction Z to about 30% near the top surface of the buffer layer 245 (para.0047).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the buffer layer of He in the teachings of Frougier, as modified by Chao, because instead of performing substitutional carbon doping to reduce lattice strain, the buffer layer 245 may support deposition of the bottom sacrificial layer SL-B without relaxation (He, [para.0047]).
Conclusion
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891