Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Page 10, Paragraphs 6-7 of applicant’s arguments, filed 11/12/2025, with respect to the rejection(s) of claim(s) 1 and 17, as well as dependent claims in view of Liaw(US 20190164971 A1, hereafter Liaw) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Liaw 2(US 20190288069 A1, hereafter Liaw 2). Furthermore, additional rejections are made over Liaw in view of Liaw 2. The amendments overcome the prior rejections but do not bring the claims into the conditions for allowance for the reasons given below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 17 recite the limitations of “gate electrodes”, such as first gate electrodes, second gate electrodes, etc., however later in the claim the terminology appears to shift to “gate structure”, which while examiner believes is referring to the same thing, the inconsistent terminology gives rise to a lack of antecedent basis. Appropriate correction is needed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw 2
Regarding Claim 1, Liaw 2 discloses:
A semiconductor structure(Fig. 3B/4A), comprising:
A semiconductor substrate(Fig. 4A [164]);
A first well region(Fig. 4A [160]) with a first conductivity type(N-type) over the semiconductor substrate(Fig. 4A [164]);
A second well region(Fig. 4A [162]) with a second conductivity type(P-type) over the semiconductor substrate(Fig. 4A [164]), wherein the first conductivity type is different from the second conductivity type; and
A logic cell(Fig. 3B), comprising:
At least one first transistor(Fig. 3B See figure below) in a first active region(Fig. 4A [210]) over the first well region(Fig. 4A [160]), and comprising a first gate electrode(Fig. 3B [250]) extending in a first direction;
At least one second transistor(Fig. 3B See figure below) in a second active region(Fig. 4A [220]) over the second well region(Fig. 4A [162]), wherein the second transistor(Fig. 3B See figure below) and the first transistor(Fig. 3B See figure below) share the first gate electrode(Fig. 3B [250]);
A second gate electrode and a third gate electrode(Fig. 3B [254]) on opposite edges of the first transistor(Fig. 3B See figure below) and extending in the first direction
A first isolation structure and a second isolation structure(Fig. 3B [252]) on opposite edges of the second active region(Fig. 3B [220]) and extending in the first direction,
Wherein the first isolation structure(Fig. 3B See figure below) is aligned with the second gate structure(Fig. 3B See figure below) in the first direction and separated from the second gate structure(Fig. 3B See figure below) by a dielectric material(Fig. 3B [272]), and the second isolation structure(Fig. 3B See figure below) is aligned with the third gate structure(Fig. 3B See figure below) in the first direction and separated from the third gate structure(Fig. 3B See figure below) by the dielectric material.
For clarity, the reason that the isolation structure on the NMOSFET is an isolation structure and the reason the gate structure on the PMOSFET is a gate structure is due to the fact that the isolation structure has a Vss voltage, which is typically considered zero voltage, and the gate structure has a Vdd voltage, which is a nonzero voltage(See paragraph 0037).
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Above: Fig. 3B of Liaw 2 with first, second, third gate structures, first and second transistors, first and second isolation structures denoted by examiner.
Regarding Claim 17, Liaw 2 discloses:
A semiconductor structure(Fig. 3B/4A), comprising:
A semiconductor substrate(Fig. 4A [164]); and
A cell array(Fig. 3B) comprising:
A first logic cell(Fig. 3B [201]), comprising:
At least one first transistor(Fig. 3B See figure below) in a first active region(Fig. 4A [210]) over the semiconductor substrate(Fig. 4A [164]), and comprising a first gate electrode(Fig. 3B [250]) in a first direction; and
At least one second transistor(Fig. 3B See figure below) in a second active region(Fig. 4A [220]) over the semiconductor substrate(Fig. 4A [164]), wherein the second transistor(Fig. 3B See figure below) and the first transistor(Fig. 3B See figure below) share the first gate electrode(Fig. 3B [250]); and
A second logic cell(Fig. 3B [202]), comprising:
At least one third transistor(Fig. 3B See figure below) in the first active region(Fig. 3B See figure below), and comprising a second gate electrode(Fig. 3B See figure below) extending in the first direction; and
At least one fourth transistor(Fig. 3B See figure below) in a third active region(Fig. 3B See figure below) over the semiconductor substrate(Fig. 4A [164]), wherein the third transistor(Fig. 3B See figure below) and the fourth transistor(Fig. 3B See figure below) share the second gate electrode(Fig. 3B See figure below).
A third gate electrode(Fig. 3B See figure below), a fourth gate electrode(Fig. 3B See figure below), and a fifth gate electrode(Fig. 3B See figure below) extending in the first direction; and
A first isolation structure(Fig. 3B See figure below), a second isolation structure(Fig. 3B See figure below), and a third isolation structure(Fig. 3B See figure below) extending in the first direction,
Wherein the third gate electrode(Fig. 3B See figure below) and the fourth gate electrode(Fig. 3B See figure below) are disposed on opposite sides of the first transistor(Fig. 3B See figure below), and the fourth gate electrode(Fig. 3B See figure below) and the fifth gate electrode(Fig. 3B See figure below) are disposed on opposite sides of the third transistor(Fig. 3B See figure below),
Wherein the first isolation structure(Fig. 3B See figure below) and the second isolation structure(Fig. 3B See figure below) are disposed on opposite edges of the second active region(Fig. 3B See figure below), and the second isolation structure(Fig. 3B See figure below) and the third isolation structure(Fig. 3B See figure below) are disposed on opposite edges of the third active region(Fig. 3B See figure below),
Wherein the second active region(Fig. 3B See figure below) is separated from the third active region(Fig. 3B See figure below) by the second isolation structure(Fig. 3B See figure below),
Wherein the first isolation structure(Fig. 3B See figure below), is aligned with the third gate structure(Fig. 3B See figure below) in the first direction and separated from the third gate structure(Fig. 3B See figure below) by a dielectric material(Fig. 3B [272]), the second isolation structure(Fig. 3B See figure below) is aligned with the fourth gate structure(Fig. 3B See figure below) in the first direction and separated from the fourth gate structure(Fig. 3B See figure below) by the dielectric material(Fig. 3B [272]), and the third isolation structure(Fig. 3B See figure below) is aligned with the fifth gate structure(Fig. 3B See figure below) in the first direction and separated from the fifth gate structure(Fig. 3B See figure below) by the dielectric material(Fig. 3B [272]).
For clarity, the reason that the isolation structure on the NMOSFET is an isolation structure and the reason the gate structure on the PMOSFET is a gate structure is due to the fact that the isolation structure has a Vss voltage, which is typically considered zero voltage, and the gate structure has a Vdd voltage, which is a nonzero voltage(See paragraph 0037).
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Above: Fig. 3B of Liaw 2 with various structures denoted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Liaw 2.
Regarding Claim 1, Liaw discloses:
A semiconductor structure(Fig. 4B-8) comprising:
A semiconductor substrate(Fig. 5 [500]);
A first well region(Fig. 4B [N-type well]) with a first conductivity type(N-type) over the semiconductor substrate(Fig. 5 [500]);
A second well region(Fig. 4B [P-type well]) with a second conductivity type(P-type) over the semiconductor substrate(Fig. 5 [500]), wherein the first conductivity type is different from the second conductivity type; and
A logic cell(Fig. 4B), comprising:
At least one first transistor(Fig. 4B [PMOSFET]) in a first active region(Fig. 4B [210]) over the first well region(Fig. 4B [N-type well]), and comprising a first gate electrode(Fig. 4B [250]) extending in a first direction;
At least one second transistor(Fig. 4B [NMOSFET]) in a second active region(Fig. 4B [221]) over the second well region(Fig. 4B [P-type well]), wherein the second transistor(Fig. 4B [NMOSFET]) and first transistor(Fig. 4B [PMOSFET]) share the first gate electrode(Fig. 4B [250]);
A second gate electrode(Fig. 4B [300]) and a third gate electrode(Fig. 4B [301]) on opposite sides of the first transistor(Fig. 4B [PMOSFET]) and extending in the first direction, and
A first isolation structure(Fig. 4B [310]) and a second isolation structure(Fig. 4B [310]) on opposite edges of the second active region(Fig. 4B [221]) and extending in the first direction,
Wherein the first isolation structure(Fig. 4B [310]) is aligned with the second gate structure(Fig. 4B [300]) in the first direction, and the second isolation structure(Fig. 4B [311]) is aligned with the third gate structure(Fig. 4B [301]) in the first direction.
Liaw does not teach or disclose the first isolation structure is separated from the second gate structure by a dielectric material, and the second isolation structure is separated from the third gate structure by the dielectric material.
In the same field of endeavor, Liaw 2 discloses the first isolation structure(Fig. 3B [252]) is separated from a second gate(Fig. 3B [254]) by a dielectric material(Fig. 3B [272]), and the second isolation structure(Fig. 3B [252]) is separated from a third gate structure(Fig. 3B [254]) by the dielectric material(Fig. 3B [270]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify Liaw’s device along the lines of Liaw 2. One might have been motivated to add a dielectric material between the isolation structure and the gate structure to form a gate spacer which provides electrical isolation between the gate and other components of the device. Performing this modification would have generated a predictable result in the creation of Liaw’s device with a isolating gate spacer surrounding the gate electrodes.
Regarding Claim 2, Liaw further discloses:
The second and third gate electrodes(Fig. 4B [300/301]) are shorter than the first gate electrode(Fig. 4B [250]) in the first direction.
Regarding claim 3, Liaw further discloses:
The first and second isolation structures(Fig. 4B [310/311]) are shorter than the first gate electrode(Fig. 4B [250]) in the first direction.
Regarding Claim 17, Liaw discloses:
A semiconductor structure(Fig. 4B-8), comprising:
A semiconductor substrate(Fig. 5 [500]); and
A cell array(Fig. 4B) comprising:
A first logic cell(Fig. 4B [Inverter]), comprising:
At least one first transistor(Fig. 4B [PMOSFET]) in a first active region(See Fig. 4B [210]) over the semiconductor substrate(Fig. 5 [500]), and comprising a first gate electrode(Fig. 4B [250]) in a first direction; and
At least one second transistor(Fig. 4B [NMOSFET]) in a second active region(Fig. 4B [221]) over the semiconductor substrate(Fig. 5 [500]), wherein the second transistor(Fig. 4B [NMOSFET]) and the first transistor(Fig. 4B [PMOSFET]) share the first gate electrode(Fig. 4B [250]); and
A second logic cell(Fig. 4B [NAND]), comprising:
At least one third transistor(Fig. 4B [PMOSFET-1]) in the first active region(Fig. 4B [210]), and comprising a second gate electrode(Fig. 4B [251]) extending in the first direction; and
At least one fourth transistor(Fig. 4B [NMOSFET-2]) in a third active region(Fig. 4B [222]) over the semiconductor substrate(Fig. 5 [500]), wherein the third transistor(Fig. 4B [PMOSFET-1]) and the fourth transistor(Fig. 4B [NMOSFET-2]) share the second gate electrode(Fig. 4B [251]);
A third gate electrode(Fig. 4B [300]), a fourth gate electrode(Fig. 4B [301]), and a fifth gate electrode(Fig. 4B [302]) extending in the first direction; and
A first isolation structure(Fig. 4B [310]), a second isolation structure(Fig. 4B [311]), and a third isolation structure(Fig. 4B [312]) extending in the first direction,
Wherein the third gate electrode(Fig. 4B [300]) and the fourth gate electrode(Fig. 4B [301]) are disposed on opposite sides of the first transistor(Fig. 4B [PMOSFET]), and the fourth gate electrode(Fig. 4B [301]) and the fifth gate electrode(Fig. 4B [302]) are disposed on opposite sides of the third transistor(Fig. 4B [PMOSFET-1]),
Wherein the first isolation structure(Fig. 4B [310]) and the second isolation structure(Fig. 4B [311]) are disposed on opposite edges of the second active region(Fig. 4B [221]), and the second isolation structure(Fig. 4B [311]) and the third isolation structure(Fig. 4B [312]) are disposed on opposite edges of the third active region(Fig. 4B [222]),
Wherein the second active region(Fig. 4B [221]) is separated from the third active region(Fig. 4B [222]) by the second isolation structure(Fig. 4B [311]),
Wherein the first isolation structure(Fig. 4B [310]) is aligned with the third gate structure(Fig. 4B [300]) in the first direction, the second isolation structure(Fig. 4B [311]) is aligned with the fourth gate structure(Fig. 4B [301]) in the first direction, and the third isolation structure(Fig. 4B [312]) is aligned with the fifth gate structure(Fig. 4B [302]) in the first direction.
Liaw does not teach or disclose that the isolation structures are separated from their respective gate structures by a dielectric material.
Liaw does not teach or disclose the first isolation structure is separated from the second gate structure by a dielectric material, and the second isolation structure is separated from the third gate structure by the dielectric material.
In the same field of endeavor, Liaw 2 discloses a first isolation structure(Fig. 3B [252]) is separated from a second gate(Fig. 3B [254]) by a dielectric material(Fig. 3B [272]), and the second isolation structure(Fig. 3B [252]) is separated from a third gate structure(Fig. 3B [254]) by the dielectric material(Fig. 3B [270]), and a third isolation structure(Fig. 3B [252]) is separated from a fourth gate structure(Fig. 3B [254]) by the dielectric material(Fig. 3B [270]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify Liaw’s device along the lines of Liaw 2. One might have been motivated to add a dielectric material between the isolation structure and the gate structure to form a gate spacer which provides electrical isolation between the gate and other components of the device. Performing this modification would have generated a predictable result in the creation of Liaw’s device with a isolating gate spacer surrounding the gate electrodes.
Claims 4-5, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw and Liaw 2 further in view of Yang et al.(US 8446176 B1, hereafter Yang).
Regarding Claim 4,
Liaw discloses a first power line(See paragraph 0041) wherein the second and third gate electrodes(Fig. 4B [300/301]) are electrically connected to the first power line(See paragraph 0041).
Neither Liaw nor Liaw 2 teach or disclose:
a first power line over a first well region,
a second power line over the second well region and extending in the second direction; and
an additional power line extending in the second direction and over the first active region,
wherein the first power line is electrically separated from the second power line;
wherein the second and third gate electrodes are electrically connected to the first power line through the additional power line.
In the same field of endeavor, Yang discloses:
A first power line(Fig. 9 [340]) over the first well region(See Fig. 8 [320]) and extending in the second direction, wherein the second direction is perpendicular to the first direction;
A second power line(Fig. 9 [359]) over the second well region and extending in the second direction; and
At least one additional power line(Fig. 9 [355]) extending in the second direction and over the first active region(Fig. 9 [315]),
Wherein the first power line(Fig. 9 [340]) is electrically separated from the second power line(Fig. 9 [359]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitations of claim 4 by modifying the device disclosed by Liaw and Liaw 2 further along the lines of Yang. Firstly, Yang does not explicitly teach or disclose the second and third gate electrodes electrically connected to the first power line through the additional power line. However, with consideration of the teaching given by Liaw, in that the second and third gate structures are to be connected electrically to a VDD structure, and with the arrangement respective second and third gate structures, the teachings of Yang would lead a person of ordinary skill in the art to construct a line which connects to each of the second and third gates, which is then connected to the VDD structure disclosed by Liaw. One might have been motivated to perform this modification in order to generate the necessary network of electrical connections to operate the device disclosed by Liaw as intended, as without such a network of connections Liaw’s device would not function. Performing this modification would have generated predictable results in the creation of Liaw and Liaw 2’s device with a number of additional features disclosed by Yang necessary to the operation of this device.
Regarding Claim 5,
Liaw discloses some of the features in regards to claim 4(See above rejection).
Neither Liaw or Liaw 2 teach or disclose a plurality of power lines wherein the first power line, the second power line, and the additional power line are formed in the same metal layer.
In the same field of endeavor, Yang discloses a first power line(Fig. 9 [340]), a second power line(Fig. 9 [359]), and a third power line(Fig. 9 [355]) formed in the same metal layer(See paragraph regarding Fig. 9).
It would have been obvious to further modify the device disclosed by Liaw and Liaw 2 along the lines of Yang. One might have been motivated to produce the set of lines in the same metal layer as to produce the necessary electrical connections in a single layer deposition step, rather than a plurality of such. Producing Liaw’s device in according to this modification would have generated predictable results as one of ordinary skill in the art would be presented with a limited set of ways in the prior art as to satisfy Liaw’s teaching of respective electrical connects between additional gate structures and a Vdd line. Performing this modification would have generated Liaw and Liaw 2’s device with the necessary electrical connections to practice the use of it.
Regarding Claim 18,
Liaw discloses a first power line(See paragraph 0041) wherein the third, fourth, and fifth gate electrodes(Fig. 4B [300/301]) are electrically connected to the first power line(See paragraph 0041).
Neither Liaw or Liaw 2 teach or disclose:
a first power line over a first well region,
a second power line over the second well region and extending in the second direction; and
an additional power line extending in the second direction and over the first active region,
wherein the first power line is electrically separated from the second power line;
wherein the third, fourth, and fifth gate electrodes are electrically connected to the first power line through the additional power line.
In the same field of endeavor, Yang discloses:
A first power line(Fig. 9 [340]) over the first well region(See Fig. 8 [320]) and extending in the second direction, wherein the second direction is perpendicular to the first direction;
A second power line(Fig. 9 [359]) over the second well region and extending in the second direction; and
At least one additional power line(Fig. 9 [355]) extending in the second direction and over the first active region(Fig. 9 [315]),
Wherein the first power line(Fig. 9 [340]) is electrically separated from the second power line(Fig. 9 [359]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitations of claim 4 by modifying the device disclosed by Liaw and Liaw 2 along the lines of Yang. Firstly, Yang does not explicitly teach or disclose the third, fourth, and fifth gate electrodes electrically connected to the first power line through the additional power line. However, with consideration of the teaching given by Liaw, in that the third, fourth, and fifth gate structures are to be connected electrically to a VDD structure, and with the arrangement respective third, fourth and fifth gate structures, the teachings of Yang would lead a person of ordinary skill in the art to construct a line which connects to each of the third, fourth, and fifth gates, which is then connected to the VDD structure disclosed by Liaw. In the disclosure by Liaw, there is no ambiguity for the type of feature that must be added, however, Liaw does not specify the exact structure arrangement of the respective lines that should be constructed in order to satisfy the teaching. One might have been motivated to perform this modification in order to generate the necessary network of electrical connections to operate the device disclosed by Liaw as intended, as without such a network of connections Liaw’s device would not function. Performing this modification would have generated predictable results in the creation of Liaw and Liaw 2’s device with a number of additional features disclosed by Yang necessary to the operation of this device.
Claims 6-8, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Liaw 2 and Yang, further in view of Peng et al.(US 20210265217 A1, hereafter Peng).
Regarding Claim 6,
Claim 4 is rejected under 35 U.S.C. 103(see above rejection).
Neither Liaw, Liaw 2, or Yang teach or disclose that a first and second power lines are wider than the additional power line.
In the same field of endeavor, Peng discloses a set of VDD and VSS lines, in which half of the width of each of the width of each of the VSS and VDD lines is equal to the distance between them(See Paragraph 0148, in which [834L] = 0.5 [800H]), in which an additional power line(Fig. 19B [A1]) was located. This means that the maximum width of the additional power line is equal to a width of the either of the VDD or VSS lines, giving a range of the width of the additional power line must be equal to or less than the width of either the VSS or VDD lines.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation by applying the teaching of Peng along the device disclosed by Liaw, Liaw 2, and Yang. One might have been motivated to make the VSS and Vdd lines wider than the additional power line as to accommodate a greater number of electrical connections or to reduce contact resistance, especially under a higher potential. In addition, the range given by Peng only slightly differs from the claimed range, which means the claimed range could have been reached via optimization of the power lines as disclosed by Peng. Performing this modification would have generated a predictable result in the creation of a device substantially the same as the one in claim 4, but with a specified dimension between the first and second power lines and the additional power line.
Regarding Claim 7,
Claim 4 is rejected under 35 U.S.C. 103(See above rejection).
Neither Liaw, Liaw 2 or Yang teach or disclose a plurality of signal lines extending in the second direction wherein the additional power line and the signal lines are formed in the same metal layer and arranged with a fixed pitch between the first and second power lines.
In the same field of endeavor, Peng discloses a plurality of signal lines(Fig. 19B [842/ZN]) extending in the second direction,
Wherein the additional power line(Fig. 19B [A1]) and the signal lines(Fig. 19B [842/ZN]) are formed in the same metal layer(See paragraph 0146, M0) and arranged with a fixed pitch(See paragraph 0046, “metal structures having metal lines routed in one direction have a regular pattern than reduces the risk of manufacturing or process errors”) between the first(Fig. 19B [VDD]) and second(Fig. 19B [VSS]) power lines.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Liaw along the lines of Peng. One might have been motivated to include Peng’s signal lines as it would be necessary to establish an electrical connection between each of the several source and drain structures of Liaw’s device in order to construct a logic cell of some kind using the transistors disclosed by Liaw. Performing this modification would have generated predictable results in the creation of Liaw and Liaw 2’s device with an explicitly disclosed set of signal lines for operating the cell.
Regarding Claim 8,
Claim 7 is rejected under 35 U.S.C. 103(See above rejection).
Neither Liaw, Liaw 2, nor Yang teach or disclose an additional power line separated from the first power line by one of the signal lines.
In the same field of endeavor, Peng discloses an additional power line(Fig. 19B [A1]) separated from the first power line(Fig. 19B [VDD]) by one of the signal lines(Fig. 19B [842]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Liaw along the lines of Peng. One might have been motivated to include Peng’s signal lines with a signal line between the additional power line and the VDD structure as to accommodate the source and drain structures that lie between the additional gates disclosed by Liaw and a VDD line located on either lateral side of the device disclosed by Liaw. Performing this modification would have generated a predictable result in the creation of a device as disclosed by Liaw and Liaw 2 with the plurality of signal lines and power lines as disclosed by Yang and Peng.
Regarding Claim 19,
Claim 18 is rejected under 35 U.S.C. 103(See above rejection).
Neither Liaw nor Liaw 2 teach or disclose a plurality of power lines wherein the first power line, the second power line, and the additional power line are formed in the same metal layer.
In the same field of endeavor, Yang discloses a first power line(Fig. 9 [340]), a second power line(Fig. 9 [359]), and a third power line(Fig. 9 [355]) formed in the same metal layer(See paragraph regarding Fig. 9).
It would have been obvious to further modify the device disclosed by Liaw along the lines of Yang. One might have been motivated to produce the set of lines in the same metal layer as to produce the necessary electrical connections in a single layer deposition step, rather than a plurality of such. Producing Liaw’s device in according to this modification would have generated predictable results as one of ordinary skill in the art would be presented with a limited set of ways in the prior art as to satisfy Liaw’s teaching of respective electrical connects between additional gate structures and a Vdd line. Performing this modification would have generated Liaw’s device with the necessary electrical connections to practice the use of it.
Neither Liaw, Liaw 2 nor Yang teach or disclose that a first and second power lines are wider than the additional power line.
In the same field of endeavor, Peng discloses a set of VDD and VSS lines, in which half of the width of each of the width of each of the VSS and VDD lines is equal to the distance between them(See Paragraph 0148, in which [834L] = 0.5 [800H]), in which an additional power line(Fig. 19B [A1]) was located. This means that the maximum width of the additional power line is equal to a width of the either of the VDD or VSS lines, giving a range of the width of the additional power line must be equal to or less than the width of either the VSS or VDD lines.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation by applying the teaching of Peng along the device disclosed by Liaw and Yang. One might have been motivated to make the VSS and Vdd lines wider than the additional power line as to accommodate a greater number of electrical connections or to reduce contact resistance, especially under a higher potential. In addition, the range given by Peng only slightly differs from the claimed range, which means the claimed range could have been reached via optimization of the power lines as disclosed by Peng. Performing this modification would have generated a predictable result in the creation of a device substantially the same as the one in claim 18, but with a specified dimension between the first and second power lines and the additional power line.
Regarding Claim 20,
Claim 19 is rejected under 35 U.S.C. 103(See above rejection).
Neither Liaw, Liaw 2, nor Yang teach or disclose a plurality of signal lines extending in the second direction wherein the additional power line and the signal lines are formed in the same metal layer and arranged with a fixed pitch between the first and second power lines.
In the same field of endeavor, Peng discloses a plurality of signal lines(Fig. 19B [842/ZN]) extending in the second direction,
Wherein the additional power line(Fig. 19B [A1]) and the signal lines(Fig. 19B [842/ZN]) are formed in the same metal layer(See paragraph 0146, M0) and arranged with a fixed pitch(See paragraph 0046, “metal structures having metal lines routed in one direction have a regular pattern than reduces the risk of manufacturing or process errors”) between the first(Fig. 19B [VDD]) and second(Fig. 19B [VSS]) power lines.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Liaw along the lines of Peng. One might have been motivated to include Peng’s signal lines as it would be necessary to establish an electrical connection between each of the several source and drain structures of Liaw’s device in order to construct a logic cell of some kind using the transistors disclosed by Liaw. Performing this modification would have generated predictable results in the creation of Liaw and Liaw 2’s device with an explicitly disclosed set of signal lines for operating the cell.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al.(US 20200020700 A1) discloses a memory cell with a PMOS and NMOS. Lee et al.(US 20230135653 A1) discloses a logic cell with a PMOS and an NMOS with a plurality of signal lines.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897 /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897