Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 6/12/2026 has been entered. Claim 1 is amended. Claims 8 – 10 are canceled. Claims 1 – 7, 11 – 14 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding Independent Claim 1 ( Currently Amended ), applicant amended independent claim 1, cited “ wherein the gate is disposed on the lateral wall of the active layer and is not disposed below the active layer along the normal direction. ”, which conflicts with the original specification, [0018], cited “ the orthographic projection of the gate on the insulating substrate overlaps a side of an orthographic projection of the active section on the insulating substrate ”, and [0019], cited “ the orthographic projection of the gate on the insulating substrate overlaps two sides or multiple sides of an orthographic projection of the active section on the insulating substrate ”. Besides, for the FIG. 6 in original specification, if FIG. 6 is rotated 180 degree by using BB’ as axis, then it will be “ wherein the gate is disposed on the lateral wall of the active layer and is disposed below the active layer along the normal direction. ” which conflicts with the newly added limitation. Therefore, claim 1 is rejected under 35 U.S.C. § 112(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 5 ̶ 6, 11, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Li ( Pub. No. US 20240038769 A1 ), hereinafter Li, in view of Onyema ( Pub. No. US 20200136619 A1 ), hereinafter Onyema.
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Regarding Independent Claim 1 ( Currently Amended ), Li teaches thin-film transistor (TFT) having a vertical structure ( Li, [0002], thin film transistor device into a vertical channel structure ), comprising:
an insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 );
an active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) disposed on the insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 ), wherein the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) comprises a first conductive part ( Li, [0066], first electrode 40 ), an active section ( Li, [0066], first conductive channel 60 ), and a second conductive part ( Li, [0066], second electrode 80 ) which are stacked;
a gate ( Li, FIG. 6, second gate electrode 70 ) disposed on a lateral wall of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) , and an orthographic projection of the gate ( Li, FIG. 6, second gate electrode 70 ) on the lateral wall ( Li, FIG. 6, the wall between “ second gate electrode 70 ” and “ first electrode 40 + first conductive channel 60 + second electrode 80 ” ) of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) covers the active section ( Li, [0066], first conductive channel 60 );
wherein an orthographic projection of the first conductive part ( Li, [0066], first electrode 40 ) on the insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 ) partly overlaps an orthographic projection of the second conductive part ( Li, [0066], second electrode 80 ) on the insulating substrate ( Li, FIG. 6, an orthographic projection of first electrode 40 partly overlaps an orthographic projection of second electrode 80; [0014], wherein an orthograph projection of the first electrode ( i.e. 40 ) on the substrate overlaps an orthograph projection of the first conductive channel ( i.e. 60 ) on the substrate; [0069], The first conductive channel 60 is disposed in the third through-hole and connected to the first electrode 40; [0087], wherein the second connecting electrode 81 is disposed on the first conductive channel 60, the second electrode 80 is disposed on the second connecting electrode 81 );
wherein the active section ( Li, [0066], first conductive channel 60 ) is located between the insulating substrate ( Li, [0066], substrate 10, or first insulating layer 30, or second insulating layer 50; [0074], passivating layer 300 ) and the gate ( Li, FIG. 6, second gate electrode 70, first gate electrode 20 ) along a normal direction perpendicular to a surface of the insulating substrate ( Li, [0066], substrate 10, or first insulating layer 30, or second insulating layer 50; [0074], passivating layer 300 ) on which the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) is disposed;
wherein the orthographic projection of the gate ( Li, FIG. 6, first gate electrode 20 ) on the insulating substrate ( Li, [0066], first insulating layer 30, or second insulating layer 50, or substrate 10 ) overlaps two opposite sides ( Li, FIG. 6, the orthographic projection of first gate electrode 20, is extending from the left side to the right side ) of an orthographic projection of the active section ( Li, [0066], first conductive channel 60 ) on the insulating substrate ( Li, [0066], substrate 10, or first insulating layer 30, or second insulating layer 50; [0074], passivating layer 300 ) along the normal direction.
wherein the gate ( Li, FIG. 6, second gate electrode 70, first gate electrode 20 ) is disposed on the lateral wall ( Li, FIG. 6, the wall between “ second gate electrode 70 ” and “ first electrode 40 + first conductive channel 60 + second electrode 80 ” ) of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) and is not ( Li, FIG.6, if FIG. 6 is rotated 180 degree by using substrate 10 as axis, then there will be no first gate electrode 20 below the active layer 40, 60, 80 ) disposed below the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) along the normal direction.
Li does not explicitly disclose:
a connection part connected between the opposite sides of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides and the connection part collectively form a U-shaped overlapping portion and a notched non-overlapping portion partially surrounded by the U-shaped overlapping portion.
However, Onyema teaches:
a connection part ( Onyema, FIG. 6, polysilicon gate 608 on top side of fins 602; FIG. 7B, polysilicon gate 702 on top side of fins 704 ) connected between the opposite sides ( Onyema, FIG. 6, polysilicon gate 608 on front side and back side of fins 602; FIG. 7B, polysilicon gate 702 on left side and right side of fins 704 ) of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides ( Onyema, FIG. 6, polysilicon gate 608 on front side and back side of fins 602; FIG. 7B, polysilicon gate 702 on left side and right side of fins 704 ) and the connection part ( Onyema, FIG. 6, polysilicon gate 608 on top side of fins 602; FIG. 7B, polysilicon gate 702 on top side of fins 704 ) collectively form a U-shaped ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704 ) overlapping portion and a notched ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 is not on bottom side of fins 704 ) non-overlapping portion partially surrounded by the U-shaped (Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704) overlapping portion.
Li and Onyema are both considered to be analogous to the claimed invention because they are forming field-effect transistor ( FET ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ( [0002], a thin film transistor device into a vertical channel structure ), to incorporate the teachings of Onyema ( FIG. 6 is a three dimensional view of an example FinFET; FIG. 7B is a cross sectional view of the FinFET ), to implement that “ a connection part connected between the opposite sides of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides and the connection part collectively form a U-shaped overlapping portion and a notched non-overlapping portion partially surrounded by the U-shaped overlapping portion ” as mapped above. Doing so would provide specific FinFET structure for field-effect transistor ( FET ), and therefore high speed and low power applications can be implemented.
Regarding Claim 5 ( Previously presented ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teaches:
wherein the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) comprises the first conductive part ( Li, [0066], first electrode 40 ) doped with an ion ( Li, [0067], first electrode 40 can be used as the drain electrode; which means an n-type or p-type ion is doped into drain ), and the third active layer comprises the second conductive part ( Li, [0066], second electrode 80 ) doped with the ion ( Li, [0067], second electrode 80 can be used as the source electrode; which means an n-type or p-type ion is doped into source ).
Regarding Claim 6 ( Previously presented ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teaches:
wherein the active section ( Li, [0066], first conductive channel 60 ) and the second conductive part ( Li, [0066], second electrode 80 ) have a same shape ( Li, FIG. 6, first conductive channel 60 and second electrode 80 have a same shape ).
Regarding Claim 11 ( Previously presented ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teaches: comprising:
a light-shielding layer ( Li, [0070], first gate electrode 20 can block backlight, so as to avoid an influence of the backlight on the first conductive channel 60 and reduce a leakage current of the array substrate 100 ) disposed between the insulating substrate ( Li, [0066], substrate 10 ) and the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) , wherein an orthographic projection of the light-shielding layer ( Li, [0070], first gate electrode 20 can block backlight ) on the insulating substrate ( Li, [0066], substrate 10 ) at least covers an orthographic projection of the active section ( Li, [0066], first conductive channel 60 ) on the insulating substrate ( Li, [0066], substrate 10 ), and the gate ( Li, FIG. 6, second gate electrode 70 ) is connected to the light-shielding layer ( Li, [0070], first gate electrode 20 can block backlight ) .
Regarding Claim 14 ( Original ), Li teaches an electronic device ( Li, [0001], The present application relates to a field of display technology, and particularly to an array substrate and a display panel ), comprising the TFT having the vertical structure ( Li, [0002], thin film transistor device into a vertical channel structure ) of claim 1 ( as shown in this office action, Claim Rejections - 35 USC § 102 ).
Claim 2 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Onyema, in view of Guo ( Pub. No. US 20130093000 A1 ), hereinafter Guo.
Regarding Claim 2 – 3 ( Original ), 4 ( Previously Amended ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent,
Li and Onyema fail to teach wherein a thickness of the second conductive part is greater than a thickness of the first conductive part; wherein the thickness of the second conductive part is two times greater than the thickness of the first conductive part; wherein in the normal direction perpendicular to the insulating substrate, the thickness of the second conductive part is greater than or equal to 50 nm and is less than or equal to 300 nm, and the thickness of the first conductive part is greater than or equal to 10 nm and is less than or equal to 100 nm.
Regarding claims 2 – 4, Guo teaches that the source and drain can have different thicknesses ( Guo, [0027], The n+ Si source region 14 can be doped …, and can have an exemplary thickness in a range of about 10 nm to about 200 nm … The n+ Si drain region 18 can be doped …, and can have an exemplary thickness in a range of about 10 nm to about 200 nm ), however, the reference Guo does not explicitly disclose that the source or drain thickness is greater than the drain or source thickness. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above to have source or drain thickness greater than the drain or source thickness as a design choice. Furthermore, “ [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. ” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Onyema, in view of Schuele ( Pub. No. US 20050236625 A1 ), hereinafter Schuele.
Regarding Claim 7 ( Original ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teach:
wherein there are the second conductive part ( Li, [0066], first electrode 40; [0067], first electrode 40 can be used as the drain electrode ) and the first conductive part ( Li, [0066], second electrode 80; [0067], second electrode 80 can be used as the source electrode ).
Li and Onyema fail to teach wherein a dopant concentration of the ion of the second conductive part is less than a dopant concentration of the ion of the first conductive part.
However, Schuele teaches wherein a dopant concentration of the ion of the second conductive part is less than a dopant concentration of the ion of the first conductive part ( Schuele, FIG. 1, 124, 118, 114; [0024], a lightly doped drain (LDD) 124 is formed in the channel region 118 adjacent the first source/drain region 114; [0023], A channel region 118 overlies the first gate sidewall 108, interposed between the first and second source/drain regions 114/116 ).
Li and Onyema and Schuele are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor or field-effect transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( the second conductive part and the first conductive part; FinFET ), to incorporate the teachings of Schuele ( FIG. 1, 124, 118, 114; [0024], a lightly doped drain (LDD) 124 is formed in the channel region 118 adjacent the first source/drain region 114 ), forming a dopant concentration of the ion of the drain is less than a dopant concentration of the ion of the source. Doing so would form lightly doped drain (LDD) in the channel region adjacent to the drain of vertical-channel thin film transistor, and therefore the short-channel effect of vertical-channel thin film transistor can be reduced or prevented.
Claim 12 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Qu ( Pub. No. US 20210210528 A1 ), hereinafter Qu.
Regarding Claim 12 ( Original ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teach:
wherein a thickness of the active section ( Li, [0066], first conductive channel 60 ).
Li and Onyema fail to teach wherein a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm.
However, Qu teaches wherein a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm ( Qu, FIG. 8, 13; [0084], For example, the isolating layer 13 can have a thickness in the range of 0.5 μm ~ 2.0 μm. This thickness determines a channel length. During actual practice, for example, a width of the part of the surface of the first electrode that is exposed can be configured as 0.5 μm ~ 1.5 μm ).
Li and Onyema and Qu are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor or field-effect transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( TFT having the vertical structure which has active section; FinFET ) to incorporate the teachings of Qu ( active layer can have a length in the range of 0.5 μm ~ 1.5 μm ), forming a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm. Doing so would provide specific range of thickness for the active section, and therefore the vertical type thin film transistor can be implemented accordingly.
Regarding Claim 13 ( Currently Amened ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teach:
comprising a side of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) away from the insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 );
Li and Onyema fail to teach comprising a first metal layer disposed on a side of the active layer away from the insulating substrate, wherein the first metal layer is connected to the first conductive part; wherein the first conductive part comprises a first sub-conductive part connected to the active section and a second sub-conductive part connected to the first metal layer.
However, Qu teaches comprising a first metal layer ( Qu, [0045], active layer 26 is formed at a side of the spacer layer 24, and is electrically connected to the drain electrode 14 and the source electrode 12 ) disposed on a side of the active layer away from the insulating substrate, wherein the first metal layer is connected to the first conductive part ( Qu, FIG. 1, source electrode 12 ); wherein the first conductive part comprises a first sub-conductive part ( Qu, FIG. 1, central part of source electrode 12, under the spacer layer 24 ) connected to the active section and a second sub-conductive part ( Qu, FIG. 1, right part of source electrode 12, out of the spacer layer 24 ) connected to the first metal layer.
Li and Onyema and Qu are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor or field-effect transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( a side of the active layer away from the insulating substrate; FinFET ) to incorporate the teachings of Qu ( active layer 26 is formed at a side of the spacer layer 24, and is electrically connected to the source electrode 12; central part of source electrode 12 is first sub-conductive part, right part of source electrode 12 is second sub-conductive part ), forming an orthographic projection of the first sub-conductive part on the insulating substrate overlaps an orthographic projection of the second conductive part on the insulating substrate. Doing so would provide a specific layout by using a metal via to connect drain or source electrode on top layer, to connect with drain or source electrode at the bottom layer, therefore the vertical type thin film transistor can be implemented accordingly.
Response to Arguments
Applicant's arguments filed 6/12/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding Claim 1 ( Currently Amended ): page 5, line 3 from bottom, cited “ As shown in FIGs. 5-8 of the present application, the gate 23 is disposed solely on the lateral wall of active layer 21. Active section 21B is positioned between insulating substrate 11 and gate 23 along the normal direction, i.e., the gate is at the lateral side of the channel, not below it. ”; page 7, line 1, cited “ In Li's structure, the first gate electrode 20 is always below the active channel regardless of how layers are re-equated. ”.
Examiner’s response:
First, based on FIG. 6 of application, the gate 23 is disposed not only on the wall of the active layer 21, but also on the top of active layer 21.
Second, please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ wherein the gate ( Li, FIG. 6, second gate electrode 70, first gate electrode 20 ) is disposed on the lateral wall ( Li, FIG. 6, the wall between “ second gate electrode 70 ” and “ first electrode 40 + first conductive channel 60 + second electrode 80 ” ) of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) and is not ( Li, FIG.6, if FIG. 6 is rotated 180 degree by using substrate 10 as axis, then there will be no first gate electrode 20 below the active layer 40, 60, 80 ) disposed below the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) along the normal direction. ”. In other words, “ all parts of 23 in FIG. 6 of application ” should be considered and compared with “ all parts of 70 and 20 in FIG. 6 of prior art Li ”, not “ partial part of 23 in FIG. 6 of application ” to be considered and compared with “ partial part of 70 and 20 in FIG. 6 of prior art Li ”.
Applicant’s remarks regarding Claim 1 ( Currently Amended ): page 8, line 3, cited “ (a) Different device physics and technology platforms: Onyema discloses a FinFET - a bulk-silicon CMOS device where a vertical silicon fin is formed by etching bulk silicon, and the gate wraps around three sides of the fin … ”; page 8, line 9, cited “ The present application discloses a vertical-channel TFT fabricated on an insulating substrate (e.g., glass), using thin-film semiconductor materials (e.g., oxide semiconductor, polysilicon, or amorphous silicon). These are fundamentally different device types …”.
Examiner’s response: Onyema discloses the gate wraps around three sides of the fin, is fundamentally identical device with the claim 1 limitations “ a U-shaped overlapping portion and a notched non-overlapping portion ”, as shown claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ a U-shaped ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704 ) overlapping portion and a notched ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 is not on bottom side of fins 704 ) non-overlapping portion partially surrounded by the U-shaped (Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704) overlapping portion ”.
Applicant’s remarks regarding Claim 1 ( Currently Amended ): page 8, line 7 from bottom, cited “ (b) Different functional purpose of the U-shaped gate: In the FinFET of Onyema, the three-sided gate wrapping around the fin serves to improve electrostatic control of the channel in three dimensions. In claim 1, the U-shaped overlapping portion of the gate projection on the insulating substrate serves to control the channel width of the vertical TFT and adjust the transistor current characteristics, as explicitly described in the present application (paragraphs [0050]-[0055]). ”.
Examiner’s response: As written above, the purpose of Onyema ( the three-sided gate wrapping around the fin ) is to control the channel, and claim 1 ( the U-shaped overlapping portion ) it to control the channel width; therefore, Onyema and claim 1 have the same functional purpose.
Applicant’s remarks regarding Claims 2 ( Original ) – 4 ( Previously presented ): page 9, line 6 from bottom, cited “ Moreover, the specific thickness ratio (2x or more) and the specific ranges in claims 3-4 provide concrete technical benefits in the vertical TFT context - specifically, a thicker second conductive part (source) better shields the active section from source-side fields and improves channel uniformity. ”.
Examiner’s response: The support of “ specifically, a thicker second conductive part (source) better shields the active section from source-side fields and improves channel uniformity ” could not be found in the original specification, therefore, this argument is not persuasive, and please clarify where in the specification can support this technical benefits.
Applicant’s remarks regarding Claim 7 ( Original ): page 10, line 5, cited “ The non- uniform doping in Huang - with higher doping near the drain and lower doping near the source - is specifically engineered to suppress the impact of drain electric field on the tunneling width at the tunneling junction, a feature unique to TFET operation (Huang, [0005], [0025]). ”.
Examiner’s response: This argument is persuasive. Please refer to claim 7 in Claim Rejections - 35 USC § 103 of this office action, cited “
However, Schuele teaches wherein a dopant concentration of the ion of the second conductive part is less than a dopant concentration of the ion of the first conductive part ( Schuele, FIG. 1, 124, 118, 114; [0024], a lightly doped drain (LDD) 124 is formed in the channel region 118 adjacent the first source/drain region 114; [0023], A channel region 118 overlies the first gate sidewall 108, interposed between the first and second source/drain regions 114/116 ).
Li and Onyema and Schuele are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor or field-effect transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( the second conductive part and the first conductive part; FinFET ), to incorporate the teachings of Schuele ( FIG. 1, 124, 118, 114; [0024], a lightly doped drain (LDD) 124 is formed in the channel region 118 adjacent the first source/drain region 114 ), forming a dopant concentration of the ion of the drain is less than a dopant concentration of the ion of the source. Doing so would form lightly doped drain (LDD) in the channel region adjacent to the drain of vertical-channel thin film transistor, and therefore the short-channel effect of vertical-channel thin film transistor can be reduced or prevented. ”.
Applicant’s remarks regarding Claim 12 ( Original ): page 10, line 7 from bottom, cited “ The thickness of the active layer of Qu determines the contact area with the source/drain electrodes. In claim 12, the thickness of active section 21B defines the vertical channel length of the TFT. ”.
Examiner’s response: This argument is persuasive. Please refer to claim 12 in Claim Rejections - 35 USC § 103 of this office action, cited “
However, Qu teaches wherein a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm ( Qu, FIG. 8, 13; [0084], For example, the isolating layer 13 can have a thickness in the range of 0.5 μm ~ 2.0 μm. This thickness determines a channel length. During actual practice, for example, a width of the part of the surface of the first electrode that is exposed can be configured as 0.5 μm ~ 1.5 μm ).
Li and Onyema and Qu are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor or field-effect transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( TFT having the vertical structure which has active section; FinFET ) to incorporate the teachings of Qu ( active layer can have a length in the range of 0.5 μm ~ 1.5 μm ), forming a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm. Doing so would provide specific range of thickness for the active section, and therefore the vertical type thin film transistor can be implemented accordingly. ”.
Applicant’s remarks regarding Claim 13 ( Previously presented ): page 11, line 5, cited “ The planar source electrode structure of Qu does not teach, suggest, or motivate this specific three-dimensional configuration, and the equivalence proposed by the Examiner requires importing a structural relationship from the horizontal TFT architecture of Qu into the vertical TFT architecture of claim 1 in a manner that is not taught or suggested by Qu. ”.
Examiner’s response: This argument is not persuasive. Qu teaches three-dimensional configuration ( Qu, [0083], a three-dimensional active layer ). Qu does not teach the horizontal TFT architecture, but the vertical-channel transistor ( Qu, [0045], FIG. 1 is a structural diagram illustrating a vertical type TFT ). Besides, prior arts Li and Qu still read on all limitations in claim 13, as shown in Claim Rejections - 35 USC § 103 of this office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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