Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 1/21/2026 has been entered. Claims 1, 13 are amended. Claims 8 – 10 are canceled. Claims 1 – 7, 11 – 14 remain pending in the application.
Claim Rejections - 35 USC § 112
Regarding Claim 13 ( Currently Amended ), applicant deleted “ an orthographic projection of the second sub-conductive part on the insulating substrate and the orthographic projection of the second sub-conductive part on the insulating substrate have no overlap region ”, therefore, the rejection under 35 U.S.C. § 112(b) is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 5 ̶ 6, 11, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Li ( Pub. No. US 20240038769 A1 ), hereinafter Li, in view of Onyema ( Pub. No. US 20200136619 A1 ), hereinafter Onyema.
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Regarding Independent Claim 1 ( Currently Amended ), Li teaches thin-film transistor (TFT) having a vertical structure ( Li, [0002], thin film transistor device into a vertical channel structure ), comprising:
an insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 );
an active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) disposed on the insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 ), wherein the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) comprises a first conductive part ( Li, [0066], first electrode 40 ), an active section ( Li, [0066], first conductive channel 60 ), and a second conductive part ( Li, [0066], second electrode 80 ) which are stacked;
a gate ( Li, FIG. 6, second gate electrode 70 ) disposed on a lateral wall of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) , and an orthographic projection of the gate ( Li, FIG. 6, second gate electrode 70 ) on the lateral wall ( Li, FIG. 6, the wall between “ second gate electrode 70 ” and “ first electrode 40 + first conductive channel 60 + second electrode 80 ” ) of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) covers the active section ( Li, [0066], first conductive channel 60 );
wherein an orthographic projection of the first conductive part ( Li, [0066], first electrode 40 ) on the insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 ) partly overlaps an orthographic projection of the second conductive part ( Li, [0066], second electrode 80 ) on the insulating substrate ( Li, FIG. 6, an orthographic projection of first electrode 40 partly overlaps an orthographic projection of second electrode 80; [0014], wherein an orthograph projection of the first electrode ( i.e. 40 ) on the substrate overlaps an orthograph projection of the first conductive channel ( i.e. 60 ) on the substrate; [0069], The first conductive channel 60 is disposed in the third through-hole and connected to the first electrode 40; [0087], wherein the second connecting electrode 81 is disposed on the first conductive channel 60, the second electrode 80 is disposed on the second connecting electrode 81 );
wherein the active section ( Li, [0066], first conductive channel 60 ) is located between the insulating substrate ( Li, [0066], substrate 10, or first insulating layer 30, or second insulating layer 50; [0074], passivating layer 300 ) and the gate ( Li, FIG. 6, second gate electrode 70, first gate electrode 20 ) along a normal direction perpendicular to a surface of the insulating substrate ( Li, [0066], substrate 10, or first insulating layer 30, or second insulating layer 50; [0074], passivating layer 300 ) on which the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) is disposed;
wherein the orthographic projection of the gate ( Li, FIG. 6, first gate electrode 20 ) on the insulating substrate ( Li, [0066], first insulating layer 30, or second insulating layer 50, or substrate 10 ) overlaps two opposite sides ( Li, FIG. 6, the orthographic projection of first gate electrode 20, is extending from the left side to the right side ) of an orthographic projection of the active section ( Li, [0066], first conductive channel 60 ) on the insulating substrate ( Li, [0066], substrate 10, or first insulating layer 30, or second insulating layer 50; [0074], passivating layer 300 ) along the normal direction.
Li does not explicitly disclose:
a connection part connected between the opposite sides of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides and the connection part collectively form a U-shaped overlapping portion and a notched non-overlapping portion partially surrounded by the U-shaped overlapping portion.
However, Onyema teaches:
a connection part ( Onyema, FIG. 6, polysilicon gate 608 on top side of fins 602; FIG. 7B, polysilicon gate 702 on top side of fins 704 ) connected between the opposite sides ( Onyema, FIG. 6, polysilicon gate 608 on front side and back side of fins 602; FIG. 7B, polysilicon gate 702 on left side and right side of fins 704 ) of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides ( Onyema, FIG. 6, polysilicon gate 608 on front side and back side of fins 602; FIG. 7B, polysilicon gate 702 on left side and right side of fins 704 ) and the connection part ( Onyema, FIG. 6, polysilicon gate 608 on top side of fins 602; FIG. 7B, polysilicon gate 702 on top side of fins 704 ) collectively form a U-shaped ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704 ) overlapping portion and a notched ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 is not on bottom side of fins 704 ) non-overlapping portion partially surrounded by the U-shaped (Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704) overlapping portion.
Li and Onyema are both considered to be analogous to the claimed invention because they are forming thin-film transistor (TFT). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ( [0002], a thin film transistor device into a vertical channel structure ), to incorporate the teachings of Onyema ( FIG. 6 is a three dimensional view of an example FinFET; FIG. 7B is a cross sectional view of the FinFET ), to implement that “ a connection part connected between the opposite sides of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides and the connection part collectively form a U-shaped overlapping portion and a notched non-overlapping portion partially surrounded by the U-shaped overlapping portion ” as mapped above. Doing so would provide specific FinFET structure for thin-film transistor (TFT), and therefore high performance and low power applications can be implemented.
Regarding Claim 5 ( Previously presented ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teaches:
wherein the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) comprises the first conductive part ( Li, [0066], first electrode 40 ) doped with an ion ( Li, [0067], first electrode 40 can be used as the drain electrode; which means an n-type or p-type ion is doped into drain ), and the third active layer comprises the second conductive part ( Li, [0066], second electrode 80 ) doped with the ion ( Li, [0067], second electrode 80 can be used as the source electrode; which means an n-type or p-type ion is doped into source ).
Regarding Claim 6 ( Previously presented ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teaches:
wherein the active section ( Li, [0066], first conductive channel 60 ) and the second conductive part ( Li, [0066], second electrode 80 ) have a same shape ( Li, FIG. 6, first conductive channel 60 and second electrode 80 have a same shape ).
Regarding Claim 11 ( Previously presented ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teaches: comprising:
a light-shielding layer ( Li, [0070], first gate electrode 20 can block backlight, so as to avoid an influence of the backlight on the first conductive channel 60 and reduce a leakage current of the array substrate 100 ) disposed between the insulating substrate ( Li, [0066], substrate 10 ) and the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) , wherein an orthographic projection of the light-shielding layer ( Li, [0070], first gate electrode 20 can block backlight ) on the insulating substrate ( Li, [0066], substrate 10 ) at least covers an orthographic projection of the active section ( Li, [0066], first conductive channel 60 ) on the insulating substrate ( Li, [0066], substrate 10 ), and the gate ( Li, FIG. 6, second gate electrode 70 ) is connected to the light-shielding layer ( Li, [0070], first gate electrode 20 can block backlight ) .
Regarding Claim 14 ( Original ), Li teaches an electronic device ( Li, [0001], The present application relates to a field of display technology, and particularly to an array substrate and a display panel ), comprising the TFT having the vertical structure ( Li, [0002], thin film transistor device into a vertical channel structure ) of claim 1 ( as shown in this office action, Claim Rejections - 35 USC § 102 ).
Claim 2 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Onyema, in view of Guo ( Pub. No. US 20130093000 A1 ), hereinafter Guo.
Regarding Claim 2 – 3 ( Original ), 4 ( Previously Amended ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent,
Li and Onyema fail to teach wherein a thickness of the second conductive part is greater than a thickness of the first conductive part; wherein the thickness of the second conductive part is two times greater than the thickness of the first conductive part; wherein in the normal direction perpendicular to the insulating substrate, the thickness of the second conductive part is greater than or equal to 50 nm and is less than or equal to 300 nm, and the thickness of the first conductive part is greater than or equal to 10 nm and is less than or equal to 100 nm.
Regarding claims 2 – 4, Guo teaches that the source and drain can have different thicknesses ( Guo, [0027], The n+ Si source region 14 can be doped …, and can have an exemplary thickness in a range of about 10 nm to about 200 nm … The n+ Si drain region 18 can be doped …, and can have an exemplary thickness in a range of about 10 nm to about 200 nm ), however, the reference Guo does not explicitly disclose that the source thickness is greater than the drain thickness. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above to have source thickness greater than the drain thickness as a design choice, or to prevent short channel effects. Furthermore, “ [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. ” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Onyema, in view of Huang ( Pub. No. US 20160020306 A1 ), hereinafter Huang.
Regarding Claim 7 ( Original ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teach:
wherein there are the second conductive part ( Li, [0066], second electrode 80; [0067], second electrode 80 can be used as the source electrode ) and the first conductive part ( Li, [0066], first electrode 40; [0067], first electrode 40 can be used as the drain electrode ).
Li and Onyema fail to teach wherein a dopant concentration of the ion of the second conductive part is less than a dopant concentration of the ion of the first conductive part.
However, Huang teaches wherein a dopant concentration of the ion of the second conductive part is less than a dopant concentration of the ion of the first conductive part ( Huang, [0005], the doping concentration in the channel near the drain region is higher, which is generally higher than 1E14 cm−3, while the doping concentration in the channel near the source region is lower, which is generally 2 – 3 orders of magnitude lower than the doping concentration in the channel near the drain region ).
Li and Onyema and Huang are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( the second conductive part and the first conductive part; FinFET ), to incorporate the teachings of Huang ( the doping concentration in the channel near the drain region is higher, which is generally higher than 1E14 cm−3, the doping concentration in the channel near the source region is lower, which is generally 2 – 3 orders of magnitude lower than the doping concentration in the channel near the drain region ), forming a dopant concentration of the ion of the second conductive part is less than a dopant concentration of the ion of the first conductive part. Doing so would provide the specific doping concentration for drain and source, and therefore the vertical type thin film transistor can be implemented accordingly.
Claim 12 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Qu ( Pub. No. US 20210210528 A1 ), hereinafter Qu.
Regarding Claim 12 ( Original ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teach:
wherein a thickness of the active section ( Li, [0066], first conductive channel 60 ).
Li and Onyema fail to teach wherein a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm.
However, Qu teaches wherein a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm ( Qu, [0086], For example, the active layer can have a thickness in the range of 2000 Å – 8000 Å ).
Li and Onyema and Qu are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( TFT having the vertical structure which has active section; FinFET ) to incorporate the teachings of Qu ( active layer can have a thickness in the range of 2000 Å – 8000 Å ), forming a thickness of the active section is greater than or equal to 0.1 µm and is less than or equal to 1 µm. Doing so would provide specific range of thickness for the active section, and therefore the vertical type thin film transistor can be implemented accordingly.
Regarding Claim 13 ( Currently Amened ), Li and Onyema teach the TFT having the vertical structure as claimed in claim 1, on which this claim is dependent, Li further teach:
comprising a side of the active layer ( Li, [0066], first electrode 40, first conductive channel 60, second electrode 80 ) away from the insulating substrate ( Li, [0066], first insulating layer 30, second insulating layer 50 );
Li and Onyema fail to teach comprising a first metal layer disposed on a side of the active layer away from the insulating substrate, wherein the first metal layer is connected to the first conductive part; wherein the first conductive part comprises a first sub-conductive part connected to the active section and a second sub-conductive part connected to the first metal layer.
However, Qu teaches comprising a first metal layer ( Qu, [0045], active layer 26 is formed at a side of the spacer layer 24, and is electrically connected to the drain electrode 14 and the source electrode 12 ) disposed on a side of the active layer away from the insulating substrate, wherein the first metal layer is connected to the first conductive part ( Qu, FIG. 1, source electrode 12 ); wherein the first conductive part comprises a first sub-conductive part ( Qu, FIG. 1, central part of source electrode 12, under the spacer layer 24 ) connected to the active section and a second sub-conductive part ( Qu, FIG. 1, right part of source electrode 12, out of the spacer layer 24 ) connected to the first metal layer.
Li and Onyema and Qu are all considered to be analogous to the claimed invention because they are in the same field of thin film transistor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li and Onyema ( a side of the active layer away from the insulating substrate; FinFET ) to incorporate the teachings of Qu ( active layer 26 is formed at a side of the spacer layer 24, and is electrically connected to the source electrode 12; central part of source electrode 12 is first sub-conductive part, right part of source electrode 12 is second sub-conductive part ), forming an orthographic projection of the first sub-conductive part on the insulating substrate overlaps an orthographic projection of the second conductive part on the insulating substrate. Doing so would provide a specific layout by using a metal via to connect drain or source electrode on top layer, to connect with drain or source electrode at the bottom layer, therefore the vertical type thin film transistor can be implemented accordingly.
Response to Arguments
Applicant's arguments filed 1/21/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding Claim 1 ( Currently Amended ): page 8, line 10, cited “ Moreover, the active section 60 of Li is NOT located between the gate 20 and the insulating substrate 10 along the normal direction perpendicular to the surface of the insulating substrate 10 on which the active layer 60 is disposed. Instead, the gate 20 of Li is sandwiched between the active section 60 and the insulating substrate 10. ”.
Examiner’s response: First, if prior art Li's FIG. 6 passivating layer 300 is mapped to be the applicant's FIG. 5 insulating substrate 11, then prior art Li's first conductive channel 60 is located between first gate electrode 20 and substrate. Second, since the present application is thin-film transistor having vertical structure, it is reasonable to map second insulating layer 50 (right portion) in prior art Li's FIG. 6 as insulating substrate, therefore active section 60 is located between second gate electrode 70 and insulating substrate. Third, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create “ first gate electrode 20 is placed on the surface of passivating layer 300 in Li's FIG. 6 ”, by “ duplicating first gate electrode 20 and place it on the surface of passivating layer 300 ”, because for a vertical transistor, second gate electrode 70 provides the major function of tuning the channel, and first gate electrode 20 is used to connect second gate electrode 70 from neighboring layers, which can be the neighboring layer at the bottom or from the top, since this is within the skill level of one in the art.
Applicant’s remarks regarding Claim 1 ( Currently Amended ): page 8, line 14, cited “ Also, Applicant respectfully submits that Li (See FIG. 6) fails to disclose a connection part connected between the opposite sides of the orthographic projection of the active section on the insulating substrate and the opposite sides and the connection part collectively forming a U- shaped overlapping portion and a notched non-overlapping portion partially surrounded by the U-shaped overlapping portion as claimed in claim 1 of the present application. It is clear from FIG. 6 of Li that no opposite sides are formed on the orthographic projection of the active section 60 and therefore no connection part is formed between the opposite sides of the orthographic projection of the active section 60. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ However, Onyema teaches:
a connection part ( Onyema, FIG. 6, polysilicon gate 608 on top side of fins 602; FIG. 7B, polysilicon gate 702 on top side of fins 704 ) connected between the opposite sides ( Onyema, FIG. 6, polysilicon gate 608 on front side and back side of fins 602; FIG. 7B, polysilicon gate 702 on left side and right side of fins 704 ) of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides ( Onyema, FIG. 6, polysilicon gate 608 on front side and back side of fins 602; FIG. 7B, polysilicon gate 702 on left side and right side of fins 704 ) and the connection part ( Onyema, FIG. 6, polysilicon gate 608 on top side of fins 602; FIG. 7B, polysilicon gate 702 on top side of fins 704 ) collectively form a U-shaped ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704 ) overlapping portion and a notched ( Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 is not on bottom side of fins 704 ) non-overlapping portion partially surrounded by the U-shaped (Onyema, FIG. 6, FIG. 7B, polysilicon gate 702 on top side / left side / right side of fins 704) overlapping portion.
Li and Onyema are both considered to be analogous to the claimed invention because they are forming thin-film transistor (TFT). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li ( [0002], a thin film transistor device into a vertical channel structure ), to incorporate the teachings of Onyema ( FIG. 6 is a three dimensional view of an example FinFET; FIG. 7B is a cross sectional view of the FinFET ), to implement that “ a connection part connected between the opposite sides of the orthographic projection of the active section on the insulating substrate along the normal direction, and the opposite sides and the connection part collectively form a U-shaped overlapping portion and a notched non-overlapping portion partially surrounded by the U-shaped overlapping portion ” as mapped above. Doing so would provide specific FinFET structure for thin-film transistor (TFT), and therefore high performance and low power applications can be implemented. ”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817