Prosecution Insights
Last updated: August 17, 2026
Application No. 18/050,989

DISPLAY APPARATUS

Final Rejection §103
Filed
Oct 29, 2022
Priority
Nov 30, 2021 — RE 10-2021-0169525
Examiner
NETTLES, CORALIE ANN
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
4 (Final)
69%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
24 granted / 35 resolved
+0.6% vs TC avg
Strong +33% interview lift
Without
With
+32.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
50 currently pending
Career history
87
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
61.8%
+21.8% vs TC avg
§102
20.2%
-19.8% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This Office Action is in response to Applicant's amendments filed June 27, 2026. Claims 1 and 11 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-4, 6-7, 9-14, 16-17, and 19-23 are pending. Response to Arguments Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-7, 9, 11-14, 16-17, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 20220115473 A1) herein after “Han” in view of Kim et al. (US 20230061355 A1) herein after “Kim” and Sung et al. (US 10541380 B1) herein after “Sung”. Regarding claim 1, Figs. 1 and 3 of Han disclose a display apparatus (Fig. 1, display mother plate 100, ¶ [0004]) comprising: a substrate (Fig. 3, substrate 10, ¶ [0077]) including a display area (Fig. 3, display region 310, ¶ [0004]), a cutting region (Fig. 3, inner cutting region 420, ¶ [0075]), and a non-display area (Fig. 3, peripheral circuit region 320, peripheral region 330, ¶ [0075]) between the display area (310) and the cutting region (420); a light-emitting element (Fig. 3, organic light emitting layer 25, ¶ [0076]) disposed on a plurality of pixels in the display area (310); one or more cut-out parts (Fig. 3, multiple partition posts 203, ¶ [0100]), a first dam (Fig. 3, first dam foundation 201, ¶ [0100]) and a second dam (Fig. 3, second dam foundation 202, ¶ [0100]) disposed in the non-display area (320, 330); a plurality of insulating films (Fig. 3, first insulating layer 11, second insulating layer 13, third insulating layer 15, fourth insulating layer 16, ¶ [0077]) disposed on the substrate (10) and disposed under the light-emitting element (25), the cut-out parts (203), and the first dam (201) and the second dam (202); a plurality of transistors (Fig. 3, first transistor 101, second transistor 102, ¶ [0076]) between the plurality of insulating films (11, 13, 15, 16) and the light-emitting element (25); a planarization layer (Fig. 3, first flat layer 20, second flat layer 21, ¶ [0076]) between the plurality of transistors (101, 102) and the light-emitting element (25); a crack prevention structure (Fig. 3, crack dam 33, ¶ [0077]) disposed between the cutting region (420) and at least one of the first dam (201) and the second dam (202), wherein one or more lower structure parts (portion of 33 between the insulating layers) of the crack prevention structure (33) are disposed in an area in which at least a portion of the plurality of insulating films (11, 13, 15, 16) is removed, wherein the material directly contacts side surfaces of the plurality of insulating films (11, 13, 15, 16) exposed by the removal of the at least a portion of the plurality of insulating films (11, 13, 15, 16), wherein the one or more cut-out parts (203) comprise a first cut-out part (portion of 203 left of gap 34), and a second cut-out part (portion of 203 right of gap 34), and the first cut-out part (portion of 203 left of gap 34) and the second cut-out part (portion of 203 right of gap 34) each comprise a plurality of cut-out structures. Han fails to disclose that the cutting region is for a camera hole; the crack prevention structure is formed of an organic material identical to that of the planarization layer, and wherein the first cut-out part is disposed between the first dam and the camera hole, and the second cut-out part is disposed between the first dam and the second dam, the second dam being disposed adjacent to the display area. In the similar field of endeavor of display devices, Figs. 5-6 of Kim discloses that the cutting region is for a camera hole (Fig. 5, opening 10H, ¶ [0068]) (“the opening area OA is cut along a cutting line CL by using a method such as laser cutting, the display panel 10 may include the opening 10H”, ¶ [0221], “The opening area OA may be a component area (e.g., a sensor area, a camera area”, ¶ [0074]); and wherein the first cut-out part (Fig. 6, third portion 230c, ¶ [0161]) disposed between the first dam (Fig. 6, second partition PW2, ¶ [0103]) and the camera hole (10H), and a second cut-out part (230c) disposed between the first dam (PW2) and the second dam (Fig. 6, first partition PW1, ¶ [0103]), the second dam (PW1) being disposed adjacent to the display area (Fig. 6, display area DA, ¶ [0057]) It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the camera hole and cut-out parts as disclosed by Kim, to provide additional functionality and prevent damage (see Kim, ¶ [0075] and [0157]). Kim fails to disclose the crack prevention structure is formed of an organic material identical to that of the planarization layer. In the similar field of endeavor of display devices, Fig. 21 of Sung discloses the crack prevention structure (Fig. 21, first to fourth grooves G1-G4, col. 10, lines 18-19 and col. 22, lines 13-14) is formed of an organic material (Fig. 21, planarization layer 610, col. 7, line 26) identical to that of the planarization layer (Fig. 21, organic insulating layer 209, col. 12, line 13) (Sung discloses that layer 610 can be a polymer-based material, such as polyimide, col. 42, lines 39-41. The planarization film is organic insulating layer 209, which is also described as polyimide, col. 12, line 23). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the materials as disclosed by Sung, to obtain the desired transparency properties (see Sung, col. 42, lines 41-42) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07). Regarding claim 2, Han, Kim and Sung together disclose the display apparatus of claim 1 as applied above, and Fig. 3 of Han further discloses wherein an upper structure part (portion of 33 above the insulating layers) of the crack prevention structure (33) is disposed on the one or more lower structure parts (portion of 33 between the insulating layers) of the crack prevention structure (33). Regarding claim 3, Han, Kim and Sung together disclose the display apparatus of claim 2 as applied above, and Fig. 3 of Han further discloses wherein the plurality of insulating films (11, 13, 15, 16) comprise a lower buffer layer (Fig. 3, second insulating layer 13, ¶ [0077]). Han and Kim fail to disclose wherein the plurality of insulating films comprise a multi-buffer layer. In the similar field of endeavor of display devices, Fig. 21 of Sung discloses wherein the plurality of insulating films (Fig. 21, second inorganic layer 104, buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, col. 16, lines 46-47 and 61-62) comprise a multi-buffer layer (Fig. 21, “the second inorganic layer 104, which has a multi-layered structure”, col. 27, lines 1-2). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the materials as disclosed by Sung, to protect the device from damage (see Sung, col. 11, lines 6-10) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07). Regarding claim 4, Han, Kim and Sung together disclose the display apparatus of claim 3 as applied above, and Fig. 3 of Han further discloses wherein the area in which at least a portion of the plurality of insulating films (11, 13, 15, 16) is removed corresponds to a region in the non-display area (320, 330) from which the multi-buffer layer (102) and the lower buffer layer (13) are removed. Regarding claim 6, Han, Kim and Sung together disclose the display apparatus of claim 2 as applied above, and Fig. 3 of Han further discloses wherein the plurality of insulating films (11, 13, 15, 16) comprise a gate insulating film (Fig. 3, third insulating layer 15, ¶ [0076]) and an interlayer insulating film (Fig. 3, fourth insulating layer 16, ¶ [0076]) (“third insulating layer are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD)”, ¶ [0115]). Regarding claim 7, Han, Kim and Sung together disclose the display apparatus of claim 6 as applied above, and Fig. 3 of Han further discloses wherein the area in which at least a portion of the plurality of insulating films (11, 13, 15, 16) is removed corresponds to a region in the non-display area (320, 330) from which the gate insulating film (15) and the interlayer insulating film (16) are removed. Regarding claim 9, Han, Kim and Sung together disclose the display apparatus of claim 1 as applied above, but Han and Kim fail to disclose wherein the crack prevention structure is disposed in the first cut-out part. In the similar field of endeavor of display devices, Fig. 21 of Sung discloses wherein the crack prevention structure (G2-G4) is disposed in the first cut-out part (Fig. 21, between dam 500 and opening 10H). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the arrangement as disclosed by Sung, to protect the device from damage (see Sung, col. 19, lines 54-56). Regarding claim 11, Figs. 1 and 3 of Han disclose a display apparatus (100) comprising: a substrate (10) comprising a non-display area (320, 330) disposed between a opening (420) and a display area (310); a plurality of inorganic insulating films (11, 13, 15, 16) disposed in the display area (310) and the non-display area (320, 330) (“all of the above insulating layers are inorganic insulating layers”, ¶ [0077]); an organic light-emitting stack (Fig. 3, “organic light emitting layer 25”, ¶ [0101]) disposed on the plurality of inorganic insulating films (11, 13, 15, 16) to correspond to the display area (310); a plurality of transistors (101, 102) between the plurality of inorganic insulating films (11, 13, 15, 16) and the organic light-emitting stack (25); a planarization layer (20, 21) between the plurality of transistors (101, 102) and the organic light-emitting stack (25); one or more cut-out parts (203), a first dam (201) and a second dam (202) disposed on the plurality of inorganic insulating films (11, 13, 15, 16) to correspond to the non-display area (320, 330); and wherein one or more lower structure parts (portion of 33 between the insulating layers) of the crack prevention structure (33) are disposed in an area in which at least a portion of the plurality of inorganic insulating films (11, 13, 15, 16) is removed, wherein the material directly contacts side surfaces of the plurality of insulating films (11, 13, 15, 16) exposed by the removal of the at least a portion of the plurality of insulating films (11, 13, 15, 16), the first cut-out part (portion of 203 left of gap 34) and the second cut-out part (portion of 203 right of gap 34) each comprise a plurality of cut-out structures. Han fails to disclose that the cutting region is for a camera hole; a crack prevention structure disposed in the one or more cut out parts; the crack prevention structure is formed of an organic material identical to that of the planarization layer, and wherein the first cut-out part is disposed between the first dam and the camera hole, and the second cut-out part is disposed between the first dam and the second dam, the second dam being disposed adjacent to the display area. In the similar field of endeavor of display devices, Figs. 5-6 of Kim discloses that the cutting region is for a camera hole (Fig. 5, opening 10H, ¶ [0068]) (“the opening area OA is cut along a cutting line CL by using a method such as laser cutting, the display panel 10 may include the opening 10H”, ¶ [0221], “The opening area OA may be a component area (e.g., a sensor area, a camera area”, ¶ [0074]); a crack prevention structure (Fig. 6, openings 222oh1, 222oh2, and 222oh3, ¶ [0165]) disposed in the one or more cut out parts (230C); and wherein the first cut-out part (Fig. 6, third portion 230c, ¶ [0161]) disposed between the first dam (Fig. 6, second partition PW2, ¶ [0103]) and the camera hole (10H), and a second cut-out part (230c) disposed between the first dam (PW2) and the second dam (Fig. 6, first partition PW1, ¶ [0103]), the second dam (PW1) being disposed adjacent to the display area (Fig. 6, display area DA, ¶ [0057]) It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the camera hole and cut-out parts as disclosed by Kim, to provide additional functionality and prevent damage (see Kim, ¶ [0075] and [0157]). Kim fails to disclose the crack prevention structure is formed of an organic material identical to that of the planarization layer. In the similar field of endeavor of display devices, Fig. 21 of Sung discloses the crack prevention structure (Fig. 21, first to fourth grooves G1-G4, col. 10, lines 18-19 and col. 22, lines 13-14) is formed of an organic material (Fig. 21, planarization layer 610, col. 7, line 26) identical to that of the planarization layer (Fig. 21, organic insulating layer 209, col. 12, line 13) (Sung discloses that layer 610 can be a polymer-based material, such as polyimide, col. 42, lines 39-41. The planarization film is organic insulating layer 209, which is also described as polyimide, col. 12, line 23). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the materials as disclosed by Sung, to obtain the desired transparency properties (see Sung,col. 42, lines 41-42) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07). Regarding claim 12, Han, Kim and Sung together disclose the display apparatus of claim 11 as applied above, and Fig. 3 of Han further discloses wherein an upper structure part (portion of 33 above the insulating layers) of the crack prevention structure (33) is disposed on the one or more lower structure parts (portion of 33 between the insulating layers) of the crack prevention structure (33). Regarding claim 13, Han, Kim and Sung together disclose the display apparatus of claim 12 as applied above, and Fig. 3 of Han further discloses wherein the plurality of inorganic insulating films (11, 13, 15, 16) comprise a lower buffer layer (Fig. 3, second insulating layer 13, ¶ [0077]). Han and Kim fail to disclose wherein the plurality of inorganic insulating films comprise a multi-buffer layer. In the similar field of endeavor of display devices, Fig. 21 of Sung discloses wherein the plurality of inorganic insulating films (Fig. 21, second inorganic layer 104, buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, col. 16, lines 46-47 and 61-62) comprise a multi-buffer layer (Fig. 21, “the second inorganic layer 104, which has a multi-layered structure”, col. 27, lines 1-2). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the materials as disclosed by Sung, to protect the device from damage (see Sung, col. 11, lines 6-10) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07). Regarding claim 14, Han, Kim and Sung together disclose the display apparatus of claim 13 as applied above, and Fig. 3 of Han further discloses wherein the area in which at least a portion of the plurality of inorganic insulating films (11, 13, 15, 16) is removed corresponds to a region in the non-display area (320, 330) from which the multi-buffer layer (102) and the lower buffer layer (13) are removed. Regarding claim 16, Han, Kim and Sung together disclose the display apparatus of claim 12 as applied above, and Fig. 3 of Han further discloses wherein the plurality of inorganic insulating films (11, 13, 15, 16) comprise a gate insulating film (Fig. 3, third insulating layer 15, ¶ [0076]) and an interlayer insulating film (Fig. 3, fourth insulating layer 16, ¶ [0076]) (“third insulating layer are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD)”, ¶ [0115]). Regarding claim 17, Han, Kim and Sung together disclose the display apparatus of claim 16 as applied above, and Fig. 3 of Han further discloses wherein the area in which at least a portion of the plurality of inorganic insulating films (11, 13, 15, 16) is removed corresponds to a region in the non-display area (320, 330) from which the gate insulating film (15) and the interlayer insulating film (16) are removed. Regarding claim 19, Han, Kim and Sung together disclose the display apparatus of claim 11 as applied above, but Han and Kim fail to disclose wherein the crack prevention structure is disposed in the first cut-out part. In the similar field of endeavor of display devices, Fig. 21 of Sung discloses wherein the crack prevention structure (G2-G4) is disposed in the first cut-out part (Fig. 21, between dam 500 and opening 10H). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Han with the arrangement as disclosed by Sung, to protect the device from damage (see Sung, col. 19, lines 54-56). Regarding claim 20, Han, Kim and Sung together disclose the display apparatus of claim 1 as applied above, but Han and Sung fail to disclose wherein the plurality of transistors includes a first transistor and a second transistor, and the second transistor is disposed on a gate electrode of the first transistor. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the plurality of transistors (Fig. 6, first transistor T1 and the third transistor T3, ¶ [0125]) includes a first transistor (T1) and a second transistor (T3), and the second transistor (T3) is disposed on a gate electrode (Fig. 6, first gate electrode GE1, ¶ [0112]) of the first transistor (T1). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Regarding claim 21, Han, Kim and Sung together disclose the display apparatus of claim 20 as applied above, but Han and Sung fail to disclose wherein the plurality of insulating films includes a lower interlayer insulating film disposed between the gate electrode of the first transistor and the second transistor. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the plurality of insulating films (Fig. 6, buffer layer 201, first gate insulating layer 203, first interlayer insulating layer 205, second interlayer insulating layer 207, second gate insulating layer 209, ¶ [0110-0122]) includes a lower interlayer insulating film (Fig. 6, interlayer insulating layer 207, ¶ [0118]) disposed between the gate electrode (GE1) of the first transistor (T1) and the second transistor (T3). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Regarding claim 22, Han, Kim and Sung together disclose the display apparatus of claim 20 as applied above, but Han and Sung fail to disclose wherein the planarization layer includes a first planarization layer disposed on the plurality of transistors, and a second planarization layer disposed on the first planarization layer, and a connection electrode is disposed on the first planarization layer between the first planarization layer and the second planarization layer. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the planarization layer includes a first planarization layer (Fig. 6, interlayer insulating layer 210, ¶ [0123]) disposed on the plurality of transistors (T1, T3), and a second planarization layer (Fig. 6, organic insulating layer 211, ¶ [0127]) disposed on the first planarization layer (210), and a connection electrode (Fig. 6, connection line 166, ¶ [0086]) is disposed on the first planarization layer (210) between the first planarization layer (210) and the second planarization layer (211). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Regarding claim 23, Han, Kim and Sung together disclose the display apparatus of claim 1 as applied above, and Fig. 3 of Han further discloses wherein the planarization layer (20, 21) includes a first planarization layer (Fig. 3, first flat layer 20, ¶ [0075]) disposed on the plurality of transistors (101, 102), and a second planarization layer (Fig. 3, second flat layer 21, ¶ [0075]) disposed on the first planarization layer (20), and a connection electrode (Fig. 3, first connection electrode 106, ¶ [0076]) is disposed on the first planarization layer (20) between the first planarization layer (20) and the second planarization layer (21). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Han (US 20220115473 A1), Kim (US 20230061355 A1) and Sung (US 10541380 B1) in view of Seo et al. (US 20190334120 A1) herein after “Seo”. Regarding claim 10, Han, Kim and Sung together disclose the display apparatus of claim 1 as applied above, but the combination fails to disclose wherein the crack prevention structure is disposed in the second cut-out part. In the similar field of endeavor of display panels, Fig.9B of Seo discloses wherein the crack prevention structure (Fig. 9B, “the first blocking groove BR1-F is filled with the organic layer 33-F”, ¶ [0157]) is disposed in the second cut-out part (BR1-F). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung to include the crack prevention structure as disclosed by Seo, to increase crack resistance (see Seo, ¶ [0157]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 11:30am-7pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.A.N./ Examiner, Art Unit 2893 /YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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Prosecution Timeline

Show 1 earlier event
Apr 17, 2025
Non-Final Rejection mailed — §103
Jul 17, 2025
Response Filed
Aug 20, 2025
Final Rejection mailed — §103
Nov 20, 2025
Request for Continued Examination
Nov 25, 2025
Response after Non-Final Action
Mar 19, 2026
Non-Final Rejection mailed — §103
Jun 22, 2026
Response Filed
Jul 28, 2026
Final Rejection mailed — §103 (current)

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