Prosecution Insights
Last updated: April 19, 2026
Application No. 18/050,989

DISPLAY APPARATUS

Non-Final OA §103
Filed
Oct 29, 2022
Examiner
NETTLES, CORALIE ANN
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
3 (Non-Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
3y 7m
To Grant
96%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
22 granted / 30 resolved
+5.3% vs TC avg
Strong +22% interview lift
Without
With
+22.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
51 currently pending
Career history
81
Total Applications
across all art units

Statute-Specific Performance

§103
58.1%
+18.1% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 30 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 20, 2025 has been entered. Response to Amendment This Office Action is in response to Applicant's amendments filed November 20. 2025. Claims 1-2, 3, 7, 11-12, 14, and 17 have been amended. Claims 20-23 have been added. Claims 5, 8, 15, and 18 have been canceled. Currently, claims 1-4, 6-7, 9-14, 16-17, and 19-23 are pending. Response to Arguments Applicant's arguments filed November 20, 2025 have been fully considered but they are not persuasive. Applicant asserted that the combination of Sung and Seo does not disclose the limitations of newly amended claims 1 and 11. Specifically, Applicant asserted that the insulating layers (310, 320, 700) disposed over the functional layers (222a, 222c, 223) disclosed by Sung do not render obvious the crack prevention structure because they are to prevent moisture and is “not configured to absorb cracks”. The Examiner respectfully disagrees with this assertion, primarily because these layers were not relied upon the disclose the upper and lower structure parts of the crack prevention structure as indicated in Applicant’s argument. As outlined on pages 4-5 and 7 of the previous Office Action, Sung discloses that the groove structure filled with organic material stops the propagation of cracks from the non-display area to the display area (“the crack does not propagate further toward the display area DA due to the undercut structure of the third groove G3”, col. 19, lines 54-56, “The planarization layer 610 can prevent or minimize the occurrence of cracks”, col. 15, lines 43-44). The Applicant further asserts that Sung does not disclose the claimed crack prevention structure because “in cases where high-energy cracks exceeding a threshold are generated from the camera hole, it would be difficult for Sung to prevent crack propagation”. However, this feature was not part of the claim limitations. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant further asserts that Seo does not disclose a crack prevention structure and merely discloses a groove filled with an organic material. The Examiner respectfully disagrees with this assertion. Specifically, Sung discloses that filling grooves with organic material can prevent or minimize cracks (“the crack does not propagate further toward the display area DA due to the undercut structure of the third groove G3”, col. 19, lines 54-56, “The planarization layer 610 can prevent or minimize the occurrence of cracks”, col. 15, lines 43-44). Therefore, the Examiner asserts that one of ordinary skill in the art would recognize that the structure disclosed in Seo would be capable of the same function. The Applicant further asserts that the prior art of record fails to disclose or suggest “the crack prevention structure described in amended claims 1 and 11, being formed of the same organic material as the planarization layer”. The Examiner respectfully disagrees with this assertion. Sung discloses that the crack prevention structure is formed by the planarization layer 610 in the third groove G3. Sung further discloses that layer 610 can be the same material as the encapsulation layer 300 (see col. 5, lines 36-39). The encapsulation layer is described as including a polymer-based material, with polyimide given as an example (see col. 13, lines 41-44). The planarization film between the transistor and the light emitting element is organic insulating layer 209, which is also described as polyimide (see col. 12, line 23). Therefore, the Examiner beliefs that the prior art of record discloses these newly added limitations. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-7, 9, 11-14, 16-17, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Sung (US 10541380 B1) herein after “Sung” in view of Kim et al. (US 20230061355 A1) herein after “Kim” and Wang et al. (US 20240155872 A1) herein after “Wang”. Regarding claim 1, Fig. 21 of Sung discloses a display apparatus (Fig. 21, display panel 10, col. 6, line 48) comprising: a substrate (Fig. 21, “the substrate 100 includes a first base layer 101, a first inorganic layer 102, a second base layer 103”, col. 10, lines 61-62) including a display area (Fig. 21, display area DA, col. 6, lines 16-17), a camera hole (Fig. 21, opening 10H, col. 7, line 43), and a non-display area (Fig. 21, first non-display area NDA1, col. 6, line 29) between the display area (DA) and the camera hole (10H); a light-emitting element (Fig. 21, organic light-emitting diodes OLED, col. 9, lines 2-3) disposed in the display area (DA); one or more cut-out parts (see Annotation 1, Fig. 21 of Sung, “CP”) and a first dam (Fig. 21, partition wall 500, col. 14, line 61) in the non-display area (NDA1); a plurality of insulating films (Fig. 21, second inorganic layer 104, buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, col. 16, lines 46-47 and 61-62) disposed on the substrate (101-103) and disposed under the light-emitting element (OLED), the cut-out parts (CP), and the first dam (500); a transistor (Fig. 21, thin film transistor TFT, col. 11, line 22) between the plurality of insulating films (104, 201, 203, 205) and the light-emitting element (OLED); a planarization layer (Fig. 21, organic insulating layer 209, col. 12, line 13) between the transistor (TFT) and the light-emitting element (OLED); a crack prevention structure (Fig. 21, first to fourth grooves, col. 10, lines 18-19 and col. 22, lines 13-14) disposed between the camera hole (10H) and at least one of the first dam (500) and the second dam, wherein one or more lower structure parts (see Annotation 1, Fig. 21 of Sung, “LS”) of the crack prevention structure (G1-G4) are disposed in an area in which at least a portion of the plurality of insulating films (104, 201, 203, 205) is removed, and the crack prevention structure (G1-G4) is formed of an organic material (Fig. 21, planarization layer 610, col. 7, line 26) identical to that of the planarization layer (209), and wherein the one or more cut-out parts (CP) comprise a first cut-out part (see Annotation 1, Fig. 21 of Sung, “CP1”) disposed between the first dam (500) and the camera hole (CH), and a second cut-out part (see Annotation 1, Fig. 21 of Sung, “CP2”). PNG media_image1.png 552 430 media_image1.png Greyscale Annotation 1, Fig. 21 of Sung Sung fails to disclose a second dam disposed in the non-display area; a plurality of insulating films disposed on the second dam; a plurality of transistors; a second cut-out part disposed between the first dam and the second dam, the second dam being disposed adjacent to the display area, and the first cut-out part and the second cut-out part each comprise a plurality of cut-out structures. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses a second dam (Fig. 6, first partitions PW1, ¶ [0103]) disposed in the non-display area (Fig. 6, intermediate area IA, ¶ [0097]); a plurality of insulating films (Fig. 6, buffer layer 201, first gate insulating layer 203, first interlayer insulating layer 205, second interlayer insulating layer 207, second gate insulating layer 209, ¶ [0110-0122]) disposed on the second dam (PW1); a plurality of transistors (Fig. 6, first transistor T1 and the third transistor T3, ¶ [0125]); a second cut-out part (Fig. 6, third portion 230c, ¶ [0161]) disposed between the first dam (Fig. 6, second partitions PW2, ¶ [0103]) and the second dam (PW1), the second dam (PW1) being disposed adjacent to the display area (Fig. 6, display area DA, ¶ [0057]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors, second dam and cut-out parts as disclosed by Kim, to obtain the desired electrical characteristics and prevent damage (see Kim, ¶ [0086] and [0159]). Kim fails to disclose the first cut-out part and the second cut-out part each comprise a plurality of cut-out structures. In the similar field of endeavor of display devices, Fig. 3 of Wang discloses the first cut-out part (Fig. 3, crack-blocking dam 204, ¶ [0088]) and the second cut-out part (Fig. 3, barrier walls 202, ¶ [0055]) each comprise a plurality of cut-out structures (Fig. 3, “five barrier walls 202 are shown in the figure as an example”, “a plurality of crack-blocking dams 204”, ¶ [0055] and [0088]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the cut-out parts as disclosed by Wang, to prevent damage and improve reliability (see Wang, ¶ [0051]). Regarding claim 2, Sung, Kim and Wang together disclose the display apparatus of claim 1 as applied above, and Fig. 21 of Sung further discloses wherein an upper structure part (see Annotation 1, Fig. 21 of Sung, “US”) of the crack prevention structure (G1-G4) is disposed on the one or more lower structure parts (LS) of the crack prevention structure (G1-G4). Regarding claim 3, Sung, Kim and Wang together disclose the display apparatus of claim 2 as applied above, and Fig. 21 of Sung further discloses wherein the plurality of insulating films (104, 201, 203, 205) comprise a multi-buffer layer (Fig. 21, “the second inorganic layer 104, which has a multi-layered structure”, col. 27, lines 1-2) and a lower buffer layer (Fig. 21, buffer layer 201, col. 11, line 11). Regarding claim 4, Sung, Kim and Wang together disclose the display apparatus of claim 3 as applied above, and Fig. 21 of Sung further discloses wherein the area in which at least a portion of the plurality of insulating films (104, 201, 203, 205) is removed corresponds to a region in the non-display area (NDA1) from which the multi-buffer layer (104) and the lower buffer layer (201) are removed (Fig. 21, “the first to third grooves G1, G2 and G3 are formed by removing a portion of the substrate 100 that includes a plurality of layers”, col. 14, lines 29-31). Regarding claim 6, Sung, Kim and Wang together disclose the display apparatus of claim 2 as applied above, and Fig. 21 of Sung further discloses wherein the plurality of insulating films (104, 201, 203, 205) comprise a gate insulating film (Fig. 21, gate insulating layer 203, col. 11, line 31) and an interlayer insulating film (Fig. 21, first interlayer insulating layer 205, col. 11, lines 62-63). Regarding claim 7, Sung, Kim and Wang together disclose the display apparatus of claim 6 as applied above, and Fig. 21 of Sung further discloses wherein the area in which at least a portion of the plurality of insulating films (104, 201, 203, 205) corresponds to a region in the non-display area (NDA1) from which the gate insulating film (203) and the interlayer insulating film (205) are removed. Regarding claim 9, Sung, Kim and Wang together disclose the display apparatus of claim 1 as applied above, and Fig. 21 of Sung further discloses wherein the crack prevention structure (G2-G4) is disposed in the first cut-out part (CP). Regarding claim 11, Fig. 21 of Sung discloses a display apparatus (10) comprising: a substrate (101-103) comprising a non-display area (NDA1) disposed between a camera hole (10H) and a display area (DA); a plurality of inorganic insulating films (104, 201, 203, 205) disposed in the display area (DA) and the non-display area (NDA1); an organic light-emitting stack (OLED) disposed on the plurality of inorganic insulating films (104, 201, 203, 205) to correspond to the display area (DA); a transistor (TFT) between the plurality of inorganic insulating films (104, 201, 203, 205) and the organic light-emitting stack (OLED); a planarization layer (209) between the transistors (TFT) and the organic light-emitting stack (OLED); one or more cut-out parts (CP) and a first dam (500) disposed on the plurality of inorganic insulating films (104, 201, 203, 205) to correspond to the non-display area (NDA1); and a crack prevention structure (G1-G4) disposed in the one or more cut-out parts (CP), wherein one or more lower structure parts (LS) of the crack prevention structure (G1-G4) are disposed in an area in which at least a portion of the plurality of insulating films (104, 201, 203, 205) is removed, and the crack prevention structure (G1-G4) is formed of an organic material (610) identical to that of the planarization layer (209), and wherein the one or more cut-out parts (CP) comprise a first cut-out part (CP1) disposed between the first dam (500) and the camera hole (CH), and a second cut-out part (CP2). Sung fails to disclose a second dam disposed in the non- display area; a plurality of insulating films disposed on the second dam; a plurality of transistors; a second cut-out part disposed between the first dam and the second dam, the second dam being disposed adjacent to the display area, and the first cut-out part and the second cut-out part each comprise a plurality of cut-out structures. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses a second dam (PW1) disposed in the non-display area (IA); a plurality of insulating films (201, 203, 205, 207, 209) disposed on the second dam (PW1); a plurality of transistors (T1, T3); a second cut-out part (230c) disposed between the first dam (PW2) and the second dam (PW1), the second dam (PW1) being disposed adjacent to the display area (DA). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors, second dam and cut-out parts as disclosed by Kim, to obtain the desired electrical characteristics and prevent damage (see Kim, ¶ [0086] and [0159]). Kim fails to disclose the first cut-out part and the second cut-out part each comprise a plurality of cut-out structures. In the similar field of endeavor of display devices, Fig. 3 of Wang discloses the first cut-out part (204) and the second cut-out part (202) each comprise a plurality of cut-out structures (Fig. 3, “five barrier walls 202 are shown in the figure as an example”, “a plurality of crack-blocking dams 204”, ¶ [0055] and [0088]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the cut-out parts as disclosed by Wang, to prevent damage and improve reliability (see Wang, ¶ [0051]). Regarding claim 12, Sung, Kim and Wang together disclose the display apparatus of claim 11 as applied above, and Fig. 21 of Sung further discloses wherein an upper structure part (US) of the crack prevention structure (G1-G4) is disposed on the one or more lower structure parts (LS) of the crack prevention structure (G1-G4). Regarding claim 13, Sung, Kim and Wang together disclose the display apparatus of claim 12 as applied above, and Fig. 21 of Sung further discloses wherein the plurality of inorganic insulating films (104, 201, 203, 205) comprise a multi-buffer layer (104) and a lower buffer layer (201). Regarding claim 14, Sung, Kim and Wang together disclose the display apparatus of claim 13 as applied above, and Fig. 21 of Sung further discloses wherein the area in which at least a portion of the plurality of insulating films (104, 201, 203, 205) is removed corresponds to a region in the non-display area (NDA1) from which the multi-buffer layer (104) and the lower buffer layer (201) are removed (Fig. 21, “the first to third grooves G1, G2 and G3 are formed by removing a portion of the substrate 100 that includes a plurality of layers”, col. 14, lines 29-31). Regarding claim 16, Sung, Kim and Wang together disclose the display apparatus of claim 12 as applied above, and Fig. 21 of Sung further discloses wherein the plurality of inorganic insulating films (104, 201, 203, 205) comprise a gate insulating film (203) and an interlayer insulating film (205). Regarding claim 17, Sung, Kim and Wang together disclose the display apparatus of claim 16 as applied above, and Fig. 21 of Sung further discloses wherein the area in which at least a portion of the plurality of insulating films (104, 201, 203, 205) corresponds to a region in the non-display area (NDA1) from which the gate insulating film (203) and the interlayer insulating film (205) are removed. Regarding claim 19, Sung, Kim and Wang together disclose the display apparatus of claim 11 as applied above, and Fig. 21 of Sung further discloses wherein the crack prevention structure (G2-G4) is disposed in the first cut-out part (CP). Regarding claim 20, Sung, Kim and Wang together disclose the display apparatus of claim 1 as applied above, but Sung and Wang fail to disclose wherein the plurality of transistors includes a first transistor and a second transistor, and the second transistor is disposed on a gate electrode of the first transistor. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the plurality of transistors (T1, T3) includes a first transistor (T1) and a second transistor (T3), and the second transistor (T3) is disposed on a gate electrode (Fig. 6, first gate electrode GE1, ¶ [0112]) of the first transistor (T1). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Regarding claim 21, Sung, Kim and Wang together disclose the display apparatus of claim 20 as applied above, but Sung and Wang fail to disclose wherein the plurality of insulating films includes a lower interlayer insulating film disposed between the gate electrode of the first transistor and the second transistor. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the plurality of insulating films (201-209) includes a lower interlayer insulating film (Fig. 6, interlayer insulating layer 207, ¶ [0118]) disposed between the gate electrode (GE1) of the first transistor (T1) and the second transistor (T3). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Regarding claim 22, Sung, Kim and Wang together disclose the display apparatus of claim 20 as applied above, but Sung and Wang fail to disclose wherein the plurality of insulating films includes a lower gate insulating film disposed between the gate electrode of the first transistor and a semiconductor layer of the first transistor. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the plurality of insulating films (201-209) includes a lower gate insulating film (Fig. 6, interlayer insulating layer 205, ¶ [0116]) disposed between the gate electrode (GE1) of the first transistor (T1) and a semiconductor layer (Fig. 6, first semiconductor layer A1, ¶ [0112]) of the first transistor (T1). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Regarding claim 23, Sung, Kim and Wang together disclose the display apparatus of claim 20 as applied above, but Sung and Wang fail to disclose wherein the planarization layer includes a first planarization layer disposed on the plurality of transistors, and a second planarization layer disposed on the first planarization layer, and a connection electrode is disposed on the first planarization layer between the first planarization layer and the second planarization layer. In the similar field of endeavor of display apparatuses, Fig. 6 of Kim discloses wherein the planarization layer includes a first planarization layer (Fig. 6, interlayer insulating layer 210, ¶ [0123]) disposed on the plurality of transistors (T1, T3), and a second planarization layer (Fig. 6, organic insulating layer 211, ¶ [0127]) disposed on the first planarization layer (210), and a connection electrode (Fig. 6, connection line 166, ¶ [0086]) is disposed on the first planarization layer (210) between the first planarization layer (210) and the second planarization layer (211). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung with the transistors as disclosed by Kim, to obtain the desired electrical characteristics (see Kim, ¶ [0086]). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sung (US 10541380 B1), Kim (US 20230061355 A1) and Wang (US 20240155872 A1) in view of Seo et al. (US 20190334120 A1) herein after “Seo”. Regarding claim 10, Sung, Kim and Wang together disclose the display apparatus of claim 1 as applied above, but Sung, Kim and Wang fail to disclose wherein the crack prevention structure is disposed in the second cut-out part. In the similar field of endeavor of display panels, Fig.9B of Seo discloses wherein the crack prevention structure (Fig. 9B, “the first blocking groove BR1-F is filled with the organic layer 33-F”, ¶ [0157]) is disposed in the second cut-out part (BR1-F). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the display apparatus of Sung to include the crack prevention structure as disclosed by Seo, to increase crack resistance (see Seo, ¶ [0157]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 7:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.A.N./ Examiner, Art Unit 2893 /YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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Prosecution Timeline

Oct 29, 2022
Application Filed
Apr 07, 2025
Non-Final Rejection — §103
Jul 17, 2025
Response Filed
Aug 11, 2025
Final Rejection — §103
Nov 20, 2025
Request for Continued Examination
Nov 25, 2025
Response after Non-Final Action
Mar 09, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
96%
With Interview (+22.2%)
3y 7m
Median Time to Grant
High
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