DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 21 January 2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8, 12, 13, 18, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (US Publication 20230282684).
Regarding claim 1, Lee teaches a display panel, comprising:
a substrate (Fig. 7, BSL);
an active layer disposed on the substrate (Fig. 7, SCP), wherein the active layer comprises a channel portion and two conductive portions located at two sides of the channel portion (Fig. 7, channel portion SCP3 and two conductive portions at either side SCP1 and SCP2);
a first conductive layer disposed at one side of the active layer close to or away from the substrate, wherein the first conductive layer comprises a gate electrode (Fig. 7, GE), and a projection of the gate electrode projected on the substrate overlaps with a projection of the channel portion projected on the substrate (Fig. 7, GE overlaps SCP3); and
a second conductive layer disposed at one side of the active layer away from the substrate, the second conductive layer comprising a source electrode connected to one of the conductive portions (Fig. 7, TE1 conductive portion ALE1 source electrode);
wherein the source electrode is disposed in a different layer from a drain electrode connected to the other one of the conductive portions (Fig. 7, source electrode ALE1 in different layer than drain electrode TE2), and the source electrode extends toward the drain electrode such that a projection of the source electrode projected on the substrate overlaps with the projection of the gate electrode projected on the substrate (Fig 7, BNK area including LD above where source electrode ALE1 projection extends toward TE2 and overlaps with gate electrode GE, see also Fig. 5, ALE1 overlaps BNK, para 124);
wherein the projection of the source electrode projected on the substrate completely covers the projection of the gate electrode projected on the substrate (Fig. 7, ALE1 projection on substrate completely covers GE);
wherein the first conductive layer further comprises the drain electrode which is in the same layer as and spaced apart from the gate electrode (Fig. 7, drain electrode TE2 is spaced apart from and in the same layer as GE), and a first gap is defined between a projection of the drain electrode projected on the substrate and the projection of the gate electrode projected on the substrate (Fig. 7, gap between TE2 and GE)
wherein a material of the drain electrode is same as a material of the gate electrode (para 159, GE and TE2 formed of "molybdenum (Mo), copper (Cu), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and an oxide or alloy thereof").
wherein the second conductive layer further comprises a first electrode portion which is in the same layer as and spaced apart from the source electrode (Fig. 4-7, ALE2 in same layer as and spaced apart from ALE1), and the first electrode portion is connected to the drain electrode (para 100-102; drain TE2 is connected to VSS – see figure 4 specifically as the bottom/drain of diode is connected to VSS, and paragraphs 100-102 describe ALE2 connected to VSS through ELT5, therefore, the first electrode portion ALE2 has an electrical connection to drain electrode TE2).
Regarding claim 2, Lee teaches the limitations of claim 1 upon which claim 2 depends.
Lee teaches wherein the projection of the source electrode projected on the substrate overlaps the first gap (Fig. 7, ALE1 overlaps gap between TE2 and GE).
Regarding claim 3, Lee teaches the limitations of claim 1 upon which claim 3 depends.
Lee teaches wherein the first conductive layer is disposed between the second conductive layer and the active layer (Fig. 7, GE, TE1 and TE2 disposed between ALE1 and SCP), and the display panel further comprises:
a passivation layer disposed between the first conductive layer and the second conductive layer (Fig. 7, PSV between conductive layers);
wherein each of the conductive portions comprises a first conductive portion and a second conductive portion, the second conductive portion is disposed between the first conductive portion and the channel portion, a projection of the second conductive portion projected on the substrate overlaps the first gap (Fig. 12, SCP2 and ST2 overlapping gap between TE2 and GE), and a concentration of hydrogen in the second conductive portion is higher than a concentration of hydrogen in the channel portion (para 150, "SCP1 may function as a source area and may be a first conductive area doped with a corresponding impurity. The second area SCP2 may function as a drain area and may be a second conductive area doped with a corresponding impurity. The third area SCP3 may function as a channel area and may be an area doped with no impurity" where hydrogen is the impurity dopant for the materials of SCP listed in para 149 "oxide semiconductor, at least one of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium gallium tin oxide (IGTO), and indium zinc oxide (IZO)").
Regarding claim 4, Lee teaches the limitations of claim 3 upon which claim 4 depends.
Lee teaches a barrier layer disposed on one side of the passivation layer away from the substrate, wherein a material of the barrier layer comprises at least one of aluminum oxide or titanium oxide (Fig. 7, VIA, para 163, "silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx)").
Regarding claim 5, Lee teaches the limitations of claim 1 upon which claim 5 depends.
Lee teaches a second gap is defined between a projection of the first electrode portion projected on the substrate and a projection of the active layer projected on the substrate, and the projection of the source electrode projected on the substrate overlaps the second gap (Fig. 5 and 7, gap defined by ALE2 and SCP projections along z axis overlapped by ALE1).
Regarding claim 6, Lee teaches the limitations of claim 5 upon which claim 6 depends.
Lee teaches wherein a material of the source electrode and a material of the first electrode portion both comprise at least one of metal or metal oxide (para 166, electrodes ALE of metal or metal oxide).
Regarding claim 8, Lee teaches a display panel, comprising:
a substrate (Fig. 7, BSL);
an active layer disposed on the substrate (Fig. 7, SCP), wherein the active layer comprises a channel portion and two conductive portions located at two sides of the channel portion (Fig. 7, channel portion SCP3 and two conductive portions at either side SCP1 and SCP2);
a first conductive layer disposed at one side of the active layer close to or away from the substrate, wherein the first conductive layer comprises a gate electrode (Fig. 7, GE), and a projection of the gate electrode projected on the substrate overlaps with a projection of the channel portion projected on the substrate (Fig. 7, GE overlaps SCP3); and
a second conductive layer disposed at one side of the active layer away from the substrate, the second conductive layer comprising a source electrode connected to one of the conductive portions (Fig. 7, TE1 conductive portion ALE1 source electrode);
wherein the source electrode is disposed in a different layer from a drain electrode connected to the other one of the conductive portions (Fig. 7, source electrode ALE1 in difference layer than drain electrode TE2), and a projection of the source electrode projected on the substrate overlaps with the projection of the gate electrode projected on the substrate (Fig. 7, source electrode ALE1 projection overlaps with gate electrode GE);
wherein the projection of the source electrode projected on the substrate completely covers the projection of the gate electrode projected on the substrate (Fig. 7, source electrode ALE1 projection completely covers gate GE);
wherein the first conductive layer further comprises the drain electrode which is in the same layer as and spaced apart from the gate electrode (Fig. 7, drain electrode TE2 in same layer and spaced apart from gate electrode GE), and a first gap is defined between a projection of the drain electrode projected on the substrate and the projection of the gate electrode projected on the substrate (Fig. 7, gap between TE2 and GE);
wherein a material of the drain electrode is same as a material of the gate electrode (para 159, GE and TE2 formed of "molybdenum (Mo), copper (Cu), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and an oxide or alloy thereof"), and the projection of the source electrode projected on the substrate overlaps the first gap (Fig. 7, ALE1 overlaps gap between TE2 and GE).
wherein the second conductive layer further comprises a first electrode portion which is in the same layer as and spaced apart from the source electrode (Fig. 4-7, ALE2 in same layer as and spaced apart from ALE1), and the first electrode portion is connected to the drain electrode (para 100-102; drain TE2 is connected to VSS – see figure 4 specifically as the bottom/drain of diode is connected to VSS, and paragraphs 100-102 describe ALE2 connected to VSS through ELT5, therefore, the first electrode portion ALE2 has an electrical connection to drain electrode TE2); and
wherein a second gap is defined between a projection of the first electrode portion projected on the substrate and a projection of the active layer projected on the substrate, and the projection of the source electrode projected on the substrate overlaps the second gap (Fig. 5 and 7, gap defined by ALE2 and SCP projections along z axis overlapped by ALE1).
Regarding claim 12, Lee teaches the limitation of claim 8 upon which claim 12 depends.
Lee teaches wherein the first conductive layer is disposed between the second conductive layer and the active layer, and the display panel further comprises (Fig. 7, GE, TE1 and TE2 disposed between ALE1 and SCP):
a passivation layer disposed between the first conductive layer and the second conductive layer (Fig. 7, PSV between conductive layers);
wherein each of the conductive portions comprises a first conductive portion and a second conductive portion, the second conductive portion is disposed between the first conductive portion and the channel portion , a projection of the second conductive portion projected on the substrate overlaps the first gap (Fig. 12, SCP2 and ST2 overlapping gap between TE2 and GE), and a concentration of hydrogen in the second conductive portion is higher than a concentration of hydrogen in the channel portion (para 150, "SCP1 may function as a source area and may be a first conductive area doped with a corresponding impurity. The second area SCP2 may function as a drain area and may be a second conductive area doped with a corresponding impurity. The third area SCP3 may function as a channel area and may be an area doped with no impurity" where hydrogen is the impurity dopant for the materials of SCP listed in para 149 "oxide semiconductor, at least one of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium gallium tin oxide (IGTO), and indium zinc oxide (IZO)").
Regarding claim 13, Lee teaches the limitations of claim 12 upon which claim 13 depends.
Lee teaches a barrier layer disposed on one side of the passivation layer away from the substrate, wherein a material of the barrier layer comprises at least one of aluminum oxide or titanium oxide (Fig. 7, VIA, para 163, "silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx)").
Regarding claim 15, Lee teaches the limitations of claim 8 upon which claim 15 depends.
Lee teaches wherein a material of the source electrode and a material of the first electrode portion both comprise at least one of metal or metal oxide (para 166, electrodes ALE of metal or metal oxide).
Regarding claim 16, Lee teaches the limitations of claim 8 upon which claim 16 depends.
Lee teaches a first gate insulating layer disposed between the active layer and the first conductive layer (Fig. 7, GI between SCP layer and TE3/GE layer).
a passivation layer disposed between the drain electrode and the second conductive layer (Fig. 7, PSV between TE2 layer and ALE1 layer).
Regarding claim 18, Lee teaches the limitations of claim 8 upon which claim 18 depends.
Lee teaches a first gate insulating layer disposed between the active layer and the first conductive layer (Fig. 7, GI);
a passivation layer disposed between the first conductive layer and the second conductive layer (Fig. 7, PSV between TE2 and ALE1); and
a light shielding layer disposed at one side of the active layer close to the substrate (Fig. 7, BML1), wherein a projection of the light shielding layer projected on the substrate covers a projection of the active layer projected on the substrate (Fig. 7, BML1 projection covers SCP projection);
wherein the drain electrode and the light shielding layer are arranged in the same layer (Fig. 7, BML1 and TE2 in BFL layer).
Regarding claim 19, Lee teaches the limitations of claim 8 upon which claim 19 depends.
Lee teaches a light shielding layer disposed at one side of the active layer close to the substrate (Fig. 7, BML1, para 92 “light-shielding pattern”), wherein a projection of the light shielding layer projected on the substrate covers a projection of the active layer projected on the substrate (Fig. 7, BML1 projection covers SCP projection), and one end of the light shielding layer is connected to at least one of the source electrode or the drain electrode (Fig. 7, BML1 electrically connected to source ALE1).
Regarding claim 20, Lee teaches the limitations of claim 8 upon which claim 20 depends.
Lee teaches an electronic terminal, wherein the electronic terminal comprises the display panel of claim 8 (Fig. 3, PNL, para 78).
Response to Arguments
Applicant's arguments filed 21 January 2026 have been fully considered but they are not persuasive.
Applicant beings the argument stating that He teaches away from the claimed ‘different layer’ architecture. In the new rejection above, He is not used to teach any part of the different layer, as in a new interpretation of Lee this is seen, which is a 102 of amended claim 1.
Applicant arguments regarding claims 1 and 2 with respect to the limitation “wherein the projection of the source electrode projected on the substrate completely covers the projection of the gate electrode projected on the substrate” are not persuasive.
Applicant argues that Lee expressly disclaims the precision of the drawings in paragraphs 43 “relative sizes of elements, layers, and regions may be exaggerated for clarity” and 46 “regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape”.
While it is understood that figures are not drawn to scale, if a figure clearly shows a limitation, especially of one element covering the other, then prior art figure reads on the claimed invention in the broadest reasonable interpretation. See below annotated figure of the projection of the gate electrode (GE) is fully covered by the projection of the source electrode (ALE1) in the x direction. Understanding that someone looking down from the z direction would see that the source electrode covers the gate electrode in the x direction. Applicant is invited to more clearly claim the extent of the coverage in specific directions, etc … to clearly articulate the difference between present invention and the prior art to Lee.
PNG
media_image1.png
555
665
media_image1.png
Greyscale
To add further context to the quoted portions of paragraphs 43 and 46, para 45 states: “For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.”
Fig. 4 and 5 show a PXL unit (para 86-87) “including an emission component EMU configured to generate light having luminance corresponding to a data signal, and a pixel circuit PXC configured to drive the emission component EMU”.
This PXC, shown in figure 4, includes “at least one transistor and at least one capacitor. For example, the pixel circuit PXC may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst” para 89.
“The electrodes ALE may at least partially overlap the above-stated bank BNK. The first to third electrodes ALE1, ALE2, and ALE3 each may extend in the second direction (the Y-axis direction), and may be spaced apart from each other in the first direction (the X-axis direction), and may be successively located. Some of the electrodes ALE may be connected to the pixel circuit (PXC of FIG. 4 ) and/or a power line through a contact hole” para 124.
In comparing Fig. 5 and 7, the BNK area surrounds the various LDs with ALE1 covering the top of the EA along the lines of A-A’ and B-B’. Fig. 7 clearly shows the transistor M1, which is included with the LDs.
As to the specific argument for claim 8, Applicant again argues the He reference, but under a different interpretation of Lee, He is no longer used in the rejection of claim 8.
As to the technical arguments, please define in the claim language the structure associated with the technical argument to overcome the prior art rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US Patent 12376475), Jeong (US Publication 20250048739), and Wang (US Publication 20250015092) all describe LED drive transistors within a display panel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818