Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 30, 2025 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10 2021 0150858, filed on November 4, 2021.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed October 30, 2025. Claims 7 and 14 are amended. Claims 1, 3-6, 8, and 15 are cancelled. The Examiner notes that claims 7, 10-14, and 17-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 10-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2023/0005861 A1) hereinafter referred to as Wang-1 in view of Wang (Journal of Crystal Growth, 2005), hereinafter referred to as Wang-2 and Nakai (US 2013/0277809 A1).
With respect to claim 7, Wang-1 teaches in Fig. 11A:
A memory device comprising:
a first substrate (para 120 “semiconductor layer 1002 is a silicon substrate);
a peripheral circuit (first peripheral circuit 1104) comprising a transistor (one of a plurality of transistors 1108) on the first substrate (1102);
an insulating layer (para. 121, interlayer dielectric layers (ILD) in interconnect layer 1112 which may include silicon oxide which is an insulator) on the first substrate (1002) and on the peripheral circuit (1104);
a second substrate (polysilicon layer 106) on the insulating layer (ILD in 1112);
and a three-dimensional (3D) NAND memory cell array (para. 65 “First semiconductor structure 102 can be a NAND Flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings”) on the second substrate (106),
Wang-1 fails to teach:
wherein the first substrate comprises p-type impurities and n-type impurities,
wherein a concentration of the n-type impurities in the first substrate is lower than a concentration of the p-type impurities in the first substrate,
and wherein the concentration of the n-type impurities in the first substrate is about 2x1014 atoms/cm3 to about 1.5x1015 atoms/cm3,
and the concentration of the p-type impurities in the first substrate is about 9x1014 atoms/cm3 to about 2x1015 atoms/cm3.
wherein a resistivity of the first substrate is about 14 ohms centimeter (Ωcm) to about 17 Ωcm.
Wang-2 teaches:
wherein the first substrate (pg. 409, col. 1, para. 3 “The melt growth method is generally used for the production of substrate material”) comprises p-type impurities (boron) and n-type impurities (phosphorous) (pg. 409, col. 2, para. 2 “Two sorts of impurities (e.g., boron and phosphorus) are doped simultaneously”),
wherein a concentration of the n-type impurities (pg. 411, col. 1, “initial phosphorus concentration of 6.00 x 10^14 atoms/cm3”) in the first substrate is lower than a concentration of the p-type impurities (pg. 411, col. 1“the initial boron concentration of 1.79 x 10^15 atoms/cm”) in the first substrate,
and wherein the concentration of the n-type impurities in the first substrate is about 2x1014 atoms/cm3 to about 1.5x1015 atoms/cm3 (pg. 411, col. 1, “initial phosphorus concentration of 6.00 x 10^14 atoms/cm^3”),
and the concentration of the p-type impurities in the first substrate is about 9x1014 atoms/cm3 to about 2x1015 atoms/cm3 (pg. 411, col. 1“the initial boron concentration of 1.79 x 10^15 atoms/cm^3”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wang-2 into the device of Wang-1 to include a substrate with the claimed properties. The ordinary artisan would have been motivated to modify Wang-1 in the manner set forth above for the purpose of controlling the uniformity of the resistivity distribution of the substrate (conclusion of Wang-2) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Wang-2 teaches that the resistivity of the tested samples ranges from 9.68-10.16 Ωcm, outside the claimed range of 14-17 Ωcm.
Nakai teaches a similar method to Wang-2 in which codoped crystals are formed according to a variety of impurity concentrations. Nakai teaches samples in the range of 50-192 Ωcm (see table 3).
The combination of Wang-2 and Nakai teaches that the same method can be used to make crystals with both n-type impurities and p-type impurities and that the resistivity of the substrate can be tuned based on the initial concentration of impurities in the melt.
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
The resistivity disclosed by Wang-2 is below the range claimed in claim 7, and the resistivity disclosed by Nakai is higher than the range claimed in claim 7. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the resistivity by tuning doping concentrations with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Wang-1 does not specify the relative impurity concentrations of the first and second substrates. However, Wang-2 and Nakai teach that substrates can be made with different impurity concentrations in order to tune the resistivity profile of the substrate. Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. The Applicant has not demonstrated that the limitation “and wherein a concentration of the n-type impurities in the second substrate is lower than the concentration of the n-type impurities in the first substrate” is critical and recites in para. [0075] that a concentration of n-type impurities in the first substrate may also be lower, and states in para. [0076] that the concentrations may be the same. As the Applicant has not shown evidence that the claimed relative concentrations between the first and second substrate is critical or leads to an unexpected result, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to choose a second substrate in which the n-type impurities have a lower concentration than the first substrate, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 10, Wang-1/Wang-2/Nakai does not explicitly teach:
wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V.
Claim 10 is not directed to a structure, but rather is directed to a functional limitation or inherent property of the device described in independent claim 7. “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103” (MPEP 2112 (III)). The Examiner takes the position that since Wang-1 modified by Wang-2 teaches all structural limitations of the independent claim, the limitations of claim 10 are inherently taught by Wang-1/Wang-2.
In the event that the breakdown voltage is not inherent, which the examiner does not concede, it would be obvious for a person of ordinary skill in the art to arrive at a breakdown voltage within the claimed range through optimization within prior art conditions or through routine experimentation. The ordinary artisan would be motivated to optimize the breakdown voltage characteristics of the transistors in order to minimize the range of breakdown voltages to within acceptable tolerances.
With respect to claim 11, Wang-1/Wang-2/Nakai does not explicitly teach:
wherein a standby current of the memory device is less than or equal to 40 microamperes (µA).
Claim 11 is not directed to a structure, but rather is directed to a functional limitation or inherent property of the device described in independent claim 7. “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103” (MPEP 2112 (III)). The Examiner takes the position that since Wang-1 modified by Wang-2 teaches all structural limitations of the independent claim, the limitations of claim 11 are inherently taught by Wang-1/Wang-2.
In the event that the standby current is not inherent, which the examiner does not concede, it would be obvious for a person of ordinary skill in the art to arrive at a standby current within the claimed range through optimization within prior art conditions or through routine experimentation. The ordinary artisan would be motivated to optimize the standby current characteristics of the memory device in order to minimize the range of standby currents to within acceptable tolerances.
With respect to claim 12, Wang-1/Wang-2/Nakai does not explicitly teach:
wherein a leakage current of the transistor during an erase operation of the memory device is about 20.8 microamperes (µA) to about 22.5 µA.
Claim 12 is not directed to a structure, but rather is directed to a functional limitation or inherent property of the device described in independent claim 7. “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103” (MPEP 2112 (III)). The Examiner takes the position that since Wang-1 modified by Wang-2 teaches all structural limitations of the independent claim, the limitations of claim 12 are inherently taught by Wang-1/Wang-2.
In the event that the leakage current is not inherent, which the examiner does not concede, it would be obvious for a person of ordinary skill in the art to arrive at a leakage current within the claimed range through optimization within prior art conditions or through routine experimentation. The ordinary artisan would be motivated to optimize the leakage current characteristics of the memory device in order to minimize the range of leakage currents to within acceptable tolerances.
With respect to claim 13, Wang-1 further teaches:
wherein the 3D NAND memory cell array (NAND memory string 208) comprises:
a stack structure comprising a plurality of gate layers (gate conductive layers 806) alternately stacked with a plurality of interlayer insulating layers (dielectric layers 808) on the second substrate (106, not shown in Fig. 8, shown in Fig. 11A);
and a plurality of channel structures, wherein ones of the plurality of channel structures (channel structures 812) penetrate the stack structure in a vertical direction that is perpendicular to the second substrate (Figs. 8, 11A, para 169 “Each NAND memory string 208 extends vertically through a plurality of pairs each including a conductive layer and a dielectric layer”).
With respect to claim 14, Wang-1 teaches (Fig. 11A):
A memory device comprising a first structure (semiconductor structure 102) and a second structure (semiconductor structure 104) on the first structure (102), wherein the first structure comprises:
a first substrate (polysilicon layer 106);
a three-dimensional (3D) NAND memory cell array (para. 65 “First semiconductor structure 102 can be a NAND Flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings”) on the first substrate (106);
a first insulating layer (para. 125, ILD layers of interconnect layer 1128 which can be made of known insulator silicon oxide) on the first substrate (106) and on the 3D NAND memory cell array (array of NAND memory strings 208);
and a plurality of first bonding pads (Bonding layer 1008 can include a plurality of bonding contacts) on the first insulating layer (ILD layer of 1128) and electrically connected to the 3D NAND memory cell array (array of NAND memory strings 208) (Fig. 11A),
and wherein the second structure (104) comprises:
a second substrate (semiconductor layer 1004);
a peripheral circuit (peripheral circuit 1116) comprising a transistor (one of the plurality of transistors 1120) on the second substrate (1004);
a second insulating layer (ILD made of insulator silicon oxide within interconnect layer 1126) on the second substrate (1004) and the peripheral circuit (1116);
and a plurality of second bonding pads (para. 160, “bonding layer 1010 can also include conductive bonding contacts (not shown)”) on the second insulating layer (ILD of 1126) and electrically connected to the peripheral circuit (Fig. 11A),
wherein the plurality of first bonding pads (bonding contacts in 1008) are respectively in contact with the plurality of second bonding pads (bonding contacts in 1010) (para. 160 bonding layers 1008 and 1010 can be disposed on opposite sides of bonding interface 103, and the bonding contacts of bonding layer 1008 can be in contact with the bonding contacts of bonding layer 1010 at bonding interface 103. As a result, a large number (e.g., millions) of bonding contacts across bonding interface 103, in conjunction with through contacts (e.g., ILVs/TSVs) through semiconductor layer 1004, can make direct, short-distance (e.g., micron-level) electrical connections between adjacent semiconductor structures 102 and 104),
Wang-1 fails to teach:
wherein the second substrate comprises p-type impurities and n-type impurities,
wherein a concentration of the n-type impurities in the second substrate is lower than a concentration of the p-type impurities in the second substrate,
and wherein the concentration of the n-type impurities in the second substrate is about 2x1014 atoms/cm3 to about 1.5x1015 atoms/cm3, and the concentration of the p-type impurities in the second substrate is about 9x1014 atoms/cm3 to about 2x1015 atoms/cm3.
wherein a resistivity of the second substrate is about 14 ohms centimeter (Ωcm) to about 17 Ωcm.
Wang-2 teaches:
wherein the substrate (pg. 409, col. 1, para. 3 “The melt growth method is generally used for the production of substrate material”) comprises p-type impurities (boron) and n-type impurities (phosphorous) (pg. 409, col. 2, para. 2 “Two sorts of impurities (e.g., boron and phosphorus) are doped simultaneously”),
wherein a concentration of the n-type impurities (pg. 411, col. 1, “initial phosphorus concentration of 6.00 x 10^14 atoms/cm3”) in the substrate is lower than a concentration of the p-type impurities (pg. 411, col. 1“the initial boron concentration of 1.79 x 10^15 atoms/cm”) in the substrate,
and wherein the concentration of the n-type impurities in the substrate is about 2x1014 atoms/cm3 to about 1.5x1015 atoms/cm3 (pg. 411, col. 1, “initial phosphorus concentration of 6.00 x 10^14 atoms/cm3”),
and the concentration of the p-type impurities in the substrate is about 9x1014 atoms/cm3 to about 2x1015 atoms/cm3 (pg. 411, col. 1“the initial boron concentration of 1.79 x 10^15 atoms/cm”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wang-2 into the device of Wang-1 to include a second substrate with the claimed properties. The ordinary artisan would have been motivated to modify Wang-1 in the manner set forth above for the purpose of controlling the uniformity of the resistivity distribution of the substrate (conclusion of Wang-2) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Wang-2 teaches that the resistivity of the tested samples ranges from 9.68-10.16 Ωcm, outside the claimed range of 14-17 Ωcm.
Nakai teaches a similar method to Wang-2 in which codoped crystals are formed according to a variety of impurity concentrations. Nakai teaches samples in the range of 50-192 Ωcm (see table 3).
The combination of Wang-2 and Nakai teaches that the same method can be used to make crystals with both n-type impurities and p-type impurities and that the resistivity of the substrate can be tuned based on the initial concentration of impurities in the melt.
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
The resistivity disclosed by Wang-2 is below the range claimed in claim 7, and the resistivity disclosed by Nakai is higher than the range claimed in claim 7. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the resistivity by tuning doping concentrations with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Wang-1 does not specify the relative impurity concentrations of the first and second substrates. However, Wang-2 and Nakai teach that substrates can be made with different impurity concentrations in order to tune the resistivity profile of the substrate. Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. The Applicant has not demonstrated that the limitation “and wherein a concentration of the n-type impurities in the first substrate is lower than the concentration of the n-type impurities in the second substrate” is critical and recites in para. [0067] that a concentration of n-type impurities in the second substrate may also be lower, and states in para. [0076] that the concentrations may be the same. As the Applicant has not shown evidence that the claimed relative concentrations between the first and second substrate is critical or leads to an unexpected result, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to choose a second substrate in which the n-type impurities have a lower concentration than the first substrate, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 17, Wang-1/Wang-2/Nakai does not explicitly teach:
wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V.
Claim 17 is not directed to a structure, but rather is directed to a functional limitation or inherent property of the device described in independent claim 14. “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103” (MPEP 2112 (III)). The Examiner takes the position that since Wang-1 modified by Wang-2 teaches all structural limitations of the independent claim, the limitations of claim 17 are inherently taught by Wang-1/Wang-2.
In the event that the breakdown voltage is not inherent, which the examiner does not concede, it would be obvious for a person of ordinary skill in the art to arrive at a breakdown voltage within the claimed range through optimization within prior art conditions or through routine experimentation. The ordinary artisan would be motivated to optimize the breakdown voltage characteristics of the transistors in order to minimize the range of breakdown voltages to within acceptable tolerances.
With respect to claim 18, Wang-1/Wang-2/Nakai does not explicitly teach:
wherein a standby current of the memory device is less than or equal to 40 microamperes (µA).
Claim 18 is not directed to a structure, but rather is directed to a functional limitation or inherent property of the device described in independent claim 14. “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103” (MPEP 2112 (III)). The Examiner takes the position that since Wang-1 modified by Wang-2 teaches all structural limitations of the independent claim, the limitations of claim 18 are inherently taught by Wang-1/Wang-2.
In the event that the standby current is not inherent, which the examiner does not concede, it would be obvious for a person of ordinary skill in the art to arrive at a standby current within the claimed range through optimization within prior art conditions or through routine experimentation. The ordinary artisan would be motivated to optimize the standby current characteristics of the memory device in order to minimize the range of standby currents to within acceptable tolerances.
With respect to claim 19, Wang-1/Wang-2/Nakai does not explicitly teach:
wherein a leakage current of the transistor during an erase operation of the memory device is about 20.8 microamperes (µA) to about 22.5 µA.
Claim 19 is not directed to a structure, but rather is directed to a functional limitation or inherent property of the device described in independent claim 14. “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103” (MPEP 2112 (III)). The Examiner takes the position that since Wang-1 modified by Wang-2 teaches all structural limitations of the independent claim, the limitations of claim 19 are inherently taught by Wang-1/Wang-2.
In the event that the leakage current is not inherent, which the examiner does not concede, it would be obvious for a person of ordinary skill in the art to arrive at a leakage current within the claimed range through optimization within prior art conditions or through routine experimentation. The ordinary artisan would be motivated to optimize the leakage current characteristics of the memory device in order to minimize the range of leakage currents to within acceptable tolerances.
With respect to claim 20, Wang-1 further teaches:
wherein the 3D NAND memory cell array (NAND memory string 208) comprises:
a stack structure comprising a plurality of gate layers (gate conductive layers 806) alternately stacked with a plurality of interlayer insulating layers (dielectric layers 808) on the second substrate (106, not shown in Fig. 8, shown in Fig. 11A);
and a plurality of channel structures, wherein ones of the plurality of channel structures (channel structures 812) penetrate the stack structure in a vertical direction that is perpendicular to the substrate (Figs. 8, 11A, para 169 “Each NAND memory string 208 extends vertically through a plurality of pairs each including a conductive layer and a dielectric layer”).
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2023/0005861 A1) in view of Wang (Journal of Crystal Growth, 2005) and Nakai (US 2013/0277809 A1) as applied to independent claims 1, 7, and 14 above and further in view of Nishihara (US 2010/0117134 A1).
With respect to claims 10 and 17, Wang-1/Wang-2/Nakai teach all limitations of the independent claims 7 and 14 upon which claims 10 and 17 depend, respectively.
In the event that the limitations “wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V” as recited in claims 3, 10, and 17 is not obvious over Wang-1/Wang-2/Nakai, which the Examiner does not concede, Nishihara further teaches:
wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V (para. 56 “The peripheral element 41 is illustratively a high-voltage transistor having a breakdown voltage of approximately 25 V (volts).”)
The Examiner takes the position that the claimed range of “about 19 volts (V) to about 24V” allows for resistivity values slightly larger than 24 V, which includes the breakdown voltage 25 V taught by Nishihara.
In the event that the breakdown voltage of Nishihara does not fall within “about 24 V,” which the Examiner does not concede, “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close” (MPEP 2144.05 (I)). The Examiner takes the position the breakdown voltage taught by Nishihara is close enough to the claimed resistivity that a person of ordinary skill in the art would expect the transistors to have the same properties.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Nishihara into the device of Wang-1/Wang-2/Nakai to include a breakdown voltage of the transistor in the claimed range. The ordinary artisan would have been motivated to modify Wang-1/Wang-2 in the manner set forth above for the purpose of making a memory device in which the peripheral element has a transistor that operates at high voltage (para. 56 of Nishihara).
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2023/0005861 A1) in view of Wang (Journal of Crystal Growth, 2005) and Nakai (US 2013/0277809 A1) as applied to independent claims 1, 7, and 14 above and further in view of Tanzawa (IEEE Journal of Solid-State Circuits, 2002).
With respect to claims 11 and 18, Wang-1/Wang-2/Nakai teach all limitations of the independent claims 7 and 14 upon which claims 11 and 18 depend, respectively.
In the event that the limitations “wherein a standby current of the memory device is less than or equal to 40 microamperes (µA)” as recited in claims 11 and 18 is not obvious over Wang-1/Wang-2, which the Examiner does not concede, Tanzawa further teaches:
wherein a standby current of the memory device is less than or equal to 40 microamperes (µA) (pg. 88, para. 2 of V. Measured Results, “A standby current of 10 µA at 85 C was measured”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tanzawa into the device of Wang-1/Wang-2/Nakai to include a standby current of the memory device in the claimed range. The ordinary artisan would have been motivated to modify Wang-1/Wang-2/Nakai in the manner set forth above for the purpose of making a memory device in which charge-pump circuits require a reduced area (abstract of Tanzawa).
Response to Arguments
Applicant's arguments filed October 30, 2025 have been fully considered but they are not persuasive.
Applicant argues that Wang-1 does not disclose the impurity concentrations of the first and second substrate and therefore does not teach the limitations “wherein a concentration of the n-type impurities in the second substrate is lower than the concentration of the n-type impurities in the first substrate “of claim 7 or “wherein a concentration of the n-type impurities in the first substrate is lower than the concentration of the n-type impurities in the second substrate” of claim 14. The Applicant has not provided evidence that the concentrations are critical or lead to an unexpected result. The specification of the instant application recites that the benefits of the substrates and the impurity concentration is that the method of making the substrate leads to small variation of electrical characteristics because the variation of the p-type concentration is offset by the variation of the n-type impurity concentration but does not explain why there is a criticality or unexpected result to the second substrate having a higher or lower concentration of impurities than the first substrate. Both Nakai (abstract “good radial uniformity of resistivity and less variation in resistivity can be obtained”) and Wang-2 (abstract “the axial specific resistivity distribution can be modified in melt growth of silicon crystals and relatively uniform profile is possible by B–P codoping method”) teach methods in which the variation of electrical properties are limited by using a codoping method of both p and n type impurities. As described in the rejections of claim 7 and 14 above, Wang-2 and Nakai teach that the conditions to make substrates with the properties as claimed is known in the art and the claimed impurity concentrations could be arrived at by the ordinary artisan through routine experimentation and optimization.
Applicant also argues that the prior art does not teach a substrate with resistivity of 14-17 Ωcm with both n-type and p-type impurities. Similar to the above limitation, the Applicant teaches that the benefit of the substrates is that both n-type and p-type impurities lead to smaller variation in resistivity. The Applicant does not provide evidence that a range of 14-17 is critical to providing a benefit or leads to an unexpected result. Wang-2 and Nakai both teach similar methods in which crystals that can be used as substrates are made in which doping with both n-type and p-type impurities leads to small variations of resistivity in which the resistivity can be tuned to be lower (Wang-2) or higher (Nakai) than the claimed resistivity. As described in the rejections of claim 7 and 14 above, Wang-2 and Nakai teach that the conditions to make substrates with the properties as claimed is known in the art and the claimed resistivities could be arrived at by the ordinary artisan in crystals with both p-type and n-type impurities through routine experimentation and optimization.
The arguments are therefore found unpersuasive.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897