Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Song et al. (US 9,887,210).
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Regarding Claim 17: Song et al. discloses a semiconductor device comprising: a standard cell (annotated Fig 5B above and Figs 6A-D, MODIFIED STD1, MODIFIED STD2) including active patterns (FN1, FN2, see- [Col 11 lines 22,26-27]) extending in a first direction (D2), gate patterns (GP), extending in a second direction (D1) perpendicular to the first direction, first contact patterns (CA) being on the active patterns (see [Col 13 lines 44-55], "contact patterns CA connected to each of the PMOSFET region PR and the NMOSFET region NR") at opposite sides of the gate patterns (CA patterns are on opposite sides of GP in the D2 direction), and second contact patterns (CB) on the gate patterns (GP); interconnection line patterns (M2, PL1, PL2) extending in the first direction (D2) on the standard cell (MODIFIED STD2) and arranged in the second direction (D1); and via patterns (V2) electrically connecting the first contact patterns (CA) and the interconnection line patterns (M2, PL1, PL2) to each other, wherein the interconnection line patterns (M2, PL1, PL2) comprise a first power interconnection line pattern (PL1) and a second power interconnection line pattern (PL2) both extending in the first direction (D2), and the first power interconnection line pattern (see [Col 14 lines 14-17], "PL1 is electrically connected to the source/drain contact CA of the PMOSFET region PR through
the second via V2, and thus a drain voltage (VDD, i.e., a power voltage)") and the second power
interconnection line pattern (see [Col 14 lines 20-23]"PL2 is electrically connected to the source/drain contact CA of the NMOSFET region NR through the second via V2, and thus a source voltage (VSS, i.e., a ground voltage) ) are configured to supply different voltages (power and ground), respectively, to the standard cell (MODIFIED STD2), and are side by side (side by side is interpreted as next to each other in the image) with each other, wherein the standard cell (MODIFIED STD1, MODIFIED STD2) comprises a first standard cell (MODIFIED STD2) and a second standard cell (MODIFIED STD1), and the first standard cell (MODIFIED STD2) and the second standard cell (MODIFIED STD1) are between the first power interconnection line pattern (PL1) and the second power interconnection line pattern (PL2) and partially overlap each other to define a cell sharing region (see annotated figure of cell sharing region in Fig 5B), wherein the active patterns (FN1, FN2) comprise a first active pattern (FN1) in the first standard cell (MODIFIED STD2) and a second active pattern (FN2) in the second standard cell (MODIFIED STD1), and the first contact patterns (CA) comprise a first sharing contact pattern (CA) on
the first active pattern (FN1) and a second sharing contact pattern (another CA on FN2) on the second active pattern (FN2), in the cell sharing region (the cell sharing region in the annotated figure 5B), wherein the via patterns (( V1, V2 are vias) electrically connecting the first contact patterns (CA) and the interconnection line patterns (M1, M2) to each other), wherein the via patterns (V1,V2) comprise a first via pattern (V2) on the first sharing contact pattern (CA) and a second via pattern (V2) on the second sharing contact pattern (another of the shown structures CA) in the cell sharing region wherein the first via pattern (V2) is in a region in which the first sharing contact pattern (CA) overlaps the first power (PL1, or VDD) interconnection line pattern, and wherein the second via pattern (V2) is in a region in which the second sharing contact pattern (CA) overlaps the second power interconnection line pattern (PL2, or VSS); and wherein the first via pattern (V2) and the second via pattern (V2) do not overlap the active patterns (FN1, FN2) and the gate patterns (GP) (See fig. 6C which show via (V2) do not overlap the active patterns (FN1, FN2) and gate patterns (GP)).
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Regarding claim 18: Song et al. teaches the semiconductor device of claim 17, wherein the interconnection line patterns (M2, PL1, PL2) further comprise signal interconnection line patterns (M2) extending in the first direction (D2) between the first power interconnection line pattern (PL1) and the second power interconnection line pattern (PL2), and the signal interconnection line patterns (M2) comprise a rearrangement interconnection line pattern (M2) that is electrically connected to a corresponding one of the first contact patterns (CA), in a region outside the cell sharing region (see cell sharing region in Fig 5B annotated).
Regarding claim 19: Song et al. teaches the semiconductor device of claim 18, wherein the rearrangement interconnection line pattern (M2) is spaced apart from a boundary of the cell sharing region. (In annotated Fig 5B, M2 interconnection line is spaced apart from a boundary sharing region between standard cells MODIFIED STD1 and MODIFIED STD2).
Regarding claim 20: Song et al. teaches the semiconductor device of claim 17, wherein the first sharing contact pattern (CA connected to PL1) is configured to transmit a first voltage (positive reference voltage from PL1) that has been transmitted from the first power interconnection line pattern (PL1) to each of the first (MODIFIED STD2) and second standard cells (MODIFIED STD1), and wherein the second sharing contact pattern (another CA connected to PL2) is configured to transmit a second voltage (reference ground voltage, PL2) that has been transmitted from the second power interconnection line pattern (PL2) to each of the first (MODIFIED STD2) and second (MODIFIED STD1) standard cells.
Allowable Subject Matter
Claims 1-16 are allowed.
Response to Arguments
Applicant's arguments filed 10/14/25 have been fully considered but they are not persuasive. It is urged, in page 11 of the remarks, that Song et al. does not show the first via pattern (V2) and the second via pattern (V2) do not overlap the active patterns (FN1, FN2) and the gate patterns (GP). However, as shown in fig. 6C of Song et al., it shows vias (V2) do not overlap the active patterns (FN1, FN2) and the gate patterns (GP).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
