DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/11/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over NOH et al. (US PG Pub 2021/0407956, hereinafter Noh) in view of Appel et al. (US PG Pub 2006/0192300, hereinafter Appel).
Regarding claim 1, figure 1 of Noh discloses a semiconductor package, comprising:
a substrate (130) including substrate pads (131);
a first semiconductor chip (110) mounted on the substrate, the first semiconductor chip including first chip pads (115), wherein the first chip pads are disposed adjacent to a lateral surface in a first (X) direction of the first semiconductor chip and are arranged in a second (Y) direction, the second direction is orthogonal to the first direction, and each substrate pad of the substrate pads is located in the first direction from the semiconductor chip and arranged in the second direction along the lateral surface of the first cemiconductor chip; and
a first wire group (151/145/155) that connects the substrate pads to the first chip pads, the first wire group including a first power/ground wire (155), a first signal wire (151), a second signal wire (151), and a second power/ground wire (145) that are arranged in the first direction along the lateral surface in the second direction of the first semiconductor chip, wherein the first signal wire and the second signal wire each connect a substrate pad of the substrate pads (131) to a first chip pad of the first chip pads (115).
Noh does not explicitly disclose a first top end of the first signal wire is closer horizontally to the first chip pads than is a second top end of the second signal wire.
In the same field of endeavor, figures 3 and 4 of Appel disclose a first top end of a first signal wire (316) is closer horizontally to first chip pads (on chip 310) than is a second top end of a second signal wire (314).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the first signal wire with a top end closer to the first chip pads than a second top end of the second signal wire as taught by Appel for the purpose of minimizing mutual coupling and crosstalk (¶ 4-5).
Regarding claim 2, figures 3 and 4 of Appel disclose the second top end of the second signal wire (314) is closer horizontally to the substrate pads than is the first top end of the first signal wire (316).
Regarding claim 3, figures 3 and 4 of Appel disclose a first angle between the first signal wire (316) and a top surface of one of the first chip pads (on chip 310) is greater than a second angle between the second signal wire (314) and a top surface of another of the first chip pads.
Regarding claim 4, figures 3 and 4 of Appel disclose a third angle between the first signal wire (316) and a top surface of one of the substrate pads is less than a fourth angle between the second signal wire (314) and a top surface of another of the substrate pads.
Regarding claim 6, figure 1 of Noh discloses a top end of the first power/ground wire (155) is closer horizontally to the first semiconductor chip than is a top end of the second power/ground wire (145).
Regarding claim 9, figure 1 of Noh discloses a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including second chip pads; and
a second wire group that connects the substrate pads to the second chip pads, the second wire group including a third power/ground wire (145), a third signal wire (153), a fourth signal wire (153), and a fourth power/ground wire (145) that are arranged in the second direction that is orthogonal to the first direction.
Regarding claim 10, figure 1 of Noh discloses when viewed laterally, a gap between the third signal wire and the fourth signal wire is greater than a gap between the first signal wire and the second signal wire.
Note: The device includes a number of different signal wires (153), and the appropriate wire can be used to read on the claimed third and fourth signal wires such that the required gap is met.
Regarding claim 11, figure 1 of Noh discloses a molding layer that covers the first semiconductor chip and the second semiconductor chip (¶ 58).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Noh.
Regarding claim 7, Noh does not explicitly disclose when viewed laterally, a gap between the first signal wire and the second signal wire is in a range of about 0.1 mm to about 2 mm.
However, it would have been obvious to form the wires with a gap within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 8, Noh does not explicitly disclose a length of the first signal wire and a length of the first power/ground wire are less than a length of the second signal wire and a length of the second power/ground wire.
However, it would have been obvious to form the wires with lengths that satisfy the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-17 are allowed.
Regarding claim 12, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a substrate; a plurality of semiconductor chips that are disposed in an offset stack structure along a first direction on the substrate; a plurality of bonding wires that connect one of the plurality of semiconductor chips to the substrate; and a molding layer that covers the plurality of semiconductor chips on the substrate, wherein the plurality of bonding wires include first wire groups and second wire groups that are alternately arranged in a second direction that is orthogonal to the first direction, where each of the first and second wire groups includes a signal wire and a power/ground wire, wherein, in each of the first wire groups, the signal wire is disposed in the second direction of the power/ground wire, wherein, in each of the second wire groups, the signal wire is disposed in a direction opposite to the second direction of the power/ground wire, and wherein, in the first wire group and the second wire group that are adjacent to each other in the second direction, a first top end of the signal wire of the first wire group is shifted in the first direction from a second top end of the signal wire of the second wire group”.
Response to Arguments
Applicant's arguments filed 5/11/2026 have been fully considered but they are not persuasive.
Applicants argue that Appel shows the bonding points of the die and substrate are arranged at different intervals and thus the bond points (322, 324) are provided at different distances and thus Appel does not describe the substrate pad in the claimed arrangement.
However, the claimed “arranged in a/the second direction” does not require elements to collinear. For example, if there were two rows of people standing adjacent to but on opposite sides of a fence, both rows of people can be considered as arranged in the direction that the fence is running. Thus, the prior art is taken as teaching the chip pads and substrate pads arranged in the second direction in the claimed manner.
For at least the aforementioned reasons, the rejection is deemed proper.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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