Prosecution Insights
Last updated: May 29, 2026
Application No. 18/052,416

SEMICONDUCTOR PACKAGE INCLUDING FIDUCIAL MARK

Non-Final OA §103
Filed
Nov 03, 2022
Priority
Nov 26, 2021 — RE 10-2021-0166049
Examiner
NGUYEN, KHIEM D
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsungelectronicsco Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1896 granted / 2213 resolved
+17.7% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
40 currently pending
Career history
2267
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.8%
+29.8% vs TC avg
§102
17.5%
-22.5% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2213 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Preliminary Amendment The preliminary amendment filed on November 18th, 2022 has been entered. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The IDS filed on November 03rd, 2022 and December 10th, 2025 have been considered. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor package including a semiconductor chip and fiducial marks. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10, 12, 13, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (U.S. Pub. 2005/0253275) in view of Jones et al. (U.S. Pub. 2020/0027841). In re claim 10, Hsu discloses a semiconductor package, comprising: a substrate (see paragraph [0007] and figs. 1A-B); and at least one first semiconductor chip 110 on the substrate 120, wherein the substrate 120 comprises: a body layer 120 that has a top surface and a bottom surface; at least two first fiducial marks 126 on the top surface of the body layer 120 (see paragraph [0007] and figs. 1A-B); and a first protection layer 128 on at least edges of each of the at least two first fiducial marks 126 (see paragraph [0007] and figs. 1A-B), the first protection layer 128 having first openings 128b that each expose a respective top surface of the at least two first fiducial marks 126 (see paragraph [0007] and figs. 1A-B), wherein each of the at least two first fiducial marks 126 comprises at least one first mark exposure portion (central portion of the first fiducial marks 126 that is not being covered by the first protection layer 128) that is exposed without being covered by the first protection layer 128 (see paragraph [0007] and figs. 1A-B). PNG media_image1.png 415 633 media_image1.png Greyscale PNG media_image2.png 360 704 media_image2.png Greyscale Hsu is silent to wherein, when viewed in plan, each of the at least one first mark exposure portion comprises a first circular segment and at least one cavity inside the first circular segment, and wherein the at least one cavity of each of the at least one first mark exposure portion has a radially symmetric shape. However, Jones discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a substrate; and at least one first semiconductor chip 150 on the substrate, wherein the substrate comprises: a body layer 110 that has a top surface and a bottom surface; a fiducial mark (220,230) on the top surface of the body layer 110 (see paragraphs [0019], [0020], [0022] and fig. 2); wherein, when viewed in plan, each of the at least one first mark exposure portion comprises a first circular segment and at least one cavity inside the first circular segment, and wherein the at least one cavity of each of the at least one first mark exposure portion has a radially symmetric shape (see paragraphs [0040], [0047] and figs. 5, 6, and 7A-C, note that, Jones discloses that the fiducial mark 230 (see figs. 5 and 6) and fiducial mark 720 (see fig. 7B) may be configured as a ring shape, note that, the ring shape fiducial mark, when viewed in plan, comprises a first circular segment and at least one cavity inside the first circular segment as shown in figs. 5, 6, and 7A-C). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jones into the semiconductor package of Hsu in order to enable when viewed in plan, each of the at least one first mark exposure portion comprises a first circular segment and at least one cavity inside the first circular segment, and wherein the at least one cavity of each of the at least one first mark exposure portion has a radially symmetric shape in Hsu to be formed in order to increase in accuracy and precision of positioning the semiconductor chip with respect to the substrate (see paragraph [0034] of Jones). Additionally, it is respectfully submitted that, the configuration regarding about the shape of the at least two first fiducial marks was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)). In re claim 12, as applied to claim 10 above, Hsu in combination with Jones discloses wherein the substrate 120 comprises four corners, and wherein each of the at least two first fiducial marks 126 is adjacent to one of the four corners of the substrate 120 (see paragraph [0007] and fig. 1A of Hsu). In re claim 13, as applied to claim 10 above, Hsu in combination with Jones discloses wherein at least two of the first mark exposure portions have different shapes from each other (see paragraph [0047] and fig. 7B of Jones, the first fiducial mark 720 is of a ring shape and the second fiducial mark 730 is of a cross shape). In re claim 16, as applied to claim 10 above, Hsu and Jones are silent to wherein the semiconductor package further comprising at least one second semiconductor chip below the substrate, wherein the substrate further comprises: at least two second fiducial marks on the bottom surface of the body layer; and a second protection layer on at least edges of each of the at least two second fiducial marks, the second protection layer having second openings that each expose a respective top surface of the at least two second fiducial marks, wherein each of the at least two second fiducial marks comprises at least one second mark exposure portion that is exposed without being covered by the second protection layer, wherein, when viewed in plan, each of the at least one second mark exposure portion comprises a second circular segment and at least one cavity inside the second circular segment, and wherein the at least one cavity of each of the at least one second mark exposure portion has a radially symmetric shape. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, based on the teachings of Hsu and Jones that formed the first semiconductor chip and the at least two first fiducial marks on the top surface of the body layer to form at least one second semiconductor chip below the substrate, wherein the substrate further comprises: at least two second fiducial marks on the bottom surface of the body layer; and a second protection layer on at least edges of each of the at least two second fiducial marks, the second protection layer having second openings that each expose a respective top surface of the at least two second fiducial marks, wherein each of the at least two second fiducial marks comprises at least one second mark exposure portion that is exposed without being covered by the second protection layer, wherein, when viewed in plan, each of the at least one second mark exposure portion comprises a second circular segment and at least one cavity inside the second circular segment, and wherein the at least one cavity of each of the at least one second mark exposure portion has a radially symmetric shape in the semiconductor package of Hsu because the technique merely involves of duplication of parts and it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention since it has been held that mere duplication of the essential working parts of a device involves only routine skills in the art. St. Regis Paper Co. v. Bemis Co.. 183 USPQ 8. In re claim 18, as applied to claim 10 above, Hsu in combination with Jones discloses wherein the first mark exposure portions have the same shape as each other (see paragraph [0007] and fig. 1A of Hsu) but is silent to wherein the first mark exposure portions have different sizes from each other. However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first mark exposure portions to have different sizes from each other since a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04. Claim(s) 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (U.S. Pub. 2005/0253275) in view of Jones et al. (U.S. Pub. 2020/0027841), as applied to claim 10 above, and further in view of Dong et al. (U.S. Patent 11,079,522). In re claim 11, as applied to claim 10 above, Hsu and Jones are silent to wherein the at least one cavity of each of the first mark exposure portions has a width of about 200 µm to about 280 µm, and wherein each of the first mark exposure portions has a width of about 300 µm to about 400 µm. However, Dong discloses in a same field of endeavor, a semiconductor package, including, inter-alia, wherein the at least one cavity of each of the first mark exposure portions of the fiducial mark has a width of about 3 mm (about 3,000 µm), and wherein each of the first mark exposure portions has a width of about 4mm (about 4,000 µm) (see col. 8, lines 13-33 and fig. 5A). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Dong into the semiconductor package of Hsu to optimize during routine experimentation the width of the at least one cavity of each of the first mark exposure portions to be about 200 µm to about 280 µm and the width of each of the first mark exposure portions to be about 300 µm to about 400 µm since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). In re claim 17, as applied to claim 10 above, Hsu and Jones are silent to wherein each of the first mark exposure portions further comprises a second circular segment inside the at least one cavity or a cross segment inside the at least one cavity, wherein the cross segment or the second circular segment of each of the first mark exposure portions has a radially symmetric shape. However, Dong discloses in a same field of endeavor, a semiconductor package, including, inter-alia, wherein each of the first mark exposure portions of the fiducial mark further comprises a second circular segment 503 inside the at least one cavity and wherein the second circular segment 503 of each of the first mark exposure portions has a radially symmetric shape (see col. 8, lines 13-34 and fig. 5A). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Dong into the semiconductor package of Hsu in order to enable the first mart exposure to further comprises a second circular segment inside the at least one cavity wherein the second circular segment of each of the first mark exposure portions has a radially symmetric shape in Dong to be formed in order to improve precision alignment of components on the substrate (see col. 2, lines 22-33 of Dong). Allowable Subject Matter Claims 1-9 and 19-20 are allowed over prior art of record. Claims 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Reasons For Allowance The following is an examiner’s statement of reasons for allowance: It is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of independent claims 1 and 19 as a whole taken alone or in combination, in particular, prior art of record does not teach “wherein, when viewed in plan, each of the at least one first mark exposure portion comprises a first circular segment and at least four first protruding segments that outwardly protrude from the first circular segment", as recited in independent claim 1 and “wherein, when viewed in plan, each of the at least one first mart exposure portion comprises a first circular segment and four first protruding segments that outwardly protrude from the first circular segment”, as recited in independent claim 19. Claims 2-9 and 20 also allowed as being directly or indirectly dependent of the allowed independent base claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Min et al. (U.S. Pub. 2022/0037265) discloses a semiconductor package 10 include a first fiducial mark 420 and a second fiducial mark 430 disposed on the package substrate 100 (see paragraphs [0037], [0039] and fig. 1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Nov 03, 2022
Application Filed
Apr 27, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 2213 resolved cases by this examiner. Grant probability derived from career allowance rate.

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