DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant is advised that the Notice of Allowability dated 03/09/2026 has been withdrawn. A new Office action includes the non-final rejection of the claims under Yun (US 2019/0067308 A1) and Choi et al. (U.S 2022/0068859 A1) are provided below:
It should be noted that: the foreign document (REPUBLIC OF KOREA 10-2021-0174208) was not translated into English; therefore, its filing date (12/07/2021) cannot be used as a priority date for the present invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-9 and 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yun (U.S 2019/0067308 A1).
Regarding claim 1, Yun discloses in Fig. 10 a semiconductor memory device, comprising:
a cell array structure (“memory cell array” 50f) comprising first bonding pads (UM1, UMC1, UMC3), which are electrically connected to memory cells (“memory cell array”/“memory cells”, para. [0006], [0039], [0065]) (Fig. 10, para. [0110]-[0111]); and
a peripheral circuit structure (PERI) comprising second bonding pads (PM1-PM3; PMC1-PMC3), which are electrically connected to peripheral circuits (“one or more peripheral transistors” 22 include peripheral circuits) and are bonded to the first bonding pads (PM3 is bonded to UM1 by UMC1) (Fig. 10, para. [0114]-[0115]), wherein the cell array structure (“memory cell array” 50f) comprises: a stack (GS) comprising horizontal conductive patterns (WL1-WL8) stacked in a vertical direction (vertical y-direction) (Fig. 10, para. [0110]-[0112]);
a vertical structure (collection of UMC2) comprising vertical conductive patterns (each individual UMC2), which intersect the stack (GS) in the vertical direction (Fig. 10, para. [0111]); and
a power capacitor (the upper substrate “U_SUB” may function as “a power-capacitor”, para. [0077]) in a planarization insulating layer (34) on a portion of the stack (GS) (see Fig. 10, para. [0077]).
Regarding claim 2, as applied to claim 1 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein the power capacitor (the upper substrate “U_SUB” may function as “a power-capacitor”, para. [0077]) comprises: a first metal pattern (“first upper substrate” 42 may constitute a “lower electrode” of the capacitor, para. [0063]) in an opening in the planarization insulating layer (34); a second metal pattern (“second upper substrate” 46 may constitute an “upper electrode” of the capacitor, para. [0063]) on the first metal pattern (“first upper substrate” 42); and a dielectric material pattern (“the first layer” 44 may constitute a
“dielectric layer” of the capacitor, para. [0063]) between the first metal pattern (“first upper substrate” 42) and the second metal pattern (“second upper substrate” 46) (Fig. 10, para. [0063]).
Regarding claim 3, as applied to claims 1 and 2 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein, a height of the first metal pattern (“first upper substrate” 42) along the vertical direction is smaller than a thickness of the stack (GS) along the vertical direction (Fig. 10).
Regarding claim 4, as applied to claims 1 and 2 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein the first metal pattern (“first upper substrate” 42) and the second metal pattern (“second upper substrate” 46) are electrically connected to a subset of the first bonding pads (UM1, UMC1, UMC3) {see Fig. 10, para. [0054], [0075], [0093], [0094], the first metal pattern (42) and the second metal pattern (46) are electrically connected to a subset of the first bonding pads (UM1, UMC1, UMC3) by "the fourth peripheral contact" PMC4 and PM3}.
Regarding claim 8, as applied to claim 1 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein: the cell array structure (“memory cell array” 50f) comprises a bit line connection region (region of “bit lines” BL), a word line connection region (region of “word lines” WL1-WL8), and a first peripheral region (region in PERI), the stack (GS) has a staircase structure in the word line connection region (see Fig. 10), the vertical conductive patterns (each individual UMC2) intersect the horizontal conductive patterns (WL1-WL8), in the bit line connection region (region of “bit lines” BL) (Fig. 10), and the planarization
insulating layer (34) is in the word line connection region (region of “word lines” WL1-WL8) and the first peripheral region (region in PERI) (Fig 10).
Regarding claim 9, as applied to claim 1 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein the cell array structure (“memory cell array” 50f) comprises a bit line connection region (region of “bit lines” BL), a word line connection region (region of “word lines” WL1-WL8), and a first peripheral region (region in PERI) comprising the power capacitor (the upper substrate “U_SUB” may function as “a power-capacitor”, para. [0077]) (Fig. 10, para. [0077]), and wherein the first bonding pads (UM1, UMC1, UMC3) comprise: first upper bonding pads (each individual UMC3) in the bit line connection region (region of “bit lines” BL) and electrically connected to the vertical conductive patterns (each individual UMC2) (Fig. 10, para. [0073], [0075]); second upper bonding pads (each individual UM1) in the word line connection region (region of “word lines” WL1-WL8) and electrically connected to the horizontal conductive patterns (WL1-WL8) (Fig. 10, para. [0110]-[0112]); and one or more third upper bonding pads (UMC1) in the first peripheral region (region of PERI) and electrically connected to the power capacitor (the upper substrate “U_SUB” may function as “a power-capacitor”, para. [0077]) (Fig. 10, para. [0075], [0093]).
Regarding claim 11, as applied to claim 1 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein: the horizontal conductive patterns (WL1-WL8) of the stack (GS) comprise word lines (para. [0027], [0068], [0110]), which are parallel to a first surface of a lower insulating layer (“insulation layer” 52f), and the vertical conductive patterns (each individual UMC2) of the vertical structure (collection of UMC2) comprise bit lines (BL),
which are perpendicular to the first surface of the lower insulating layer (“insulation layer” 52f)
{see Fig. 10, para. [0112], the bit line BL has a vertical component (i.e., the side portions of BL) that are perpendicular to layer 52f}.
Regarding claim 12, as applied to claims 1 and 11 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein: the cell array structure (“memory cell array” 50f) comprises semiconductor patterns (“channel layer” 57f/57, para. [0122]), which are three-dimensionally disposed, and respective ones of the word lines (WL1-WL8) face or intersect top and bottom surfaces of respective ones of the semiconductor patterns (“channel layer” 57f/57, para. [0122]) (Fig. 10, para. [0122]).
Regarding claim 13, as applied to claims 1, 11 and 12 above, Yun discloses in Fig. 10 all claimed limitations including the limitation: wherein the cell array structure (“memory cell array” 50f) further comprises data storage elements (Fig. 10: each memory device 10/10f includes a “capacitor”) (Fig. 10, para. [0063], [0077], [0086]-[0087], [0106]).
Claim(s) 6, 10, 14-16, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Choi et al. (U.S 2022/0068859 A1).
Regarding claim 6, Choi et al. disclose in Fig. 16 a semiconductor memory device, comprising: a cell array structure (CS) comprising first bonding pads (comprising LMP1-LMP3 & LM1-LM3), which are electrically connected to memory cells (MC) (Fig. 16, para. [0040],
[0045], [0094], [0103]); and a peripheral circuit structure (PS) comprising second bonding pads (UMP1-UMP3), which are electrically connected to peripheral circuits (“sub-word line driver” SWD) and are bonded to the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) (Fig. 16, para. [0050], [0091]-[0092], [0116]), wherein the cell array structure (CS) comprises: a stack (stack of plural WL) comprising horizontal conductive patterns (each individual WL) stacked in a vertical direction (Fig. 16, para. [0045]-[0046]); a vertical structure (plural WPLG or plural BL) comprising vertical conductive patterns (each individual “word line contact plug” WPLG or BL), which intersect the stack (stack of plural WL) in the vertical direction (Fig. 16, para. [0093], [0101]); and a power capacitor (PC) in a planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) on a portion of the stack (stack of plural WL) (Fig. 16, para. [0102], [0120]);
wherein the cell array structure (CS) further comprises an input/output plug (“lower penetration plug” TSVa) that penetrates the planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) and is electrically connected to one of the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) (Fig. 16, para. [0119]);
the semiconductor memory device (Fig. 16) further comprising: a lower insulating layer
(101) having a first surface (bottom surface) and a second surface (top surface), which are opposite to each other (Fig. 16, para. [0065]); and an input/output pad (IOPa) on the first surface (bottom surface) of the lower insulating layer (101) and is electrically connected to the input/output plug (“lower penetration plug” TSVa) (Fig. 16, para. [0118]-[0119]), wherein the stack (stack of plural WL) is on the second surface (top surface) of the lower insulating layer
(101) (see Fig. 16).
Regarding claim 10, Choi et al. disclose in Fig. 16 a semiconductor memory device, comprising: a cell array structure (CS) comprising first bonding pads (comprising LMP1-LMP3 & LM1-LM3), which are electrically connected to memory cells (MC) (Fig. 16, para. [0040], [0045], [0094], [0103]); and a peripheral circuit structure (PS) comprising second bonding pads (UMP1-UMP3), which are electrically connected to peripheral circuits (“sub-word line driver” SWD) and are bonded to the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) (Fig. 16, para. [0050], [0091]-[0092], [0116]), wherein the cell array structure (CS) comprises: a stack (stack of plural WL) comprising horizontal conductive patterns (each individual WL) stacked in a vertical direction (Fig. 16, para. [0045]-[0046]); a vertical structure (plural WPLG or plural BL) comprising vertical conductive patterns (each individual “word line contact plug” WPLG or BL), which intersect the stack (stack of plural WL) in the vertical direction (Fig. 16, para. [0093], [0101]); and a power capacitor (PC) in a planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) on a portion of the stack (stack of plural WL) (Fig. 16, para. [0102], [0120]);
wherein the cell array structure (CS) comprises a bit line connection region (BLB) (Fig. 16, para. [0096]-[0097], [0102], [0103], [0113], [0115]-[0116]), a word line connection region (WLB) (Fig. 16, para. [0046]-[0048]), and a first peripheral region (PR1) comprising the power capacitor (PC) (Fig. 16, para. [0039], [0102]), and wherein the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) comprise: first upper bonding pads (LMP1) in the bit line connection region (BLB) and electrically connected to the vertical conductive patterns (each individual “word line contact plug” WPLG or BL) (Fig. 16, para. [0047], [0051]); second upper bonding pads (LMP2) in the word line connection region (WLB) and electrically connected to the horizontal conductive patterns (each individual WL) (Fig. 16, para. [0047], [0051]); and one
or more third upper bonding pads (LMP3) in the first peripheral region (PR1) and electrically connected to the power capacitor (PC) (Fig. 16, para. [0113], [0115]-[0116]);
wherein the peripheral circuit structure (PS) comprises a first core region (CR1) that overlaps with the bit line connection region (BLB) in the vertical direction (Fig. 16) (Fig. 16, para. [0048]), a second core region (CR2) that overlaps with the word line connection region (WLB) in the vertical direction (Fig. 16, para. [0048]), and a second peripheral region (PR2) that overlaps with the first peripheral region (PR1) in the vertical direction (Fig. 16, para. [0039]),
and wherein the second bonding pads (UMP1-UMP3) comprise: first lower bonding pads (UMP1), which are in the first core region (CR1), are electrically connected to sense amplifiers (SA), and are bonded to the first upper bonding pads (LMP1) (Fig. 16, para. [0112]-[0116], [0041]-[0042], [0049]-[0050], [0086], [0094], [0106]-[0107], [0110]); second lower bonding
pads (UMP2), which are in the second core region (CR2), are electrically connected to sub-word line drivers (SWD), and are bonded to the second upper bonding pads (LMP2) (Fig. 16, para
.[0005], [0041]-[0042], [0091, [0109]); and one or more third lower bonding pads (UMP3), which are in the second peripheral region (PR2), are electrically connected to control circuits (PP), and are bonded to the one or more third upper bonding pads (LMP3) (Fig. 16, para. [0094], [0104], [0110]-[0111]).
Regarding claim 14, Choi et al. disclose in Fig. 16 a semiconductor memory device, comprising: a cell array structure (CS) comprising first bonding pads (comprising LMP1-LMP3 & LM1-LM3), which are electrically connected to memory cells (MC) (Fig. 16, para. [0040], [0045], [0094], [0103]); and a peripheral circuit structure (PS) comprising second bonding pads (UMP1-UMP3), which are electrically connected to peripheral circuits (“sub-word line driver”
SWD) and are bonded to the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) (Fig. 16, para. [0050], [0091]-[0092], [0116]), wherein the cell array structure (CS) comprises: a stack (stack of plural WL) comprising horizontal conductive patterns (each individual WL) stacked in a vertical direction (Fig. 16, para. [0045]-[0046]); a vertical structure (plural WPLG or plural BL) comprising vertical conductive patterns (each individual “word line contact plug” WPLG or BL), which intersect the stack (stack of plural WL) in the vertical direction (Fig. 16, para. [0093], [0101]); and a power capacitor (PC) in a planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) on a portion of the stack (stack of plural WL) (Fig. 16, para. [0102], [0120]);
wherein: the horizontal conductive patterns (each individual WL) of the stack (stack of plural WL) comprise word lines (WL), which are parallel to a first surface of a lower insulating layer (101) (Fig. 16, para. [0045], [0056]), and the vertical conductive patterns (each individual “word line contact plug” WPLG or BL) of the vertical structure (plural WPLG or plural BL) comprise bit lines (BL), which are perpendicular to the first surface of the lower insulating layer
(101) (Fig. 16, para. [0064], [0075], [0099]);
wherein: the cell array structure (CS) comprises semiconductor patterns (SP, Fig. 7), which are three-dimensionally disposed, and respective ones of the word lines (WL) face or intersect top and bottom surfaces of respective ones of the semiconductor patterns (SP, Fig. 7) (Fig. 7, para. [0061]-[0063], [0065]-[0067]);
wherein the cell array structure (CS) further comprises data storage elements (each individual CAP, Fig. 7) on first side surfaces of the semiconductor patterns (SP) (Fig. 7, para. [0066]-[0067]);
wherein the data storage elements (each individual CAP, Figs. 6A, 7) comprise: storage node electrodes (“storage electrodes” SE, Fig. 6A), which are in contact with the first side surfaces of the semiconductor patterns (SP), respectively (see Fig. 6A, para. [0067]-[0069]); a plate electrode (PE) on the storage node electrodes (SE) (Fig. 6A, para. [0068]-[0069]); and a capacitor dielectric layer (“dielectric layer” IL) between the plate electrode (PE) and the storage node electrodes (SE) (Fig. 16, para. [0068]-[0069]).
Regarding claim 15, Choi et al. disclose in Fig. 16 a semiconductor memory device, comprising:
a cell array structure (CS) comprising first bonding pads (comprising LMP1-LMP3 & LM1-LM3) electrically connected to memory cells (MC) (Fig. 16, para. [0040], [0045], [0094]); and
a peripheral circuit structure (PS) comprising second bonding pads (UMP1-UMP3) electrically connected to peripheral circuits (“sub-word line driver” SWD) and bonded to the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) (Fig. 16, para. [0050], [0091]-[0092], [0116]), wherein the cell array structure (CS) comprises:
a lower insulating layer (101) having a first surface (top surface) and a second surface (bottom surface), which are opposite to each other (Fig. 16, para. [0065]); a stack (stack of plural WL) comprising horizontal conductive patterns (each individual WL), which are stacked on the first surface (top surface) of the lower insulating layer (101) (Fig. 16, para. [0045]-[0046]);
a vertical structure (plural WPLG or plural BL) comprising vertical conductive patterns (each individual “word line contact plug” WPLG or BL) penetrating the stack (stack of plural WL) (Fig. 16, para. [0093], [0101]);
a power capacitor (PC) in a planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) on the stack (stack of plural WL) (Fig. 16, para. [0102], [0120]);
an input/output plug (“lower penetration plug” TSVa) penetrating the planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) (Fig. 16, para. [0119]); and
an input/output pad (IOPa) on the second surface (bottom surface) of the lower insulating layer (101) and electrically connected to the input/output plug (“lower penetration plug” TSVa) (Fig. 16, para. [0118]-[0119]), wherein the power capacitor (PC) is between the first bonding pads (LMP1-LMP3) and the input/output pad (IOPa), when viewed in a vertical section (Fig.
16).
Regarding claim 16, as applied to claim 15 above, Choi et al. disclose in Fig. 16 all claimed limitations including the limitation: wherein the power capacitor (PC) comprises: a first metal pattern (M1), which is conformally extends along a plurality of openings (a “plurality of openings” corresponding to M1, M2 & MI or a “plurality of openings” corresponding plurality of PLG, Fig. 16) in the planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16); second metal patterns (M2), which are respectively provided in the plurality of openings (a “plurality of openings” corresponding to M1, M2 & MI or a “plurality of openings” corresponding plurality of PLG, Fig. 16) having the first metal pattern (M1) therein (Fig. 16); and a dielectric material pattern (MI) between the first metal pattern (M1) and the second metal patterns (M2) (Fig. 16, para. [0102]).
Regarding claim 18, as applied to claim 15 above, Choi et al. disclose in Fig. 16 all claimed limitations including the limitation: wherein: the cell array structure (CS) comprises semiconductor patterns (SP, Fig. 7), which are three-dimensionally disposed on the first surface of the lower insulating layer (101, Fig. 16) (Figs. 7 & 16, para. [0060]-[0067]), and data storage elements (each individual CAP, Fig. 7), which are on first side surfaces of the semiconductor patterns (SP, Fig. 7) (Fig. 7, para. [0066]-[0067]), and respective ones of the horizontal conductive patterns (each individual WL) face or intersect top and bottom surfaces of respective ones of the semiconductor patterns (SP, Fig. 7) (Fig. 7, para. [0063]).
Regarding claim 19, Choi et al. disclose in Fig. 16 a semiconductor memory device, comprising:
a cell array structure (CS) comprising first bonding pads (comprising LMP1-LMP3 & LM1-LM3) electrically connected to memory cells (MC) (Fig. 16, para. [0040], [0045], [0094]) in a cell array region (Fig. 16, para. [0040], [0094]), and
a first peripheral region (PR1) that is adjacent the cell array region (CS includes a cell array region) (Fig. 16, para. [0039], [0042]); and
a peripheral circuit structure (PS) comprising second bonding pads (UMP1-UMP3) electrically connected to peripheral circuits (“upper control circuits” PP) and bonded to the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) (Fig. 10, para. [0110]-[0111]), the peripheral circuit structure (PS) comprising a first core region (CR1) that overlaps with a bit line connection region (BLB) in a vertical direction (Fig. 16, para. [0039], [0044]-[0048], [0086]), a second core region (CR2) that overlaps with a word line connection region (WLB) in the vertical direction (Fig. 16, para. [0039], [0044], [0046]-[0048], [0086]), and a second peripheral region
(PR2) that overlaps with the first peripheral region (PR1) in the vertical direction (Fig. 16, para. [0039], [0042]),
wherein the cell array structure (CS) comprises:
a lower insulating layer (101) having a first surface (top surface) and a second surface (bottom surface), which are opposite to each other (Fig. 16);
a stack (stack of plural WL) comprising word lines (WL) that are in the cell array region and are stacked on the first surface (top surface) of the lower insulating layer (101) in the vertical direction (Fig. 16, para. [0044]-[0047], [0054] [0065]);
a vertical structure (comprising plurality of BL) comprising bit lines (BL) that are in the cell array region and penetrate the stack (stack of plural WL) (Fig. 16, para. [0026], [0045]-[0049]);
a planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) in the cell array region and the first peripheral region (PR1) and on the stack (stack of plural WL) (Fig. 16);
a power capacitor (PC) in the first peripheral region (PR1) and in the planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16), the power capacitor (PC) comprising a first metal pattern (M1) in an opening in the planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16), a second metal pattern (“second electrode” M2) on the first metal pattern (“ first electrode” M1), and a dielectric material pattern (“dielectric layer” MI) between the first metal pattern (“ first electrode” M1) and the second metal pattern (“second electrode” M2) (Fig. 16, para. [0102]);
an input/output plug (“lower penetration plug” TSVa) in the first peripheral region (PR1) and penetrating the planarization insulating layer (see an insulating layer that covers a stack of WL and PC, Fig. 16) (Fig. 16, para. [0119]); and
an input/output pad (IOPa) in the first peripheral region (PR1) and on the second surface (bottom surface) of the lower insulating layer (101) and electrically connected to the input/output plug (“lower penetration plug” TSVa) (Fig. 16, para. [0118]-[0119]).
Regarding claim 20, as applied to claim 19 above, Choi et al. disclose in Fig. 16 all claimed limitations including the limitation: wherein the first bonding pads (comprising LMP1-LMP3 & LM1-LM3) comprise: first upper bonding pads (LMP1), which are in the bit line connection region (BLB) and are electrically connected to the bit lines (BL) (Fig. 16, para. [0102], [0103], [0113], [0115]-[0116]); second upper bonding pads (LMP2), which are in the word line connection region (WLB) and are electrically connected to the word lines (WL) (Fig. 16, para. [0046]-[0048]); one or more third upper bonding pads (LMP3), which are in the first peripheral region (PR1) and are electrically connected to the power capacitor (PC) (Fig. 16, para. [0113], [0115]-[0116]), and wherein the second bonding pads (UMP1-UMP3) comprise: first lower bonding pads (UMP1), which are in the first core region (CR1), are electrically connected to sense amplifiers (SA), and are bonded to the first upper bonding pads (LMP1) (Fig. 16, para. [0112]-[0116], [0041]-[0042], [0049]-[0050], [0086], [0094], [0106]-[0107], [0110]); second
lower bonding pads (UMP2), which are in the second core region (CR2), are electrically connected to sub-word line drivers (SWD), and are bonded to the second upper bonding pads (LMP2) (Fig. 16, para .[0005], [0041]-[0042], [0091, [0109]); and one or more third lower bonding pads (UMP3), which are in the second peripheral region (PR2), are electrically
connected to control circuits (PP), and are bonded to the one or more third upper bonding pads (LMP3) (Fig. 16, para. [0094], [0104], [0110]-[0111]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C.
102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun (U.S 2019/0067308 A1) in view of Jeon et al. (U.S 2022/0344361 A1).
Regarding claim 5, as applied to claim 1 above, Yun discloses in Fig. 10 all claimed limitations including the memory device (10) comprising: the cell array structure (“memory cell array” 50f) and an input/output interface ( Fig, 10, para. [0026]).
Yun does not disclose the cell array structure further comprises an input/output plug that penetrates the planarization insulating layer and is electrically connected to one of the first bonding pads.
Jeon et al. disclose in Fig. 6A a memory device (Fig. 6A) comprising: a cell array structure (CS) comprises first bonding pads (comprising LCLa, LCLb, LCTa, LCTb, and BCT); wherein the cell array structure (CS) comprises an input/output plug (IOPLG, Fig. 6A) that penetrates the planarization insulating layer (120) and is electrically connected to one (“second connection contact plugs” LCTb or “conductive lines” LCLb/LCLa) of the first bonding pads
(comprising LCLa, LCLb, LCTa, LCTb, and BCT) (see Fig. 6A, para. [0050], [0073], [0076], [0077], [0079], the I/O plug IOPLG directly contacts one of the first bonding pads (LCLa, LCLb, LCTa, LCTb, and BCT), thus it is electrically connected to one of the first bonding pads).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Yun by having a cell array structure comprising an input/output plug that penetrates the planarization insulating layer and is electrically connected to one of the first bonding pads, as taught by Jeon et al., in order to enable communication between the memory device and external devices.
Allowable Subject Matter
Claims 7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached on M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/
Primary Examiner, Art Unit 2817
July 20, 2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights