DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
[0022-0025, 0034, 0038, 0044, 0050, 0052-0054, 0064, 0066-0067, 0070-0071] "accoridng" should be "according".
[0037] line 6 "blocksof" should be "blocks of".
[0027] line 21 “wrtie” should be “write”.
[0067] line 3 “coefficientz” should be “coefficients”.
[0052] describes “Further, as shown in FIG.5 to FIG. 12 … in each first writing procedure, the processing units 1401 to 1404 can read second coefficient storage blocks 1121 to 1228”. Such recitation is unclear because throughout the specification, the writing procedure would perform writing result to the memory, and the calculation procedure would perform reading from memory, see at least [0036-0037]. However, [0052] requires each first writing procedure to read second coefficient storage blocks.
The specification is also objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112(a) below.
Appropriate correction is required.
Claim Objections
Claims 3-4, 6-9, 11 and 12-20 are objected to because of the following informalities:
Claim 3 line 3 "a first coefficien" should be "a first coefficient".
Claim 4 line 3,6; claim 15 line 2-3, 5-6 “the one first coefficient” and “the one second coefficient” should be “the first coefficient” and “the second coefficient” as antecedently recited in claims 3 and 14
Claim 6 line 3, 7; claim 7 line 3, 7; claim 15 line 3, 6; claim 17 line 3, 6; claim 18 line 4, 9; claim 19 line 2, 6, 9, 12 "accoridng" should be "according".
Claim 11 line 5-6 “the
2
m
processing units blocks” should be “the
2
m
processing units” as antecedently recited.
Claim 12 line 2; claim 19 line 14 “the method” should be “the calculation method” as antecedently recited.
Claims 13-20 line 1 “The method” should be “The calculation method” as antecedently recited.
Claim 19 line 3 “the at least one first twiddle factor” should be “the first twiddle factor” as antecedently recited in claim 18 line 5.
Dependent claims are also objected for inheriting the same deficiencies in which claim they depend on.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) , is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) :
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) , is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) , is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) , except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) , except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) , because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
"
2
M
processing units" and “each processing unit” in claims 1, 3-7, and 11. Figures 1, 4 illustrates a plurality of processing unit operates in parallel, and figure 15 [0064] illustrates implementation of a processing unit having a modular multiplication unit, a modular addition unit, a modular subtraction unit, and a coefficient exchange unit, and figure 16 illustrates the implementation of the coefficient exchange unit. However, the modular multiplication unit, the modular addition unit, and the modular subtraction unit are illustrated as “black boxes” without sufficient structure to perform the claimed function of reading, writing, and performing modulo calculation as required in the claim.
“a modular multiplication unit” in claim 8. Figure 15 illustrates the modular multiplication unit 142 as “black box” without sufficient structure to perform the claimed function.
“a modular addition unit” in claim 8. Figure 15 illustrates the modular addition unit 144 as “black box” without sufficient structure to perform the claimed function.
“a modular subtraction unit” in claim 8. Figure 15 illustrates the modular subtraction unit 146 as “black box” without sufficient structure to perform the claimed function.
“a coefficient exchange unit” in claim 8. Figure 16 illustrates hardware implementation of the coefficient exchange unit 148.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) , it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) , applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) .
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 3-8, 11 recite "
2
M
processing units" and “each processing unit”, “a modular multiplication unit”, “a modular addition unit”, “a modular subtraction unit”, which invoke 112(f) interpretation. However, the specification fails to provide sufficient structure to perform the entire claimed functions. Figures 1, 4, and 15 illustrate a plurality of processing units operate in parallel, wherein each processing unit having implementation as illustrated in figure 15, where the modular multiplication unit 142, the modular addition unit 144, and modular subtraction unit 146 are illustrated as “black boxes” without sufficient structure to perform the claimed function.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 17 recite “in each round of first calculation procedure, each processing unit writes the two first output coefficients … in each round of second calculation procedure, each processing unit writes the two second output coefficients”. Such limitation renders the claim unclear because as recited antecedently, the first and second calculation procedures perform reading data from memory, and the first and second writing procedures write first and second output coefficients to memory. For examination purposes, Examiner interprets such limitation as “in each round of first writing procedure, each processing unit writes the two first output coefficients … in each round of second writing procedure, each processing unit writes the two second output coefficients
Claim 6 line 4 recites "the same address". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as "a same address".
Claim 7 line 3 recites "the two first coefficients". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as “two first coefficients”.
Claim 7 line 7 recites "the two second coefficients". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as “two second coefficients”.
Claim 8 line 5 and claim 19 line 6 recite “the first twiddle factors”. There is lack of antecedent basis for such limitation as the claim does not antecedently recite a plurality of twiddle factors. For examination purposes, Examiner interprets as “the first twiddle factor” as antecedently recited.
Claim 12 line 18 recites “the second coefficient memory”. There is lack of antecedent basis for such limitation. Examiner interprets as “a second coefficient memory”.
Claim 17 line 2-3 and line 5-6 recite “the two first output coefficients” and “the two second output coefficients”. There is lack of antecedent basis for such limitations. For examination purposes, Examiner interprets such limitation as “two first output coefficients” and “two second output coefficients”.
Claims 1, 3-8, 11 recite "
2
M
processing units" and “each processing unit”, “a modular multiplication unit”, “a modular addition unit”, “a modular subtraction unit”, which invoke 112(f) interpretation. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. See explanation in 112(b) above. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims are also rejected for inheriting the same deficiencies in which claim they depend on.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the claim objection and rejections under 35 U.S.C. 112(a) and 112(b), set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1 and 12, the prior art of records does not teach or suggest a combination of limitations, including 2M processing units, configured to perform N rounds of coefficient computation operations in parallel, wherein M is an integer greater than 1 and smaller than N; and a data flow controller, configured to control access addresses of the 2M processing units for accessing the first coefficient memory, the second coefficient memory and the twiddle factor memory; wherein: in each odd-number round of the N rounds of coefficient computation operations: the 2M processing units perform 2(N-M-1) rounds of first calculation procedures to read 2N first coefficients from the first coefficient memory, read at least one first twiddle factor from the twiddle factor memory, and perform a modulo calculation; and the 2M processing units perform 2(N-M-1) rounds of first writing procedures to write 2N first output coefficients generated during computation to the second coefficient memory; and in each even-number round of the N rounds of coefficient computation operations: the 2M processing units perform 2(N-M-1) rounds of second calculation procedures to read 2N second coefficients from the second coefficient memory, read at least one second twiddle factor from the twiddle factor memory, and perform a modulo calculation; and the 2M processing units perform 2(N-M-1) rounds of second writing procedures to write 2N second output coefficients generated during computation to the first coefficient memory.
Razmhah – NPL SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics – teaches a hardware accelerator for NTT having a plurality of processing elements each featuring a butterfly unit (BU), dual memory coefficients operating in ping-pong mode, and twiddle factor buffers as illustrated in figure 2, wherein the NTT design with 128 points and the data flow in the NTT 128 point design follows a pipeline structure, progressing from the first PE to the last PE. Each PE comprises two coefficient memories, each with N slots operating in a ping-pong manner to store all intermediate results to avoid WAR hazards since the read and write addresses of the coefficients are different. However, Razmhah does not teach or suggest the limitations required in claims 1 and 12 as described above.
Ghosh – US 20220006611 teaches an apparatus for performing number theoretic transform (NTT) algorithm on an input polynomial that is store in an input register, wherein the NTT is performed by a plurality of computing nodes as illustrated in figure 5. However, Ghosh does not teach or suggest the limitations required in claims 1 and 12 as described above.
Bisheh Niasar – US 20240413995 teaches an apparatus for performing NTT algorithm as described in figure 5 that includes a polynomial memory 550, a twiddle factor memory 552, wherein the polynomial memory 550 stores coefficients of polynomials to be converted to the NTT domain, which is being input to the butterfly operation circuit, where the order of the coefficient is illustrated in figure 6. Figure 5 also illustrates rearrange circuit 560 and 562 that can organize the coefficient so the butterfly can receive the coefficients in proper order. However, Bisheh Niasar does not teach or suggest different coefficient memories that operate in a ping pong manner for odd and even round of operation as required in the claims 1 and 12 as described above.
Niasar – US 20250247217 teaches circuit for performing NTT computation having a plurality of butterfly circuits operating in parallel that receives coefficients of polynomial of memory 440 and twiddle factors from memory 496 to generate results, which are stored in the buffer 482 and being feedback as the input. However, Niasar does not teach or suggest different coefficient memories that operate in a ping pong manner for odd and even round of operation as required in the claims 1 and 12 as described above.
Kwon – US 20230171084 teaches an apparatus includes a first memory configured to receive and store a polynomial; a second memory configured to store a twiddle factor; a number theoretic transform (NTT) module configured to perform an NTT operation on the polynomial based on the twiddle factor; and a controller configured to control the first memory, the second memory, and the NTT module, wherein the NTT module comprises a butterfly unit (BU) array that comprises a plurality of BUs configured to, for the performing of the NTT operation, perform a modular operation on coefficients of the polynomial. However, Kwon does not teach different coefficient memories that operate in a ping pong manner for odd and even round of operation as required in the claims 1 and 12 as described above.
Therefore, the prior art of records does not teach or suggest the combination of limitations as required in claims 1 and 12.
Conclusion
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
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