DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Status of claim(s) to be treated in this office action:
Independent: 1, 8 and 15.
Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,5, 15 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu (US 20220344301 A1) in view of Jacobs (US 20190237418 A1, hereinafter Jacobs).
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Re: Independent Claim 1, Yu discloses a semiconductor structure (60/60’ in [0005], Fig. 10) comprising:
Yu’s Figure 10-Annotated.
a first semiconductor wafer (24/28/32 a substrate 24, an inter-Layer Dielectric 28 and interconnect structure 32 in [0016, 0018], Fig. 10) and a second semiconductor wafer (124/128/132 a substrate 124, an inter-Layer Dielectric 128 and interconnect structure 132 in [0027], Fig. 10); and
a bonding structure (42/142 a dielectric layer 42, a dielectric layer 142 in [0023], Fig. 10-Annotated) between the first semiconductor wafer (24/28/32, Fig. 10) and the second semiconductor wafer (124/128/132, Fig. 10),
where the bonding structure (42/142, Fig. 10) comprises a first pad (50 a bond pad in [0045], Fig. 10) embedded (Fig. 10-Annotated) in a first dielectric layer (42 a dielectric layer in [0023], Fig. 10) and a second pad (150 a bond pad in [0045], Fig. 10) embedded in a second dielectric layer (142 a dielectric layer in [0023], Fig. 10), and the first pad (50, Fig. 10) is substantially aligned ([0044], Fig. 10-Annotated) with the second pad (150, Fig. 10).
Yu does not expressly disclose wherein the first pad and the second pad are coaxial pads.
However, in the same semiconductor device field of endeavor, Jacobs discloses a coaxial pad (116 coaxial interconnect in a ring shape formed by a signal core 214 made of copper, insulator 218 and ground shield 216 made of copper in [0032], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jacobs’s feature of a coaxial pad to Yu’s device to have the bonding structure comprises a first coaxial pad embedded in a first dielectric layer and a second coaxial pad embedded in a second dielectric layer, and the first coaxial pad is substantially aligned with the second coaxial pad to accommodate high-speed frequencies and improve signal performance of the semiconductor component ([0003], Jacobs).
Re: Claim 5, Yu modified by Jacobs discloses the semiconductor structure of claim 1, wherein the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) and the second coaxial pad (Jacobs’s 116 applied to Yu’150 in Jacobs: [0032], Fig. 2) have substantially same shapes and are made of copper (Cu) (Jacobs: 116 in a ring shape formed by a signal core 214 and ground shield 216 made of copper in [0032], Fig. 2).
Re: Independent Claim 15, Yu discloses a method ([0005], Figs. 6-10) comprising:
forming a first semiconductor chip (24/28/32 a substrate 24, an inter-Layer Dielectric 28 and interconnect structure 32 in [0016, 0018], Figs. 6-10);
forming a first dielectric layer (42 a dielectric layer in [0023], Figs. 6-10) on the first semiconductor chip (24/28/32, Figs. 6-10), the first dielectric layer (42, Figs. 6-10) having at least a first pad (50 a bond pad in [0045], Figs. 6-10) embedded (Figs. 6-10) therein;
forming a second semiconductor chip (124/128/132 a substrate 124, an inter-Layer Dielectric 128 and interconnect structure 132 in [0027], Figs. 6-10);
forming a second dielectric layer (142 a dielectric layer in [0023], Figs. 6-10) on the second semiconductor chip (124/128/132, Figs. 6-10), the second dielectric layer (142, Figs. 6-10) having at least a second pad (150 a bond pad in [0045], Figs. 6-10) embedded (Figs. 6-10) therein; and
bonding the first dielectric layer (42, Figs. 6-10) with the second dielectric layer (142, Figs. 6-10) and causing the first pad (50, Figs. 6-10) in the first dielectric layer (42, Figs. 6-10) to be substantially aligned ([0044], Figs. 9-10) with the second pad (150, Figs. 6-10) in the second dielectric layer (142, Figs. 6-10).
Yu does not expressly disclose wherein the first pad and the second pad are coaxial pads.
However, in the same manufacturing of a semiconductor device field of endeavor, Jacobs discloses a coaxial pad (116 coaxial interconnect in a ring shape formed by a signal core 214 made of copper, insulator 218 and ground shield 216 made of copper in [0032], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jacobs’s method of manufacturing of a coaxial pad to Yu’s method to have the first dielectric layer having at least a first coaxial pad embedded therein; forming a second semiconductor chip; forming a second dielectric layer on the second semiconductor chip, the second dielectric layer having at least a second coaxial pad embedded therein; and bonding the first dielectric layer with the second dielectric layer and causing the first coaxial pad in the first dielectric layer to be substantially aligned with the second coaxial pad in the second dielectric layer to accommodate high-speed frequencies and improve signal performance of the semiconductor component ([0003], Jacobs).
Re: Claim 20, Yu modified by Jacobs discloses the method of claim 15, wherein the first (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) and second coaxial pads (Jacobs’s 116 applied to Yu’150 in Jacobs: [0032], Fig. 2) are made of copper (Cu) (Jacobs: 116 formed by a signal core 214 and ground shield 216 made of copper in [0032], Fig. 2) and the first (Yu: 42, Fig. 10) and second (Yu: 142, Fig. 10) dielectric layers are silicon-oxide (SiO2) layers (Yu: 42/142 made of silicon-oxide in [0022], Fig. 10).
Claim(s) 2-4 and 18-19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Jacobs and further in view of Hsu et al. (US 20240071987 A1, hereinafter Hsu).
Re: Claim 2, Yu modified by Jacobs discloses the semiconductor structure of claim 1, wherein the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) includes a first inner pad (Jacobs’s 214 in Jacobs: [0032], Fig. 2) and a first outer pad (Jacobs’s 216 in Jacobs: [0032], Fig. 2), the first inner pad (Jacobs’s 214, Fig. 2) has a substantially circular shape (Jacobs: [0032], Fig. 2), and the first outer pad (Jacobs’s 216, Fig. 2) has a substantially ring shape (Jacobs: [0032], Fig. 2) surrounding the first inner pad (Jacobs’s 214, Fig. 2).
Yu modified by Jacobs does not expressly disclose wherein the first outer pad has a substantially rectangular ring shape to have different distances to the first inner pad along a periphery of the first outer pad.
However, in the same semiconductor device field of endeavor, Hsu discloses an outer pad (210/211 metal nanoparticles surrounding the conductive pads 225 in rectangle shape in [0036], Fig. 3) having a substantially rectangular ring shape (210/211 having a square/rectangle shape in [0036], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of an outer pad having a substantially rectangular ring shape to the combination of Yu and Jacobs to have the first outer pad has a substantially rectangular ring shape to have different distances to the first inner pad along a periphery of the first outer pad to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Re: Claim 3, Yu modified by Jacobs discloses the semiconductor structure of claim 1, wherein the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) includes a first inner pad (Jacobs’s 214 in Jacobs: [0032], Fig. 2) and a first outer pad (Jacobs’s 216 in Jacobs: [0032], Fig. 2), and the first outer pad (Jacobs’s 216, Fig. 2) has a substantially ring shape (Jacobs: [0032], Fig. 2) surrounding the first inner pad (Jacobs’s 214, Fig. 2).
Yu modified by Jacobs does not expressly disclose wherein the first inner pad has a substantially rectangular shape and the first outer pad has a substantially rectangular ring shape to have a substantially same distance to the first inner pad along a periphery of the first outer pad.
However, in the same semiconductor device field of endeavor, Hsu discloses an inner pad (Hsu: 225 conductive pad in [0026], Fig. 3) has a substantially rectangular shape (Hsu: 225 having a rectangle shape in [0035], Fig. 3) an outer pad (210/211 metal nanoparticles surrounding the conductive pads 225 in rectangle shape in [0036], Fig. 3) having a substantially rectangular ring shape (210/211 having a square/rectangle shape in [0036], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of an inner pad having a substantially rectangular shape and an outer pad having a substantially rectangular ring shape to the combination of Yu and Jacobs to have the first inner pad has a substantially rectangular shape, and the first outer pad has a substantially rectangular ring shape surrounding the first inner pad to have a substantially same distance to the first inner pad along a periphery of the first outer pad to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Re: Claim 4, Yu modified by Jacobs discloses the semiconductor structure of claim 1, wherein the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) includes a first inner pad (Jacobs’s 214, Fig. 2) and a first outer pad (Jacobs’s 216, Fig. 2), and wherein the first dielectric layer (Yu: 42 a dielectric layer in [0023], Fig. 10) is a silicon-oxide (SiO2) (Yu: in [0022]) layer surrounding the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2),
Yu modified by Jacobs does not expressly disclose wherein the first dielectric layer in-between the first inner pad and the first outer pad.
However, in the same semiconductor device field of endeavor, Hsu discloses a dielectric layer (120 dielectric layer in [0020], Fig. 2) in-between (Hsu: Fig. 2) the first inner pad (Hsu: 225 conductive pad in [0026], Fig. 2) and the first outer pad (210 metal nanoparticles surrounding the conductive pads 225 in [0036], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of the first dielectric layer in-between the first inner pad and the first outer pad to the combination of Yu and Jacobs to have wherein the first dielectric layer is a silicon-oxide (SiO2) layer surrounding the first coaxial pad and in-between the first inner pad and the first outer pad to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Re: Claim 18, Yu modified by Jacobs discloses the method of claim 15, wherein the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) includes a first inner pad (Jacobs’s 214 in Jacobs: [0032], Fig. 2) and a first outer pad (Jacobs’s 216 in Jacobs: [0032], Fig. 2), the first inner pad (Jacobs’s 214, Fig. 2) has a substantially circular shape (Jacobs: [0032], Fig. 2), and the first outer pad (Jacobs’s 216, Fig. 2) has a substantially ring shape (Jacobs: [0032], Fig. 2) surrounding the first inner pad (Jacobs’s 214, Fig. 2).
Yu modified by Jacobs does not expressly disclose wherein the first outer pad has a substantially rectangular ring shape.
However, in the same manufacturing of a semiconductor device field of endeavor, Hsu discloses an outer pad (210/211 metal nanoparticles surrounding the conductive pads 225 in rectangle shape in [0036], Fig. 3) having a substantially rectangular ring shape (210/211 having a square/rectangle shape in [0036], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of an outer pad having a substantially rectangular ring shape to the combination of Yu and Jacobs to have the first outer pad has a substantially rectangular ring shape to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Re: Claim 19, Yu modified by Jacobs discloses the method of claim 15, wherein the first coaxial pad (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) includes a first inner pad (Jacobs’s 214 in Jacobs: [0032], Fig. 2) and a first outer pad (Jacobs’s 216 in Jacobs: [0032], Fig. 2), and the first outer pad (Jacobs’s 216, Fig. 2) has a substantially ring shape (Jacobs: [0032], Fig. 2) surrounding the first inner pad (Jacobs’s 214, Fig. 2).
Yu modified by Jacobs does not expressly disclose wherein the first inner pad has a substantially rectangular shape and the first outer pad has a substantially rectangular ring shape.
However, in the same manufacturing of a semiconductor device field of endeavor, Hsu discloses an inner pad (Hsu: 225 conductive pad in [0026], Fig. 3) has a substantially rectangular shape (Hsu: 225 having a rectangle shape in [0035], Fig. 3) an outer pad (210/211 metal nanoparticles surrounding the conductive pads 225 in rectangle shape in [0036], Fig. 3) having a substantially rectangular ring shape (210/211 having a square/rectangle shape in [0036], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of an inner pad having a substantially rectangular shape and an outer pad having a substantially rectangular ring shape to the combination of Yu and Jacobs to have the first inner pad has a substantially rectangular shape, and the first outer pad has a substantially rectangular ring shape surrounding the first inner pad to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Jacobs in view of Arifeen (US 20220037258 A1, hereinafter Arifeen) and further in view of Li et al. (US 20200006145 A1, hereinafter Li).
Re: Claim 6, Yu modified by Jacobs disclose the semiconductor structure of claim 1, wherein the second semiconductor wafer (Yu: 124/128/132 in [0027], Fig. 10) at a backside thereof includes a redistribution layer (RDL) (Yu: 132 in [0027], Fig. 10),
Yu modified by Jacobs disclose does not expressly disclose wherein the first semiconductor wafer at a frontside thereof includes a back-end-of-line (BEOL) structure and wherein the bonding structure bonds the BEOL structure of the first semiconductor wafer directly with the RDL of the second semiconductor wafer.
However, in the same semiconductor device field of endeavor, Arifeen discloses a semiconductor chip (200 semiconductor device in [0027], Fig. 5) having a first back-end-of-line (BEOL) structure (Arifeen: 200 having an assembly 204b including a BEOL structure in [0027], Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Arifeen’s feature of a semiconductor chip having a first back-end-of-line (BEOL) structure to the combination of Yu and Jacobs to have the first semiconductor wafer at a frontside thereof includes a back-end-of-line (BEOL) structure to allow the semiconductor die to be connected to higher level circuitry ([0002], Arifeen).
Yu modified by Arifeen and Jacobs does not expressly disclose wherein the bonding structure bonds the BEOL structure of the first semiconductor wafer directly with the RDL of the second semiconductor wafer.
However, in the same semiconductor device field of endeavor, Li discloses wherein the bonding structure (108 bonding structure in [0029], Fig. 2-Annotated) bonds a back side of the first semiconductor wafer (102d a semiconductor wafer in [0033], Fig. 2) directly with the RDL (metal layers connected with transistors in 2D IC 104c in [0029], Fig. 2) of the second semiconductor wafer (102e a semiconductor wafer in [0033], Fig. 2).
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Li’s Figure 2-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Li’s feature wherein the bonding structure bonds the first semiconductor wafer directly with the RDL of the second semiconductor wafer to the combination of Yu, Arifeen and Jacobs to have the bonding structure bonds the BEOL structure of the first semiconductor wafer directly with the RDL of the second semiconductor wafer to improve the structural support between the first semiconductor wafer and the second semiconductor wafer ([0026], Li).
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Jacobs and further in view of Farooq (US 20100289144 A1, hereinafter Farooq).
Re: Claim 7, Yu modified by Jacobs disclose the semiconductor structure of claim 1,
Yu modified by Jacobs disclose does not expressly disclose wherein the first semiconductor wafer at a frontside thereof includes a first back-end-of-line (BEOL) structure and the second semiconductor wafer at a frontside thereof includes a second BEOL structure, and wherein the bonding structure bonds the first BEOL structure of the first semiconductor wafer directly with the second BEOL structure of the second semiconductor wafer.
However, in the same semiconductor device field of endeavor, Farooq discloses
the first semiconductor wafer (12/14 semiconductor wafers 12 and BEOL 14 in [0048], Fig. 3) at a frontside thereof includes a first back-end-of-line (BEOL) structure (14 BEOL wirings in [0048], Fig. 3) and the second semiconductor wafer (22/24 semiconductor wafers 22 and BEOL 24 in [0048], Fig. 3) at a frontside thereof includes a second BEOL structure (24 BEOL wirings in [0048], Fig. 3), and wherein the bonding structure (26/28/18/16 insulator layers 16, 26 and metallic layers 18, 28 in [0048], Fig. 3) bonds the first BEOL structure (14, Fig. 3) of the first semiconductor wafer (12/14, Fig. 3) directly with the second BEOL structure (24, Fig. 3) of the second semiconductor wafer (22/24, Fig. 3).
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Farooq’s Figure 3-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Farooq’s feature of the first semiconductor wafer at a frontside thereof includes a first back-end-of-line (BEOL) structure and the second semiconductor wafer at a frontside thereof includes a second BEOL structure, and wherein the bonding structure bonds the first BEOL structure of the first semiconductor wafer directly with the second BEOL structure of the second semiconductor wafer to the combination of Yu and Jacobs to improve the bonding process to the three dimensional (3D) integrated circuits ([0001], Farooq).
Claim(s) 8 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Arifeen and further in view of Jacobs.
Re: Independent Claim 8, Yu discloses a semiconductor structure (60/60’ in [0005], Fig. 10) comprising:
a first semiconductor chip (24/28/32 a substrate 24, an inter-Layer Dielectric 28 and interconnect structure 32 in [0016, 0018], Fig. 10);
a second semiconductor chip (124/128/132 a substrate 124, an inter-Layer Dielectric 128 and interconnect structure 132 in [0027], Fig. 10) having a backside with a redistribution layer (RDL) (132 an interconnect structure in [0027], Fig. 10); and
a bonding structure (42/142 a dielectric layer 42, a dielectric layer 142 in [0023], Fig. 10-Annotated) between the first semiconductor chip (24/28/32, Fig. 10) and the second semiconductor chip (124/128/132, Fig. 10),
where the bonding structure (42/142, Fig. 10) comprises a first dielectric layer (42 a dielectric layer in [0023], Fig. 10) with at least a first pad structure (50 a bond pad in [0045], Fig. 10) embedded (Fig. 10-Annotated) therein and a second dielectric layer (142 a dielectric layer in [0023], Fig. 10) with at least a second pad structure (150 a bond pad in [0045], Fig. 10) embedded (Fig. 10-Annotated) therein, and wherein the first pad structure (50, Fig. 10) is substantially aligned ([0044], Fig. 10) with the second pad structure (150, Fig. 10).
Yu does not expressly disclose a first semiconductor chip having a first back-end-of-line (BEOL) structure, a second semiconductor chip having a frontside with a second BEOL structure and wherein the first pad structure includes a first inner pad and a first outer pad.
However, in the same semiconductor device field of endeavor, Arifeen discloses a semiconductor chip (200 semiconductor device in [0027], Fig. 5) having a first back-end-of-line (BEOL) structure (Arifeen: 200 having an assembly 204b including a BEOL structure in [0027], Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Arifeen’s feature of a semiconductor chip having a first back-end-of-line (BEOL) structure to Yu’s first and second semiconductor chip to have a first semiconductor chip having a first back-end-of-line (BEOL) structure, a second semiconductor chip having a frontside with a second BEOL structure to allow the semiconductor die to be connected to higher level circuitry ([0002], Arifeen).
Yu modified by Arifeen does not expressly disclose wherein the first pad structure includes a first inner pad and a first outer pad.
However, in the same semiconductor device field of endeavor, Jacobs discloses
a pad structure (116 coaxial interconnect in a ring/circular shape formed by a signal core 214 made of copper, insulator 218 and ground shield 216 made of copper in [0032], Fig. 2) including an inner pad (Jacobs: a signal core 214 made of copper in [0032], Fig. 2) and an outer pad (Jacobs: a ground shield 216 made of copper in [0032], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jacobs’s feature of a first pad structure includes a first inner pad and a first outer pad to the combination of Yu and Arifeen to accommodate high-speed frequencies and improve signal performance of the semiconductor component ([0003], Jacobs).
Re: Claim 12, Yu modified by Arifeen and Jacobs discloses the semiconductor structure of claim 8, wherein the first pad structure (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2) in the first dielectric layer (Yu: 42, Fig. 10) and the second pad structure (Jacobs’s 116 applied to Yu’150 in Jacobs: [0032], Fig. 2) in the second dielectric layer (Yu: 142, Fig. 10) have substantially same shapes and are made of copper (Cu) (Jacobs: 116 in a ring shape formed by a signal core 214 and ground shield 216 made of copper in [0032], Fig. 2).
Claim(s) 9 - 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Arifeen in view of Jacobs and further in view of Hsu.
Re: Claim 9, Yu modified by Arifeen and Jacobs discloses the semiconductor structure of claim 8, wherein the first inner pad (Jacobs’s 214, Fig. 2) has a substantially circular shape (Jacobs: [0032], Fig. 2), and the first outer pad (Jacobs’s 216, Fig. 2) has a substantially ring shape (Jacobs: [0032], Fig. 2) surrounding the first inner pad (Jacobs’s 214, Fig. 2).
Yu modified by Arifeen and Jacobs does not expressly disclose wherein the first outer pad has a substantially rectangular ring shape.
However, in the same semiconductor device field of endeavor, Hsu discloses an outer pad (210/211 metal nanoparticles surrounding the conductive pads 225 in rectangle shape in [0036], Fig. 3) having a substantially rectangular ring shape (210/211 having a square/rectangle shape in [0036], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of an outer pad having a substantially rectangular ring shape to the combination of Yu and Jacobs to have the first outer pad has a substantially rectangular ring shape to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Re: Claim 10, Yu modified by Arifeen and Jacobs discloses the semiconductor structure of claim 8, the first outer pad (Jacobs’s 216, Fig. 2) has a substantially ring shape (Jacobs: [0032], Fig. 2) surrounding the first inner pad (Jacobs’s 214, Fig. 2).
Yu modified by Arifeen and Jacobs does not expressly disclose wherein the first inner pad has a substantially rectangular shape, and the first outer pad has a substantially rectangular ring shape surrounding the first inner pad.
However, in the same semiconductor device field of endeavor, Hsu discloses an inner pad (Hsu: 225 conductive pad in [0026], Fig. 3) has a substantially rectangular shape (Hsu: 225 having a rectangle shape in [0035], Fig. 3) an outer pad (210/211 metal nanoparticles surrounding the conductive pads 225 in rectangle shape in [0036], Fig. 3) having a substantially rectangular ring shape (210/211 having a square/rectangle shape in [0036], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of an inner pad having a substantially rectangular shape and an outer pad having a substantially rectangular ring shape to the combination of Yu, Arifeen and Jacobs to have the first inner pad has a substantially rectangular shape, and the first outer pad has a substantially rectangular ring shape surrounding the first inner pad to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Re: Claim 11, Yu modified by Arifeen, Jacobs and Hsu disclose the semiconductor structure of claim 10, wherein the first dielectric layer (Yu: 42 a dielectric layer in [0023], Fig. 10) is a silicon-oxide (SiO2) layer (Yu: in [0022]) surrounding the first pad structure (Jacobs’s 116 applied to Yu’50 in Jacobs: [0032], Fig. 2),
Yu modified by Arifeen, Jacobs and Hsu does not expressly disclose wherein
wherein the first dielectric layer in-between the first inner pad and the first outer pad.
However, in the same semiconductor device field of endeavor, Hsu discloses a dielectric layer (120 dielectric layer in [0020], Fig. 2) in-between (Hsu: Fig. 2) the first inner pad (Hsu: 225 conductive pad in [0026], Fig. 2) and the first outer pad (210 metal nanoparticles surrounding the conductive pads 225 in [0036], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature of the first dielectric layer in-between the first inner pad and the first outer pad to the combination of the combination of Yu, Arifeen and Jacobs to obtain wherein the first dielectric layer is a silicon-oxide (SiO2) layer surrounding the first coaxial pad and in-between the first inner pad and the first outer pad to mitigate risks associated with the thermal budget during the hybrid bonding process steps ([0017], Hsu).
Claim(s) 13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Arifeen in view of Jacobs and further in view of Li.
Re: Claim 13, Yu modified by Arifeen and Jacobs disclose the semiconductor structure of claim 8, wherein the bonding structure (Yu: 42/142, Fig. 10) bonds the first BEOL structure (Arifeen’s 204b BEOL applied to Yu, Arifeen: in [0027], Fig. 5) of the first semiconductor chip (Yu: 42/142, Fig. 10) with the RDL (Yu: 132 in [0027], Fig. 10) of the second semiconductor chip (Yu: 124/128/132 in [0027], Fig. 10) at the backside thereof.
Yu modified by Arifeen and Jacobs does not expressly disclose wherein the bonding structure bonds the first BEOL structure of the first semiconductor chip directly with the RDL of the second semiconductor chip.
However, in the same semiconductor device field of endeavor, Li discloses wherein the bonding structure (108 bonding structure in [0029], Fig. 2) bonds a back side of the first semiconductor chip (102d a semiconductor wafer in [0033], Fig. 2) directly with the RDL (metal layers connected with transistors in 2D IC 104c in [0029], Fig. 2) of the second semiconductor chip (102e a semiconductor wafer in [0033], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Li’s feature wherein the bonding structure bonds the first semiconductor chip directly with the RDL of the second semiconductor chip to the combination of Yu, Arifeen and Jacobs to have the bonding structure bonds the first BEOL structure of the first semiconductor chip directly with the RDL of the second semiconductor chip to improve the structural support between the first semiconductor wafer and the second semiconductor wafer ([0026], Li).
Claim(s) 14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Arifeen in view of Jacobs and further in view of Farooq.
Re: Claim 14, Yu modified by Arifeen and Jacobs disclose the semiconductor structure of claim 8,
Yu modified by Arifeen and Jacobs does not expressly disclose wherein the bonding structure bonds the first BEOL structure of the first semiconductor chip directly with the second BEOL structure of the second semiconductor chip at the frontside thereof.
However, in the same semiconductor device field of endeavor, Farooq discloses wherein a bonding structure (26/28/18/16 insulator layers 16, 26 and metallic layers 18, 28 in [0048], Fig. 3) bonds (Farooq, Fig. 3) the first BEOL structure (14 BEOL wirings in [0048], Fig. 3) of the first semiconductor chip (12/14 semiconductor wafers 12 and BEOL 14 in [0048], Fig. 3) directly with the second BEOL structure (24 BEOL wirings in [0048], Fig. 3) of the second semiconductor chip (22/24 semiconductor wafers 22 and BEOL 24 in [0048], Fig. 3) at the frontside (Farooq, Fig. 3) thereof.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Farooq’s feature of the bonding structure bonds the first BEOL structure of the first semiconductor chip directly with the second BEOL structure of the second semiconductor chip at the frontside thereof to the combination of Yu and Arifeen and Jacobs to improve the bonding process to the three dimensional (3D) integrated circuits ([0001], Farooq).
Claim(s) 16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Jacobs and further in view of Farooq.
Re: Claim 16, Yu modified by Jacobs discloses the method of claim 15, wherein the second semiconductor chip (Yu: 132 an interconnect structure in [0027], Fig. 10), at a backside thereof, includes a redistribution layer (RDL) (Yu: 132 an interconnect structure in [0027], Fig. 10),
Yu modified by Jacobs does not expressly disclose wherein the first semiconductor chip includes a first back-end-of-line (BEOL) structure and the second semiconductor chip, at a frontside thereof, includes a second BEOL structure and wherein forming the first dielectric layer includes forming the first dielectric layer directly on top of the first BEOL structure and forming the second dielectric layer includes forming the second dielectric layer directly on top of the second BEOL structure at the frontside of the second semiconductor chip.
However, in the same manufacturing of a semiconductor device field of endeavor, Farooq discloses wherein the first semiconductor chip (12/14 semiconductor wafers 12 and BEOL 14 in [0048], Fig. 3) includes a first back-end-of-line (BEOL) structure (Farooq: 14 BEOL wirings in [0048], Fig. 3) and the second semiconductor chip (Farooq: 22/24 semiconductor wafers 22 and BEOL 24 in [0048], Fig. 3), at a frontside thereof, includes a second BEOL structure (Farooq: 24 BEOL wirings in [0048], Fig. 3) and wherein forming the first dielectric layer (Farooq: 16 insulator layer in [0048], Fig. 3) includes forming the first dielectric layer (Farooq: 16, Fig. 3) directly on top of the first BEOL structure (Farooq: 14, Fig. 3) and forming the second dielectric layer (Farooq: 26 insulator layer in [0048], Fig. 3) includes forming the second dielectric layer (Farooq: 26, Fig. 3) directly on top of the second BEOL structure (Farooq: 24, Fig. 3) at the frontside of the second semiconductor chip (Farooq: 22/24, Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Farooq’s method wherein the first semiconductor chip includes a first back-end-of-line (BEOL) structure and the second semiconductor chip, at a frontside thereof, includes a second BEOL structure and wherein forming the first dielectric layer includes forming the first dielectric layer directly on top of the first BEOL structure and forming the second dielectric layer includes forming the second dielectric layer directly on top of the second BEOL structure at the frontside of the second semiconductor chip to the combination of Yu and Jacobs to improve the bonding process to the three dimensional (3D) integrated circuits ([0001], Farooq).
Claim(s) 17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu in view of Jacobs in view of Arifeen and further in view of Farooq.
Re: Claim 17, Yu modified by Jacobs discloses the method of claim 15, wherein the second semiconductor chip (Yu: 124/128/132, Fig. 10), at a backside thereof, includes a redistribution layer (RDL) (Yu: 132 an interconnect structure in [0027], Fig. 10), forming the second dielectric layer (Yu: 142, Fig. 10) includes forming the second dielectric layer (Yu: 142, Fig. 10) directly on top of the RDL (Yu: 132, Fig. 10) at the backside of the second semiconductor chip (Yu: 124/128/132, Fig. 10).
Yu modified by Jacobs does not expressly disclose wherein the first semiconductor chip includes a back-end-of-line (BEOL) structure and the second semiconductor chip, at a frontside thereof, includes a second BEOL structure and wherein forming the first dielectric layer includes forming the first dielectric layer directly on top of the first BEOL structure.
However, in the same manufacturing of a semiconductor device field of endeavor, Arifeen discloses a semiconductor chip (200 semiconductor device in [0027], Fig. 5) having a first back-end-of-line (BEOL) structure (Arifeen: 200 having an assembly 204b including a BEOL structure in [0027], Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Arifeen’s method of a semiconductor chip having a first back-end-of-line (BEOL) structure to the combination of Yu and Jacobs to have the first semiconductor chip includes a back-end-of-line (BEOL) structure and the second semiconductor chip, at a frontside thereof, includes a second BEOL structure to allow the semiconductor die to be connected to higher level circuitry ([0002], Arifeen).
Yu modified by Jacobs and Arifeen does not expressly disclose wherein forming the first dielectric layer includes forming the first dielectric layer directly on top of the first BEOL structure.
However, in the same manufacturing of a semiconductor device field of endeavor, Farooq discloses wherein forming the first dielectric layer (Farooq: 16 an insulator layer in [0048], Fig. 3) includes forming the first dielectric layer (Farooq: 16 an insulator layer in [0048], Fig. 3) directly (Farooq: Fig. 3) on top of the first BEOL structure (Farooq: 14 BEOL wirings in [0048], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Farooq’s method wherein forming the first dielectric layer includes forming the first dielectric layer directly on top of the first BEOL structure to the combination of Yu, Jacobs and Arifeen to improve the bonding process to the three dimensional (3D) integrated circuits ([0001], Farooq).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Park et al. (US 20220037273 A1) teaches “SEMICONDUCTOR PACKAGE FOR IMPROVING BONDING RELIABILITY”. This document is related to a semiconductor package including main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures.
Farooq et al. (US 20110168434 A1) teaches “BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING”. This document is related to vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898