DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and the corresponding claims 1-10 and 20 in the reply filed on 04/10/2026 is acknowledged.
Claims 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/10/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/09/2022 and 05/04/2026 was filed after the mailing date of the application on 11/09/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities:
Regarding claim 1; claim 1 contains the limitation: “… an substrate layer;…” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1, 4-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al, US 20230275084 A1 (Hong) in view of Chang et al, US 20220052168 A1 (Chang).
Regarding claim 1; Hong teaches a semiconductor device (Hong: Fig (1) shared in this OA for convenience: 10) comprising:
a substrate layer (108);
a transistor (100A) upon the substrate layer (108), the transistor (100A, 100B) includes both one or more channel regions (NP, [0037]: “… The nanosheet patterns NP may function as a channel structure of each of the transistors 100A and 100B”) and a first source or drain (S/D) region (S/D) upon the substrate layer (108), the first S/D region (S/D) connected to the one or more channel regions (NP, [0037]);
a backside S/D contact (CA+MV) connected to a top surface of the first S/D region (S/D), the backside S/D contact (CA+MV) comprising both a lateral portion (CA) that laterally extends adjacent to the first S/D region (S/D) and a vertical portion (MV) that extends vertically downward below the bottom surface of the substrate layer (108); and
a backside S/D mushroom that extends vertically downward below the vertical portion.
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Hong does not teach a backside S/D mushroom that extends vertically downward below the vertical portion.
Chang teaches a backside S/D mushroom (Chang: Annotated Fig (11): Mushroom Portion of the connector 230) that extends vertically downward below the vertical portion (Vertical Portion of the connector 230).
Hong and Chang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong by constructing the mushroom portion of the connector as disclosed in Chang to improve the electrical connection by reducing the contact resistance between the connector and the contact area in which it is embedded leading to a more efficient device.
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Regarding claim 4; Hong in view of Chang teaches all the limitations of the semiconductor device of claim 1.
Hong teaches further comprising: a shallow trench isolation (STI) region (Hong: Fig (1): 107) around the backside S/D contact (CA+MV) between the first S/D region (S/D) and the backside rail (101).
Regarding claim 5; Hong in view of Chang teaches all the limitations of the semiconductor device of claim 4.
Hong does not teach wherein the backside S/D reduces electrical impedance from the backside rail to the backside S/D contact.
Chang teaches wherein the backside S/D (Chang: Annotated Fig (11): 230) reduces electrical impedance from the backside rail to the backside S/D contact (230, the mushroom shape used by Chang is bound to increase the contact surface area of the S/D contact and thus will reduce the impedance).
Hong and Chang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong by using the mushroom shape of the contact to reduce the impedance of the S/D contact as disclosed in Chang leading to a more efficient device.
Regarding claim 8; Hong in view of Chang teaches all the limitations of the semiconductor device of claim 1.
Hong does not teach wherein the backside S/D contact is formed of a first conductive metal and the backside S/D mushroom is also formed of the first conductive metal.
Chang teaches wherein the backside S/D contact (Chang: Annotated Fig (11) shared in this OA: 230) is formed of a first conductive metal and the backside S/D mushroom (Mushroom Portion) is also formed of the first conductive metal (the process involves filling the via that holds the conductor 228 (seen in Fig (7)) which becomes 230 (seen in Fig (11)) with the same metal, [0023]: “…In some embodiments, the metal fill layer 228 may include tungsten (W) or ruthenium (Ru)”).
Hong and Chang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong by making the contact and the mushroom portion made of the same metal to simplify the device production process.
Claims 2-3, 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al, US 20230275084 A1 (Hong) in view of Chang et al, US 20220052168 A1 (Chang) in further view of Chu et al, US 20210399099 A1 (Chu).
Regarding claim 2; Hong in view of Chang teaches all the limitations of the semiconductor device of claim1.
Hong in view of Chang does not teach further comprising: a backside rail around the backside S/D mushroom.
Chu teaches further comprising: a backside rail (Chu: Fig (16) shared in this OA for convenience: 264) around the backside S/D mushroom (Mushroom Portion of S/D Contact).
Hong in view of Chang and Chu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong in view of Chang by using a backside rail around the S/D mushroom as disclosed in Chu to make establishing electrical connections through the device easier leading to a more efficient device production process.
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Regarding claim 3; Hong in view of Chang in further view of Chu teaches the semiconductor device of claim 2.
However, Hong in view of Chang does not teach wherein the backside rail comprises an internal conductive region and a conductive barrier liner between the internal conductive region and the backside S/D mushroom.
Chu teaches wherein the backside rail (Chu: Annotated Fig (16) shared in this OA: 264) comprises an internal conductive region (internal region of 264) and a conductive barrier liner (262) between the internal conductive region (internal region of 264) and the backside S/D mushroom (Mushroom Portion of S/D/ Contact).
Hong in view of Chang and Chu are considered analogous art Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong in view of Chang by using the structure of the backside rail and the backside mushroom S/D contact to improve the conductivity of the device leading to a more efficient device.
Regarding claim 6; Hong in view of Chang teaches all the limitations of the semiconductor device of claim 5.
Further, Hong teaches wherein the transistor (Hong: Fig (1): 100A,100B) is a gate all around nanosheet structure (NP) that includes a plurality of channel regions (NP) each surrounded by one work function metal gate.
Hong in view Chang does not gate all around nanosheet structure
Chu teaches gate (Chu: Annotated Fig (16) shared in this OA: 220) all around nanosheet structure ([0020]: “Gate structures 220 are then deposited over the channel regions 10C to wrap around each of the channel members 2080”.).
Hong in view of Chang and Chu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hing in view of Chang by constructing the gate such that it wraps around all the channel layers as disclosed in chu to improve control over the current passing through the channel thus leading to a more reliable device.
Hong in view of Cheng does not explicitly teach each surrounded by one work function metal gate.
Chu teaches each (Chu: Annotated Fig (16) shared in this OA: 218) surrounded by one work function metal gate ([0020]: “… The gate electrode layer 218 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer)…”).
Hong in view of Chang and Chu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong in view of Chang by using the work function metal layer as disclosed in Chu to improve the device performance.
Regarding claim 20; Hong teaches a transistor (Hong: Fig (1): 100A, 100B)comprising:
one or more channel regions (NP);
a single gate that is around each of the one or more channel regions (NP);
a source or drain (S/D) region (S/D) connected to the one or more channel regions (NP); and
a backside S/D contact (CA+MV) connected to a top surface of the S/D region (S/D), the backside S/D contact (CA+MV) comprising a lateral portion (CA) upon the top surface of the S/D region (S/D) and that laterally extends adjacent to the first S/D region (S/D), and a vertical portion (MV) that extends vertically downward from the lateral portion (CA) below the bottom surface of the substrate layer (108); and
a backside S/D mushroom that extends vertically downward from the vertical portion.
Hong does not teach a backside S/D mushroom that extends vertically downward below the vertical portion.
Chang teaches a backside S/D mushroom (Chang: Annotated Fig (11): Mushroom Portion of the connector 230) that extends vertically downward below the vertical portion (Vertical Portion of the connector 230).
Hong and Chang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong by constructing the mushroom portion of the connector as disclosed in Chang to improve the electrical connection by reducing the contact resistance between the connector and the contact area in which it is embedded leading to a more efficient device.
Hong in view of Chang does not explicitly teach a single gate that is around each of the one or more channel regions.
However, Chu teaches a single gate (Chu: Annotated Fig (16) shared in this OA: 220) that is around each of the one or more channel regions ([0020]: “Gate structures 220 are then deposited over the channel regions 10C to wrap around each of the channel members 2080”.).
Hong in view of Chang and Chu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hing in view of Chang by constructing the gate such that it wraps around all the channel layers as disclosed in chu to improve control over the current passing through the channel thus leading to a more reliable device.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al, US 20230275084 A1 (Hong) in view of Chang et al, US 20220052168 A1 (Chang) in further view of Stehr et al, DE 3802403 A1 (Stehr).
Regarding claim 9; Hong in view of Chang teach all the limitations of the semiconductor device of claim 1.
Hong does not teach wherein the backside S/D contact is formed of a first conductive metal and the backside S/D mushroom is formed of a second conductive metal with higher conductivity relative to the first conductive metal.
Chang teaches wherein the backside S/D contact (Chang: Annotated Fig (11) shared in this OA: 230) is formed of a first conductive metal (the process involves filling the via that holds the conductor 228 (seen in Fig (7)) which becomes 230 (seen in Fig (11)) with the same metal, [0023]: “…In some embodiments, the metal fill layer 228 may include tungsten (W) or ruthenium (Ru)”) and the backside S/D mushroom is formed of a second conductive metal with higher conductivity relative to the first conductive metal.
Hong and Chang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong by using a first metal to construct the S/D contact as disclosed in Chang to improve the conductivity of the contact leading to a more efficient device.
Hong in view of Chang does not teach the backside S/D mushroom is formed of a second conductive metal with higher conductivity relative to the first conductive metal.
Stehr teaches the backside S/D mushroom (Stehr: Figs (1c) and (2b): top part of 10) is formed of a second conductive metal with higher conductivity relative to the first conductive metal. (8, 10, “by producing a thin metal layer 8 which consists of a layer sequence of titanium-titanium tungsten-gold”, “This contact 10 is produced by electroplating, the metal layer 8 serving as an electrode.”
Hong in view of Chang and Stehr are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong in view of Chang by using a second metal to construct the mushroom portion of the S/D contact as disclosed in Stehr to improve the conductivity of the device leading to a more efficient device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al, US 20230275084 A1 (Hong) in view of Chang et al, US 20220052168 A1 (Chang) in further view of Chu et al, US 20210399099 A1 (Chu) in further view of Ham et al, US 20230326858 A1 (Ham).
Regarding claim 7; Hong in view of Chang in further view of Chu teaches all the limitations of the semiconductor device of claim 6.
Hong in view of Chang in further view of Chu does not teach wherein the vertical portion of the backside S/D contact is between adjacent gate cut regions.
Ham teaches wherein the vertical portion (Ham: Fig (6C): 116”) of the backside S/D contact is between adjacent gate cut regions (117’).
Hong in view of Chang in further view of Chu and Ham are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong in view of Chang in further view of Chu by using the gate cuts between the different vertical portions of the contacts as disclosed in Ham to improve the isolation of the different gate structures of the device leading to a more reliable device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al, US 20230275084 A1 (Hong) in view of Chang et al, US 20220052168 A1 (Chang) in further view of Kim et al, US 20230343839 A1 (Kim).
Regarding claim 10; Hong in view of Chang teaches all the limitations of the semiconductor device of claim 1.
Further, Hong teaches further comprising: a second S/D region (Hong: Fig (1): S/D) upon the substrate layer (109) and connected to the one or more channel regions (NP); a frontside S/D region (S/D) contact (CA+MV) upon connected to the top surface of the second S/D region (S/D); and a metallization feature within a back end of the line (BEOL) level (104) electrically connected to the frontside S/D region contact.
Hong in view of Chang does not teach a metallization feature within a back end of the line (BEOL) level connected to the frontside S/D region contact.
Kim teaches a metallization feature (Kim: Fig (1): M1) within a back end of the line (BEOL) level (level containing M1) connected to the frontside S/D region contact (130).
Hong in view of Chang and Kim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hong in view of Chang by constructing a BEOL contact that is connected to the S/D region of the transistor to make establishing electrical connections between the different layers of the device easier leading to a more reliable device production process.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Xie et al, US 20230132353 A1 (Xie); discloses an S/D contact in the form of a via and a horizontal component that connects the top of an S/D region of transistor to a backside power line.
Xie et al, US 20230178433 A1 (Xie); teaches a nanosheet channel structure S/D that is connected at its top surface to backside power line.
Chu et al, US 20210376093 A1 (Chu); teaches a nanosheet channel transistor.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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