DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 05/12/2026 has been entered. Applicant's amendment have overcome
the objections to the to the Claims 112 (b), rejections previously set forth in the Non-Final Office Action dated on 02/13/2026. Claims 2-3,13,15-16 are canceled. Claims 21-25 are new. Claims 1,4-12,14 and 17-25 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 05/12/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20230343765 A1 to Jeng, being used in the current rejection, see detail below.
Election/Restrictions
New claim 25 is directed to a different Species to the Species of claim 14. The limitation of “a
motherboard coupled to a side of the package substrate opposite to the plurality of IC dies” of new claim 25 is disclosed by Figure 5 but different to Fig. 1. In figure 5 is showed an interposer 2257 but not a bridge, in paragraph 0121 is disclosed a motherboard coupled to interconnects 2270. Figure 1 shows a bridge IC die 114. Figures 1 and 5 shows different embodiments. Then, New claim 25 is withdrawn from consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of new claim 24 “…the bridge IC die comprises conductive pathways conductively coupling two or more IC dies in the plurality of IC dies”, (it is not clear what element correspond to conductive pathways) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 7 is objected to because of the following informalities: “…a plurality of layers of
conductive trace…”. It should be read “…a plurality of layers of conductive traces…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 1, 8 and 14 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first
paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed, fails to adequately describe the limitation of Claim 1 “the first conductive via and the second conductive via are misaligned relative to a centerline of the conductive trace along a length of the trace from the first conductive via to the second conductive via”, for example in Figure 2A is showed a via 108A aligned relative to a centerline 210 of the layer 106 and a via 108B misaligned relative to a centerline 210 of the layer 106. In addition, Fig. 2B shows, a via 108A and a via 108B misaligned relative to each other along a length of the conductive trace 106.
Claim 1 includes a new matter, figs. 1-7, none of the figures shows "the first conductive via and the second conductive via are misaligned relative to a centerline of the conductive trace along a length of the trace from the first conductive via to the second conductive via”. For examination propose of claim 1, this limitation will not be examined.
The specification as filed, fails to adequately describe the limitation of Claim 8 “a first and
second conductive vias of the subset of conductive vias are misaligned relative to a corresponding centerline of a conductive trace in the second layer along a length of the trace from the first via to the second via”, for example in Figure 2A is showed a via 108A aligned relative to a centerline 210 of the layer 106 and a via 108B misaligned relative to a centerline 210 of the layer 106. In addition, Fig. 2B shows, a via 108A and a via 108B misaligned relative to each other along a length of the conductive trace 106.
Claim 8 includes a new matter, figs. 1-7, none of the figures shows " a first and second conductive vias of the subset of conductive vias are misaligned relative to a corresponding centerline of a conductive trace in the second layer along a length of the trace from the first via to the second via”. For examination propose of claim 8, this limitation will not be examined.
The specification as filed, fails to adequately describe the limitation of Claim 14 “the first conductive via and the second conductive via are misaligned relative to a centerline of the same conductive trace along a length of the same conductive trace from the first via to the second via”, for example in Figure 2A is showed a via 108A aligned relative to a centerline 210 of the layer 106 and a via 108B misaligned relative to a centerline 210 of the layer 106. In addition, Fig. 2B shows, a via 108A and a via 108B misaligned relative to each other along a length of the conductive trace 106.
Claim 14 includes a new matter, figs. 1-7, none of the figures shows "the first conductive via and the second conductive via are misaligned relative to a centerline of the same conductive trace along a length of the same conductive trace from the first via to the second via”. For examination propose of claim 14, this limitation will not be examined.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 6-7 and 21-22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal (US 6204165 B1, hereinafter Ghoshal, of the record) in view of Jeng et al. (US 20230343765 A1, hereinafter Jeng) and further in view of Dixit (US 6566258 B1, hereinafter Dixit, of the record).
Re: Independent Claim 1, Ghoshal discloses a package substrate, comprising:
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Ghoshal, Fig. 4G-Annotated
a conductive via (190 interconnection in Col. 2, lines 65-66, Fig. 4G) in a first layer (111 dielectric layer in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G);
a conductive trace (151 interconnection in Col. 3, lines 3-5, Fig. 4G) in a second layer (112 dielectric layer in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G),
wherein: the conductive via (190, Fig. 4G) is directly attached to the conductive trace (151, Fig. 4G),
the conductive via (190, Fig. 4G) is a first conductive via (190, Fig. 4G), the package substrate comprises a second conductive via (171 connection in Col. 3, lines 26-27, Fig. 4G) in a third layer (113 dielectric layer in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G, Ghoshal),
the second layer (112, Fig. 4G) of the conductive trace (151, Fig. 4G) is between the first layer (112, Fig. 4G) of the first conductive via (190, Fig. 4G) and the third layer (113, Fig. 4G) of the second conductive via (171, Fig. 4G), the second conductive via (171, Fig. 4G) is directly attached to the conductive trace (151, Fig. 4G).
Ghoshal does not expressly disclose wherein the first layer comprising a positive-type photo-imageable dielectric, the second layer comprising a negative-type photo- imageable dielectric; and
an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers, wherein: the conductive via is directly attached to the conductive trace through the insulative material,
the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation, the third layer comprising the positive-type photo-imageable dielectric.
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Jeng, Fig. 5-Annotated
However, in the same semiconductor device field of endeavor, Jeng discloses a first layer (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric) comprising a positive-type photo-imageable dielectric ([0016]), a second layer (40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric) comprising a negative-type photo-imageable dielectric ([0026]), the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation (24 having the properties of a positive photo-sensitive material, wherein they are soluble to a photoresist developer after exposed to the radiation in [0016]), and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation (40 having the properties of a negative photo-sensitive material, wherein they are insoluble to a photoresist developer after exposed to the radiation in [0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeng’s feature of the first layer comprising a positive-type photo-imageable dielectric, the second layer comprising a negative-type photo- imageable dielectric, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation to Ghoshal’s device to obtain the third layer comprising the positive-type photo-imageable dielectric to form traces and vias in the device ([0016], Jeng).
Ghoshal modified by Jeng does not expressly disclose wherein an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers, wherein: the conductive via is directly attached to the conductive trace through the insulative material.
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Dixit, Fig. 3-Annotated
However, in the same semiconductor device field of endeavor, Dixit discloses wherein an insulative material (16 an etch stop layer between two dielectric layers in Col.1, lines 24-27, Figs. 2-3) between two layers (14, 18 two dielectric layers in Col.1, lines 24-26, Figs. 2-3), the insulative material (16) configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers (etch stop layer 16 made of silicon nitride can absorb ultraviolet light in Col.1, lines 24-27, Figs. 2-3) wherein: the conductive via (20 a via in Figs. 2-3) is directly attached to the conductive trace (22/24 a metal layer in Col.1, lines 49-50, Figs. 2-3) through the insulative material (16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers, wherein: the conductive via is directly attached to the conductive trace through the insulative material to the combination of Ghoshal and Jeng to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
Re: Claim 6, Ghoshal modified by Jeng and Dixit discloses the package substrate of claim 1, wherein: the conductive via (190, Fig. 4G, Ghoshal) has a first width (w1, Fig. 4G-Annotated, Ghoshal), the conductive trace (151, Fig. 4G, Ghoshal) has a second width (w2, Fig. 4G-Annotated, Ghoshal), and the first width (w1, Fig. 4G-Annotated, Ghoshal) is substantially equal (Fig. 4G, Ghoshal) to the second width (w2, Fig. 4G-Annotated, Ghoshal).
Re: Claim 7, Ghoshal modified by Jeng and Dixit discloses the package substrate of claim 1,
further comprising: a plurality of layers (111,113 dielectric layers in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G, Ghoshal) of conductive vias (171, 190, Fig. 4G, Ghoshal); a plurality of layers (112,114 dielectric layers in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G, Ghoshal) of conductive traces (151,153 Fig. 4G, Ghoshal), wherein: individual layers in the plurality of conductive vias (111,113, Fig. 4G, Ghoshal) alternate with individual layers in the plurality of layers of conductive traces (112,114, Fig. 4G, Ghoshal).
Ghoshal modified by Jeng and Dixit does not expressly disclose a plurality of layers of conductive vias surrounded by the positive-type photo-imageable dielectric; a plurality of layers of conductive traces surrounded by the negative-type photo-imageable dielectric; and a plurality of layers of the insulative material, and the individual layers of the insulative material are at interfaces between the positive-type photo-imageable dielectric and the negative-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Jeng discloses a layer (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric) of conductive vias (via, Fig. 5) surrounded by the positive-type photo-imageable dielectric ([0016]); a plurality of layers (40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric) of conductive traces (trace, Fig. 5) surrounded by the negative-type photo-imageable dielectric ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeng’s feature of a layer of conductive vias surrounded by the positive-type photo-imageable dielectric; a layer of conductive traces surrounded by the negative-type photo- imageable dielectric to the combination of Ghoshal, Jeng and Dixit to obtain a plurality of layers of conductive vias surrounded by the positive-type photo-imageable dielectric; a plurality of layers of conductive traces surrounded by the negative-type photo- imageable dielectric to form traces and vias in the device ([0016], Jeng).
Ghoshal modified by Jeng and Dixit does not expressly disclose a plurality of layers of the insulative material, and individual layers of the insulative material are at interfaces between the positive-type photo-imageable dielectric and the negative-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Dixit discloses wherein a plurality of layers of the insulative material (12,16,30,34 etch stop layers between two dielectric layers in Col.1, lines 24-27,56-59 Figs. 2-3) are between pair of dielectric layers (14, 18,32,36 dielectric layers in Col.1, lines 24-26, Figs. 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of a plurality of layers of the insulative material between are between pair of dielectric layers to the combination of Ghoshal, Jeng and Dixit to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
The combination of Ghoshal, Jeng and Dixit results in individual layers of the insulative material (12,16,30,34’s Dixit applied to Ghoshal) are at interfaces between the positive-type photo-imageable dielectric (24’s Jeng applied to Ghoshal) and the negative-type photo-imageable dielectric (40’s Jeng applied to Ghoshal).
Re: Claim 21, Ghoshal modified by Jeng and Dixit discloses the package substrate of claim 1, wherein the positive-type photo-imageable dielectric comprises at least one of polymethyl methacrylate (PMMA), diazoalkylquinone, diazobenzoquinone, or diazonaphtoquinone (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric, Jeng), and the negative-type photo-imageable dielectric comprises an epoxy material (40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric, Jeng).
Re: Claim 22, Ghoshal modified by Jeng and Dixit discloses the package substrate of claim 1, wherein sidewalls of the conductive via (171 and 190, Fig.4G, Ghoshal) are not tapered (Fig.4G, Ghoshal).
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal in view of Jeng et al. in view of Dixit and further in view of Strong (US 20200211949 A1, hereinafter Strong, of the record).
Re: Claim 4, Ghoshal modified by Jeng and Dixit discloses the package substrate of claim 1,
Ghoshal modified by Jeng and Dixit does not expressly disclose wherein a first centerline of the conductive via is aligned with a second centerline of the conductive trace.
However, in the same semiconductor device field of endeavor, Strong discloses wherein a first centerline of a conductive via (114 a via in [0048], Fig. 1A) is aligned (a center point of the top via 114 aligned with the centerline of the trace 116 in [0048]) with a second centerline of a conductive trace (116 a trace in [0048], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Strong’s feature of wherein a first centerline of the conductive via is aligned with a second centerline of the conductive trace to the combination of Ghoshal, Jeng and Dixit to allow the formation of smaller and better-aligned features (e.g., vias and traces) in package substrates and other IC components ([0041], Strong).
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal in view of Jeng et al. in view of Dixit and further in view of Sato (US 12108608 B1, hereinafter Sato, of the record).
Re: Claim 5, Ghoshal modified by Jeng and Dixit discloses the package substrate of claim 1,
Ghoshal modified by Jeng and Dixit does not expressly disclose wherein the insulative material comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and transferable hyperbolic metamaterial particles (THMMP).
However, in the same semiconductor device field of endeavor, Sato discloses wherein an insulative material (113 an etch stop layer made of carbon in Col. 20, lines 31-33, Fig. 1A) comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and transferable hyperbolic metamaterial particles (THMMP).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Sato’s feature of wherein the insulative material comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and transferable hyperbolic metamaterial particles (THMMP) to the combination of Ghoshal, Jeng and Dixit to pattern and form devices and alternative enabling integration methods essential for realizing a high-density memory array (Col. 1, lines 23-25, Sato).
Claim(s) 8 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal (US 6204165 B1, hereinafter Ghoshal, of the record) in view of Jeng et al. (US 20230343765 A1, hereinafter Jeng) and further in view of Strong (US 20200211949 A1, hereinafter Strong, of the record).
Re: Independent Claim 8, Ghoshal discloses a package substrate, comprising:
a plurality of dielectric materials (111,112,113 dielectric layers in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G) in separate layers (Fig. 4G);
a plurality of conductive vias (190, 193 interconnections layers in Col. 2, lines 65-66, Fig. 4G) in a first subset of the layers (first subset-Fig. 4G-Annotated); and
a plurality of conductive traces (151 a plurality of interconnections layers in Col. 3, lines 3-5, Fig. 4G) in a second subset of the layers (second subset-Fig. 4G-Annotated), wherein:
individual ones of the first subset of the layers (first subset-Fig. 4G-Annotated) alternate (Fig. 4G-Annotated) with individual ones of the second subset of the layers (second subset-Fig. 4G-Annotated),
conductive vias (171 and 190, wherein the 171 is in dielectric layer 113 in Col. 3, line 26, Fig. 4G) in separate ones of the first subset of the layers (first subset-Fig. 4G-Annotated), the conductive vias (171 and 190) attached to a common conductive trace (151), are misaligned with respect to each other in a direction along a length of the conductive trace (Fig. 4G-Annotated).
Ghoshal does not expressly disclose a plurality of different dielectric materials in separate layers; and centers of a subset of conductive vias in a first layer in the first subset of layers are aligned with corresponding centerlines of conductive traces in a second layer in the second subset of layers, the first layer being adjacent to the second layer, the subset of conductive vias being coupled directly to the corresponding conductive traces.
However, in the same semiconductor device field of endeavor, Jeng discloses a plurality of different dielectric materials in separate layers (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric and 40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric) comprising a negative-type photo-imageable dielectric ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeng’s feature of a plurality of different dielectric materials in separate layers to Ghoshal’s device to obtain the third layer comprising the positive-type photo-imageable dielectric to form traces and vias in the device ([0016], Jeng).
Ghoshal modified Jeng by does not expressly disclose centers of a subset of conductive vias in a first layer in the first subset of layers are aligned with corresponding centerlines of conductive traces in a second layer in the second subset of layers, the first layer being adjacent to the second layer, the subset of conductive vias being coupled directly to the corresponding conductive traces.
However, in the same semiconductor device field of endeavor, Strong discloses a center of a conductive via (114 a via in [0048], Fig. 1A) in a first layer (106 a second dielectric layer in [0047], Fig. 1A) is aligned with (a center point of the top via 114 aligned with the centerline of the trace 116 in [0048]) corresponding centerline of conductive trace (116 a trace in [0048], Fig. 1A) in a second layer (104 a first dielectric layer in [0048], Fig. 1A), the first layer (106) being adjacent to the second layer (104), the conductive via (114) being coupled directly to the corresponding conductive trace (116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Strong’s feature of a center of a conductive via in a first layer is aligned with corresponding centerline of conductive trace in a second layer, the first layer being adjacent to the second layer, the conductive via being coupled directly to the corresponding conductive trace to the combination of Ghoshal and Jeng to have centers of a subset of conductive vias in a first layer in the first subset of layers are aligned with corresponding centerlines of conductive traces in a second layer in the second subset of layers, the first layer being adjacent to the second layer, the subset of conductive vias being coupled directly to the corresponding conductive traces to allow the formation of smaller and better-aligned features (e.g., vias and traces) in package substrates and other IC components ([0041], Strong).
Re: Claim 12, Ghoshal modified by Jeng and Strong discloses the package substrate of claim 8, wherein: the package substrate is part of a computing device, and the computing device comprises at least one of a processor device, a memory, and a display (a device including memory chips such as DRAMs in Col. 5, lines 30-32, Ghoshal).
Claim(s) 9-11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal in view of Jeng in view of Strong and further in view of Dixit (US 6566258 B1, hereinafter Dixit, of the record).
Re: Claim 9, Ghoshal modified by Jeng and Strong discloses the package substrate of claim 8, wherein the different dielectric materials include: a positive-type photo-imageable dielectric (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric, Jeng), a negative-type photo-imageable dielectric (40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric, Jeng).
Ghoshal modified by Jeng and Strong does not expressly disclose wherein an insulative material capable of absorbing light or ultraviolet light.
However, in the same semiconductor device field of endeavor, Dixit discloses wherein an insulative material (16 an etch stop layer between two dielectric layers in Col.1, lines 24-27, Figs. 2-3) capable of absorbing light or ultraviolet light (etch stop layer 16 made of silicon nitride can absorb ultraviolet light in Col.1, lines 24-27, Figs. 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of an insulative material capable of absorbing light or ultraviolet light to the combination of Ghoshal, Jeng and Strong to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
Re: Claim 10, Ghoshal modified by Jeng, Strong and Dixit discloses the package substrate of claim 9, wherein the positive-type photo-imageable dielectric comprises polymethyl methacrylate (PMMA) (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric, Jeng).
Re: Claim 11, Ghoshal modified by Jeng, Strong and Dixit discloses the package substrate of claim 9, wherein the negative-type photo-imageable dielectric comprises an epoxy material (40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric, Jeng).
Claim(s) 14,17-20 and 24 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu (US 20170263518 A1, hereinafter Yu, of the record) in view of Jeng and further in view of Dixit.
Re: Independent Claim 14, Yu discloses a microelectronic assembly (Fig. 20), comprising:
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a plurality of IC dies (66A, 66B, and 66C plurality of dies in [0022], Fig.20); and
a package substrate (100, 64,62, 60, 44, 30 elements in Fig. 15 forms the package substrate in [0031], Fig.15) coupled to the plurality of IC dies (66A, 66B, and 66C),
wherein:
the package substrate (100, 64,62, 60, 44, 30) comprises:
a bridge IC die (100 a device dies as a bridge between connections top and bottom in [0024], Fig.20) surrounded by an epoxy-based dielectric material (44 an encapsulating material made of epoxy in [0024], Fig.20);
conductive traces (62-horizontal horizontal lines in RDL 62 made of metal in [0031], Fig.20) in a dielectric (60 dielectric layers in [0031], Fig.20);
conductive vias (62-vertical vertical lines in RDL 62 made of metal in [0031], Fig.20) in a dielectric (60 dielectric layers in [0031], Fig.20)
the conductive vias (62-vertical) comprise first (62-vertical-1, Fig.20-Annotated) and second (62-vertical-2, Fig.20-Annotated) conductive vias directly attached to a same conductive trace (62-horizontal-1, Fig.20-Annotated) of the conductive traces (62-horizontal).
Yu does not expressly disclose conductive traces in negative-type photo-imageable dielectric;
conductive vias in positive-type photo-imageable dielectric; and an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at a subset of interfaces between the negative-type photo-imageable dielectric and positive-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Jeng discloses conductive traces (traces, Fig. 5) in negative-type photo-imageable dielectric (40 a layer made of epoxy in [0026], Fig. 5, as an example of negative photo imageable dielectric); conductive vias (vias, Fig. 5) in positive-type photo-imageable dielectric (24 photo-sensitive material made of polymer as PMMA in [0016], Fig. 5, as an example of positive photo imageable dielectric).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeng’s feature of conductive traces in negative-type photo-imageable dielectric; conductive vias in positive-type photo-imageable dielectric to Yu’s device to form traces and vias in the device ([0016], Jeng).
Yu modified by Jeng does not expressly disclose an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at a subset of interfaces between the negative-type photo-imageable dielectric and positive-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Dixit discloses an insulative material (16 an etch stop layer between two dielectric layers in Col.1, lines 24-27, Figs. 2-3) capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers (etch stop layer 16 made of silicon nitride can absorb ultraviolet light in Col.1, lines 24-27, Figs. 2-3) at an interface between two dielectric layers (14, 18 two dielectric layers in Col.1, lines 24-26, Figs. 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at an interface between two dielectric layers to the combination of Yu and Jeng to obtain an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at a subset of interfaces between the negative-type photo-imageable dielectric and positive-type photo-imageable dielectric to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
Re: Claim 17, Yu modified by Jeng and Dixit disclose the microelectronic assembly of claim 14, wherein: the first conductive via (62-vertical-1, Fig.20-Annotated, Yu) and the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) have respective widths (Fig.20-Annotated, Yu) that are substantially similar to the width of the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Re: Claim 18, Yu modified by Jeng and Dixit disclose the microelectronic assembly of claim 14, wherein: the insulative material (16 in Col.1, lines 24-27, Figs. 2-3, Dixit) is between the positive-type photo-imageable dielectric (24’s Jeng applied to Yu) surrounding the first conductive via (62-vertical-1, Fig.20-Annotated, Yu) and the negative-type photo-imageable dielectric (40’s Jeng applied to Yu) surrounding the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Yu modified by Jeng and Dixit does not expressly disclose wherein: the first conductive via is aligned with the conductive trace.
However, in the same semiconductor device field of endeavor, Dixit discloses wherein a conductive via (40 via in Fig. 3) is aligned with a conductive trace (42 trace in Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature wherein the first conductive via is aligned with the conductive trace to the combination of Yu, Jeng and Dixit to form complex electrical interconnects required for the millions of semiconductor devices included in such silicon integrated circuits (Col.1, lines 14-16, Dixit).
Re: Claim 19, Yu modified by Jeng and Dixit disclose the microelectronic assembly of claim 14, wherein: the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) is not aligned (Fig.20-Annotated, Yu) with the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu) and the insulative material is not between the positive-type photo-imageable dielectric (24’s Jeng applied to Yu) surrounding the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) and the negative-type photo-imageable dielectric (40’s Jeng applied to Yu) surrounding the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Re: Claim 20, Yu modified by Jeng and Dixit disclose the microelectronic assembly of claim 14, wherein: the microelectronic assembly is part of a computing device, and the computing device includes at least one of: a processing device, a memory, a communication chip, a display device and an output device (a device having memory dies in [0032], Fig. 20, Yu).
Re: Claim 24, Yu modified by Jeng and Dixit disclose the microelectronic assembly of claim 14, wherein the bridge IC die (100A in [0024], Fig.20, Yu) comprises conductive pathways (140 metal pillars140A and 140B in [0019], Fig.20, Yu) conductively coupling (Fig.20) two or more IC dies (66A, 66B, Yu) in the plurality of IC dies (66A, 66B, and 66C, Yu).
Claim(s) 23 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal, in view of Jeng, in view of Strong, in view of Dixit and further in view of Sato (US 12108608 B1, hereinafter Sato, of the record).
Re: Claim 23, Ghoshal modified by Jeng, Strong and Dixit discloses the package substrate of claim 9,
Ghoshal modified by Jeng, Strong and Dixit does not expressly disclose wherein the insulative material is at least one of: carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and THMMP.
However, in the same semiconductor device field of endeavor, Sato discloses wherein an insulative material (113 an etch stop layer made of carbon in Col. 20, lines 31-33, Fig. 1A) comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and THMMP (in Col. 20, lines 31-33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Sato’s feature of wherein the insulative material comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and THMMP to the combination of Ghoshal, Jeng, Strong and Dixit to pattern and form devices and alternative enabling integration methods essential for realizing a high-density memory array (Col. 1, lines 23-25, Sato).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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