DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as
being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, it recites the limitation “…a first plurality of layers of conductive vias… … a second plurality of layers of conductive trace…”, “…the first plurality of layers alternate with individual layers in the second plurality of layers” is not explained. The limitation is not clear of “vias”, “first plurality of layers”, “second plurality of layers”. Therefore, it is indefinite. For the examination purpose and according to claim 1 and Fig. 3P, the limitation “…a first plurality of layers of conductive vias… …a second plurality of layers of conductive trace”, “…the first plurality of layers alternate with individual layers in the second plurality of layers” is interpreted as “…a plurality of first layers of conductive via…. “… a plurality of second layers of conductive trace…” “…the plurality of first layers alternate with individual layers in the plurality of second layers”.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal (US 6204165 B1, hereinafter Ghoshal) in view of Lee et al. (KR 20230168753 A, hereinafter Lee) and further in view of Dixit (US 6566258 B1, hereinafter Dixit).
Re: Independent Claim 1, Ghoshal discloses a package substrate, comprising:
PNG
media_image1.png
642
848
media_image1.png
Greyscale
Ghoshal, Fig. 4G-Annotated
a conductive via (190 interconnection in Col. 2, lines 65-66, Fig. 4G) in a first layer (111 dielectric layer in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G);
a conductive trace (151 interconnection in Col. 3, lines 3-5, Fig. 4G) in a second layer (112 dielectric layer in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G),
wherein: the conductive via (190, Fig. 4G) is directly attached to the conductive trace (151, Fig. 4G).
Ghoshal does not expressly disclose wherein the first layer comprising a positive-type photo-imageable dielectric, the second layer comprising a negative-type photo- imageable dielectric; and
an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers, wherein: the conductive via is directly attached to the conductive trace through the insulative material,
the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.
However, in the same semiconductor device field of endeavor, Lee discloses a first layer (110 an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095] Figs. 2,11, as an example of positive photo imageable dielectric) comprising a positive-type photo-imageable dielectric, a second layer (150 a resist layer made of resin in [0129], Figs. 2,11, as an example of negative photo imageable dielectric) comprising a negative-type photo-imageable dielectric, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation (as part of the process to form vias and traces using optical/resist materials that are exposed to electromagnetic radiation, a PMMA material can be soluble to a photoresist developer after exposed to the radiation in [0095]), and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation (as part of the process to form vias and trace using optical/resist layer that are exposed to electromagnetic radiation, a resin material can be insoluble to a photoresist developer after exposed to the radiation in [0129]).
PNG
media_image2.png
287
423
media_image2.png
Greyscale
Lee, Fig. 11-Annotated
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of the first layer comprising a positive-type photo-imageable dielectric, the second layer comprising a negative-type photo- imageable dielectric, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation to Ghoshal’s device to pattern the interconnections using optical/resist material ([0095, 00129], Lee).
Ghoshal modified by Lee does not expressly disclose wherein an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers, wherein: the conductive via is directly attached to the conductive trace through the insulative material.
PNG
media_image3.png
520
622
media_image3.png
Greyscale
Dixit, Fig. 3-Annotated
However, in the same semiconductor device field of endeavor, Dixit discloses wherein an insulative material (16 an etch stop layer between two dielectric layers in Col.1, lines 24-27, Figs. 2-3) between two layers (14, 18 two dielectric layers in Col.1, lines 24-26, Figs. 2-3), the insulative material (16) configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers (etch stop layer 16 made of silicon nitride can absorb ultraviolet light in Col.1, lines 24-27, Figs. 2-3) wherein: the conductive via (20 a via in Figs. 2-3) is directly attached to the conductive trace (22/24 a metal layer in Col.1, lines 49-50, Figs. 2-3) through the insulative material (16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers, wherein: the conductive via is directly attached to the conductive trace through the insulative material to the combination of Ghoshal and Lee to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
Re: Claim 2, Ghoshal modified by Lee and Dixit discloses the package substrate of claim 1, wherein: the conductive via (190, Fig. 4G, Ghoshal) is a first conductive via (190, Fig. 4G, Ghoshal), the package substrate comprises a second conductive via (171 connection in Col. 3, lines 26-27, Fig. 4G, Ghoshal) in a third layer (113 dielectric layer in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G, Ghoshal), the second layer (112, Fig. 4G, Ghoshal) of the conductive trace (151, Fig. 4G, Ghoshal) is between the first layer (112, Fig. 4G, Ghoshal) of the first conductive via (190, Fig. 4G, Ghoshal) and the third layer (113, Fig. 4G, Ghoshal) of the second conductive via (171, Fig. 4G, Ghoshal), the second conductive via (171, Fig. 4G, Ghoshal) is directly attached to the conductive trace (151, Fig. 4G, Ghoshal), and the first conductive via (190, Fig. 4G, Ghoshal) and the second conductive via (171, Fig. 4G, Ghoshal) are misaligned (Fig. 4G, Ghoshal) relative to each other along a length of the conductive trace (151, Fig. 4G, Ghoshal).
Ghoshal modified by Lee and Dixit does not expressly disclose wherein the third layer comprising the positive-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Lee discloses a layer (110 an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095] Figs. 2,11, as an example of positive photo imageable dielectric) comprising a positive-type photo-imageable dielectric.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of the third layer comprising the positive-type photo-imageable dielectric to the combination of Ghoshal, Lee and Dixit to pattern the interconnections using optical/resist material ([0095, 00129], Lee).
Re: Claim 3, Ghoshal modified by Lee and Dixit discloses the package substrate of claim 2, wherein the first conductive via (190, Fig. 4G, Ghoshal) and the second conductive via (171, Fig. 4G, Ghoshal) are misaligned in a plane of the conductive trace (151, Fig. 4G, Ghoshal) and along a direction orthogonal to the length of the conductive trace (151, Fig. 4G, Ghoshal).
Re: Claim 6, Ghoshal modified by Lee and Dixit discloses the package substrate of claim 1, wherein: the conductive via (190, Fig. 4G, Ghoshal) has a first width (w1, Fig. 4G-Annotated, Ghoshal), the conductive trace (151, Fig. 4G, Ghoshal) has a second width (w2, Fig. 4G-Annotated, Ghoshal), and the first width (w1, Fig. 4G-Annotated, Ghoshal) is substantially equal (Fig. 4G, Ghoshal) to the second width (w2, Fig. 4G-Annotated, Ghoshal).
Re: Claim 7, Ghoshal modified by Lee and Dixit discloses the package substrate of claim 1,
further comprising: a plurality of first layers (111,113 dielectric layers in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G, Ghoshal) of conductive via (171, 190, Fig. 4G, Ghoshal); a plurality of second layers (112,114 dielectric layers in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G, Ghoshal) of conductive trace (151,153 Fig. 4G, Ghoshal), wherein: individual layers in the plurality of first layers (111,113, Fig. 4G, Ghoshal) alternate with individual layers in the plurality of second layers (112,114, Fig. 4G, Ghoshal).
Ghoshal modified by Lee and Dixit does not expressly disclose a first plurality of layers of conductive vias surrounded by the positive-type photo-imageable dielectric; a second plurality of layers of conductive trace surrounded by the negative-type photo- imageable dielectric; and a third plurality of layers of the insulative material between some of the first plurality of layers and the second plurality of layers, and the insulative material is at interfaces between the positive-type photo-imageable dielectric and the negative-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Lee discloses a first layer (110 is an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095] Figs. 2,11, as an example of positive photo imageable dielectric) of conductive via (140 Figs. 2,11) surrounded by a positive-type photo-imageable dielectric (110 Figs. 2,11); a second layer (150 is a resist layer made of resin in [0129], Figs. 2,11, as an example of negative photo imageable dielectric) of conductive trace (120 Figs. 2,11) surrounded by the negative-type photo- imageable dielectric (150 Figs. 2,11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of a first layer of conductive vias surrounded by the positive-type photo-imageable dielectric; a second layer of conductive trace surrounded by the negative-type photo- imageable dielectric to the combination of Ghoshal, Lee and Dixit to pattern the interconnections using optical/resist material ([0095, 00129], Lee).
Ghoshal modified by Lee and Dixit does not expressly disclose a third plurality of layers of the insulative material between some of the first plurality of layers and the second plurality of layers, and the insulative material is at interfaces between the positive-type photo-imageable dielectric and the negative-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Dixit discloses wherein a third plurality of layers of the insulative material (12,16,30,34 etch stop layers between two dielectric layers in Col.1, lines 24-27,56-59 Figs. 2-3) is between pair of dielectric layers (14, 18,32,36 dielectric layers in Col.1, lines 24-26, Figs. 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of a third plurality of layers of the insulative material between some of the first plurality of layers and the second plurality of layers to the combination of Ghoshal, Lee and Dixit to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
The combination of Ghoshal, Lee and Dixit results in the insulative material (12,16,30,34’s Dixit applied to Ghoshal) is at interfaces between the positive-type photo-imageable dielectric (110’s Lee applied to Ghoshal) and the negative-type photo-imageable dielectric (150’s Lee applied to Ghoshal).
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal in view of Lee et al. in view of Dixit and further in view of Strong (US 20200211949 A1, hereinafter Strong).
Re: Claim 4, Ghoshal modified by Lee and Dixit discloses the package substrate of claim 1,
Ghoshal modified by Lee and Dixit does not expressly disclose wherein a first centerline of the conductive via is aligned with a second centerline of the conductive trace.
However, in the same semiconductor device field of endeavor, Strong discloses wherein a first centerline of a conductive via (114 a via in [0048], Fig. 1A) is aligned (a center point of the top via 114 aligned with the centerline of the trace 116 in [0048]) with a second centerline of a conductive trace (116 a trace in [0048], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Strong’s feature of wherein a first centerline of the conductive via is aligned with a second centerline of the conductive trace to the combination of Ghoshal, Lee and Dixit to allow the formation of smaller and better-aligned features (e.g., vias and traces) in package substrates and other IC components ([0041], Strong).
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal in view of Lee et al. in view of Dixit and further in view of Sato (US 12108608 B1, hereinafter Sato).
Re: Claim 5, Ghoshal modified by Lee and Dixit discloses the package substrate of claim 1,
Ghoshal modified by Lee and Dixit does not expressly disclose wherein the insulative material comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and transferable hyperbolic metamaterial particles (THMMP).
However, in the same semiconductor device field of endeavor, Sato discloses wherein an insulative material (113 an etch stop layer made of carbon in Col. 20, lines 31-33, Fig. 1A) comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and transferable hyperbolic metamaterial particles (THMMP).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Sato’s feature of wherein the insulative material comprises at least one selected from carbon black, carbon nanotubes, anti-reflective nanorods, graphene, and transferable hyperbolic metamaterial particles (THMMP) to the combination of Ghoshal, Lee and Dixit to pattern and form devices and alternative enabling integration methods essential for realizing a high-density memory array (Col. 1, lines 23-25, Sato).
Claim(s) 8 and 12-13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal (US 6204165 B1, hereinafter Ghoshal) in view of Lee et al. (KR 20230168753 A, hereinafter Lee) and further in view of Strong (US 20200211949 A1, hereinafter Strong).
Re: Independent Claim 8, Ghoshal discloses a package substrate, comprising:
a plurality of dielectric materials (111,112,113 dielectric layers in Col. 2, line 66, Col. 3, lines 13-19, Fig. 4G) in separate layers (Fig. 4G);
a plurality of conductive vias (190, 193 interconnections layers in Col. 2, lines 65-66, Fig. 4G) in a first subset of the layers (first subset-Fig. 4G-Annotated); and
a plurality of conductive traces (151 a plurality of interconnections layers in Col. 3, lines 3-5, Fig. 4G) in a second subset of the layers (second subset-Fig. 4G-Annotated), wherein:
individual ones of the first subset of the layers (first subset-Fig. 4G-Annotated) alternate (Fig. 4G-Annotated) with individual ones of the second subset of the layers (second subset-Fig. 4G-Annotated),
conductive vias (171 and 190, wherein the 171 is in dielectric layer 113 in Col. 3, line 26, Fig. 4G) in separate ones of the first subset of the layers (first subset-Fig. 4G-Annotated), the conductive vias (171 and 190) attached to a common conductive trace (151), are misaligned with respect to each other in a direction along a length of the conductive trace (Fig. 4G-Annotated).
Ghoshal does not expressly disclose a plurality of different dielectric materials in separate layers; and centers of a subset of conductive vias in a first layer in the first subset of layers are aligned with corresponding centerlines of conductive traces in a second layer in the second subset of layers, the first layer being adjacent to the second layer, the subset of conductive vias being coupled directly to the corresponding conductive traces.
However, in the same semiconductor device field of endeavor, Lee discloses a plurality of different dielectric materials in separate layers (110, 150, wherein 110 is an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095] Figs.2,11, as an example of positive photo imageable dielectric and 150 is a resist layer made of resin in [0129], Figs.2,11, as an example of negative photo imageable dielectric).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of a plurality of different dielectric materials in separate layers to Ghoshal’s device to pattern the interconnections using optical/resist material ([0095, 00129], Lee).
Ghoshal modified Lee by does not expressly disclose centers of a subset of conductive vias in a first layer in the first subset of layers are aligned with corresponding centerlines of conductive traces in a second layer in the second subset of layers, the first layer being adjacent to the second layer, the subset of conductive vias being coupled directly to the corresponding conductive traces.
However, in the same semiconductor device field of endeavor, Strong discloses a center of a conductive via (114 a via in [0048], Fig. 1A) in a first layer (106 a second dielectric layer in [0047], Fig. 1A) is aligned with (a center point of the top via 114 aligned with the centerline of the trace 116 in [0048]) corresponding centerline of conductive trace (116 a trace in [0048], Fig. 1A) in a second layer (104 a first dielectric layer in [0048], Fig. 1A), the first layer (106) being adjacent to the second layer (104), the conductive via (114) being coupled directly to the corresponding conductive trace (116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Strong’s feature of a center of a conductive via in a first layer is aligned with corresponding centerline of conductive trace in a second layer, the first layer being adjacent to the second layer, the conductive via being coupled directly to the corresponding conductive trace to the combination of Ghoshal and Lee to have centers of a subset of conductive vias in a first layer in the first subset of layers are aligned with corresponding centerlines of conductive traces in a second layer in the second subset of layers, the first layer being adjacent to the second layer, the subset of conductive vias being coupled directly to the corresponding conductive traces to allow the formation of smaller and better-aligned features (e.g., vias and traces) in package substrates and other IC components ([0041], Strong).
Re: Claim 12, Ghoshal modified by Lee and Strong discloses the package substrate of claim 8, wherein: the package substrate is part of a computing device, and the computing device comprises at least one of a processor device, a memory, and a display (a device including memory chips such as DRAMs in Col. 5, lines 30-32, Ghoshal).
Re: Claim 13, Ghoshal modified by Lee and Strong discloses the package substrate of claim 8, wherein respective centerlines (Fig. 4G-Annotated) of the conductive vias (171 and 190, Fig.4G, Ghoshal) in separate ones of the first subset of the layers (first subset-Fig. 4G-Annotated) and coupled to a common conductive trace (151, Fig.4G, Ghoshal) are misaligned (Fig. 4G-Annotated) with respect to each other in a direction along a width of the conductive trace (151).
Claim(s) 9-11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ghoshal in view of Lee et al. in view of Strong and further in view of Dixit (US 6566258 B1, hereinafter Dixit).
Re: Claim 9, Ghoshal modified by Lee and Strong discloses the package substrate of claim 8, wherein the different dielectric materials include: a positive-type photo-imageable dielectric (110, an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095], as an example of positive photo imageable dielectric, Lee), a negative-type photo-imageable dielectric (150, a resist layer made of epoxy in [0129], as an example of negative photo imageable dielectric, Lee).
Ghoshal modified by Lee and Strong does not expressly disclose wherein an insulative material capable of absorbing light or ultraviolet light.
However, in the same semiconductor device field of endeavor, Dixit discloses wherein an insulative material (16 an etch stop layer between two dielectric layers in Col.1, lines 24-27, Figs. 2-3) capable of absorbing light or ultraviolet light (etch stop layer 16 made of silicon nitride can absorb ultraviolet light in Col.1, lines 24-27, Figs. 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of an insulative material capable of absorbing light or ultraviolet light to the combination of Ghoshal, Lee and Strong to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
Re: Claim 10, Ghoshal modified by Lee, Strong and Dixit discloses the package substrate of claim 9, wherein the positive-type photo-imageable dielectric comprises polymethyl methacrylate (PMMA) (110, an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095], Lee).
Re: Claim 11, Ghoshal modified by Lee, Strong and Dixit discloses the package substrate of claim 9, wherein the negative-type photo-imageable dielectric comprises an epoxy material (150, a resist layer made of epoxy in [0129], Lee).
Claim(s) 14-20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu (US 20170263518 A1, hereinafter Yu) in view of Lee et al. and further in view of Dixit.
Re: Independent Claim 14, Yu discloses a microelectronic assembly (Fig. 20), comprising:
PNG
media_image4.png
480
896
media_image4.png
Greyscale
Yu, Fig. 20-Annotated.
a plurality of IC dies (66A, 66B, and 66C plurality of dies in [0022], Fig.20); and
a package substrate (100, 64,62, 60, 44, 30 elements in Fig. 15 forms the package substrate in [0031], Fig.15) coupled to the plurality of IC dies (66A, 66B, and 66C),
wherein:
the package substrate (100, 64,62, 60, 44, 30) comprises:
a bridge IC die (100 a device dies as a bridge between connections top and bottom in [0024], Fig.20) surrounded by an epoxy-based dielectric material (44 an encapsulating material made of epoxy in [0024], Fig.20);
conductive traces (62-horizontal horizontal lines in RDL 62 made of metal in [0031], Fig.20) in a dielectric (60 dielectric layers in [0031], Fig.20);
conductive vias (62-vertical vertical lines in RDL 62 made of metal in [0031], Fig.20) in a dielectric (60 dielectric layers in [0031], Fig.20).
Yu does not expressly disclose conductive traces in negative-type photo-imageable dielectric;
conductive vias in positive-type photo-imageable dielectric; and an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at a subset of interfaces between the negative-type photo-imageable dielectric and positive-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Lee discloses conductive traces (120 traces, Figs.2,11) in negative-type photo-imageable dielectric (150 is a resist layer made of resin in [0129], Figs.2,11, as an example of negative photo imageable dielectric); conductive vias (140 vias, Figs.2,11) in positive-type photo-imageable dielectric (110 is an optically isotropic film made of polymethyl methacrylate (PMMA) in [0095] Figs.2,11, as an example of positive photo imageable dielectric).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of conductive traces in negative-type photo-imageable dielectric; conductive vias in positive-type photo-imageable dielectric to Yu’s device to pattern the interconnections using optical/resist material ([0095, 00129], Lee).
Yu modified by Lee does not expressly disclose an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at a subset of interfaces between the negative-type photo-imageable dielectric and positive-type photo-imageable dielectric.
However, in the same semiconductor device field of endeavor, Dixit discloses an insulative material (16 an etch stop layer between two dielectric layers in Col.1, lines 24-27, Figs. 2-3) capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers (etch stop layer 16 made of silicon nitride can absorb ultraviolet light in Col.1, lines 24-27, Figs. 2-3) at an interface between two dielectric layers (14, 18 two dielectric layers in Col.1, lines 24-26, Figs. 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature of an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at an interface between two dielectric layers to the combination of Yu and Lee to obtain an insulative material capable of absorbing electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers at a subset of interfaces between the negative-type photo-imageable dielectric and positive-type photo-imageable dielectric to protect the underlying dielectric layer during the CMP planarization of the copper which tends to introduce defects into the oxides. Also, depending upon its composition relative to other layers, it may be used as an anti-reflective coating (ARC) (Col.4, lines 55-64, Dixit).
Re: Claim 15, Yu modified by Lee and Dixit disclose the microelectronic assembly of claim 14, wherein: a first conductive via (62-vertical-1 vertical line in [0031], Fig.20-Annotated, Yu) in the package substrate (100, 64,62, 60, 44, 30, Yu, Fig.20) is coupled to a conductive trace (62-horizontal-1 horizontal line in [0031], Fig.20-Annotated, Yu) in the package substrate (100, 64,62, 60, 44, 30, Yu, Fig.20), a second conductive via (62-vertical-2 vertical line in [0031], Fig.20-Annotated, Yu) in the package substrate (100, 64,62, 60, 44, 30, Yu, Fig.20) is coupled to the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu), the first conductive via (62-vertical-1, Fig.20-Annotated, Yu) and the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) are displaced with respect to each other along (Fig.20-Annotated, Yu) a length of the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Re: Claim 16, Yu modified by Lee and Dixit disclose the microelectronic assembly of claim 15, wherein: the first conductive via (62-vertical-1, Fig.20-Annotated, Yu) and the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) are displaced with respect to each other along (Fig.20-Annotated, Yu) a width of the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Re: Claim 17, Yu modified by Lee and Dixit disclose the microelectronic assembly of claim 16, wherein: the first conductive via (62-vertical-1, Fig.20-Annotated, Yu) and the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) have respective widths (Fig.20-Annotated, Yu) that are substantially similar to the width of the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Re: Claim 18, Yu modified by Lee and Dixit disclose the microelectronic assembly of claim 15, wherein: the insulative material (16 in Col.1, lines 24-27, Figs. 2-3, Dixit) is between the positive-type photo-imageable dielectric (110’s Lee applied to Yu) surrounding the first conductive via (62-vertical-1, Fig.20-Annotated, Yu) and the negative-type photo-imageable dielectric (150’s Lee applied to Yu) surrounding the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Yu modified by Lee and Dixit does not expressly disclose wherein: the first conductive via is aligned with the conductive trace.
However, in the same semiconductor device field of endeavor, Dixit discloses wherein a conductive via (40 via in Fig. 3) is aligned with a conductive trace (42 trace in Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Dixit’s feature wherein the first conductive via is aligned with the conductive trace to the combination of Yu, Lee and Dixit to form complex electrical interconnects required for the millions of semiconductor devices included in such silicon integrated circuits (Col.1, lines 14-16, Dixit).
Re: Claim 19, Yu modified by Lee and Dixit disclose the microelectronic assembly of claim 15, wherein: the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) is not aligned (Fig.20-Annotated, Yu) with the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu) and the insulative material is not between the positive-type photo-imageable dielectric (110’s Lee applied to Yu) surrounding the second conductive via (62-vertical-2, Fig.20-Annotated, Yu) and the negative-type photo-imageable dielectric (150’s Lee applied to Yu) surrounding the conductive trace (62-horizontal-1, Fig.20-Annotated, Yu).
Re: Claim 20, Yu modified by Lee and Dixit disclose the microelectronic assembly of claim 14, wherein: the microelectronic assembly is part of a computing device, and the computing device includes at least one of: a processing device, a memory, a communication chip, a display device and an output device (a device having memory dies in [0032], Fig. 20).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yu et al. (US 9768145 B2) teaches “METHODS OF FORMING MULTI-DIE PACKAGE STRUCTURES INCLUDING REDISTRIBUTION LAYERS”. This document is related to a semiconductor device including a first die and a second die placed over a carrier substrate. A first molding material formed adjacent to the first die and the second die. A first redistribution layer formed overlying the first molding material. A through via formed over the first redistribution layer. A package component on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.
Kawai et al. (US 20150366077 A1) teaches “METHOD FOR PRODUCING MOUNTED STRUCTURE”. This document is related to a device including an insulation layer and a conductive layer, on a support member by alternately stacking the insulation layer and the conductive layer on the support member; a mounted structure, which includes the circuit substrate and an electronic component, on the support member by mounting the electronic component on the circuit substrate; and a step of removing the support member from the mounted structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898