DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species I (Fig. 1), claims 1-5, 7, 8 and 10-20, in the reply filed on 07/18/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. US 2018/0138101 A1.
Regarding claim 1, Yu discloses:
A semiconductor package (Figs. 19 and 20 in view of layout of Fig. 13) comprising:
an interposer (96) comprising a base layer (70) and a plurality of through-electrodes (74) penetrating the base layer;
at least one stacked structure (400A) attached to the interposer, the at least one stacked structure comprising a first semiconductor chip (bottommost chip), a plurality of second semiconductor chips (chips above bottommost chip) sequentially stacked on the first semiconductor chip, and a chip molding layer (414 para 0070) on a side surface of the plurality of second semiconductor chips;
a plurality of third semiconductor chips (400B) attached to the interposer adjacent the at least one stacked structure; and
a package molding layer (112) extending around the at least one stacked structure and the plurality of third semiconductor chips, wherein
the plurality of third semiconductor chips comprise a first chip group (Fig. 13; para 0065, left stacks 88/110 equivalent of 400B) and a second chip group (Fig. 13; para 0065, right stacks 88/110 equivalent of 400B), and
the at least one stacked structure is between the first chip group and the second chip group (Figs. 13 and 19).
Regarding claim 2, Yu discloses:
wherein the interposer (Fig. 13; 92 equivalent of Fig. 19; 96) comprises a pair of first edges opposite to each other in a first direction (Fig. 13; horizontal) and a pair of second edges opposite to each other in a second direction (Fig. 13; vertical) orthogonal to the first direction,
the first chip group (Fig. 13; left 88/110) is adjacent to one of the first edges, and the second chip group (Fig. 13; right 88/110) is adjacent to the other one of the first edges, and
the first chip group, the at least one stacked structure, and the second chip group are sequentially arranged along the first direction (Fig. 19).
Regarding claim 3, Yu discloses:
wherein the first chip group includes at least two different semiconductor chips (Fig. 19; left 400B chip stacks), and the second chip group includes at least two different semiconductor chips (Fig. 19; right 400B chip stacks), and
the semiconductor chips in the first chip group are arranged in a row adjacent one of the first edges (left), and the semiconductor chips in the second chip group are arranged in a row adjacent the other one of the first edges (right).
Regarding claims 7 and 8, Yu discloses:
(claim 7) wherein a side surface of the at least one stacked structure adjacent to one of the second edges is not closer to the one of the second edges than a side surface of a third semiconductor chip adjacent to the one of the second edges; and (claim 8) wherein the side surface of the at least one stacked structure and the side surface of the third semiconductor chip are equidistant from the one of the second edges (Fig. 13; 88/110 equivalent of 400B closer to vertical edge than 68 equivalent of 400A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5 and 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. US 2018/0138101 A1.
Regarding claims 4 and 5, Yu discloses:
(claim 4) wherein the plurality of third semiconductor chips (88/110 equivalent of 400B) include at least two main semiconductor chips (para 0026; memory controller) and at least one chiplet (para 0026; memory); and (claim 5) wherein the at least one chiplet in the first chip group and the at least one chiplet in the second chip group are adjacent to a same one of the second edges (Figs. 13 and 19; 88/110 equivalent of 400B).
Although Yu does not specifically disclose “the two main semiconductor chips having a plurality of functional blocks and the at least one chiplet having a functional block”, Yu does provide insight, in para 0026, that the dies 88 (stack 400B) have a memory controller and memory dies in the stack. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the memory controller would employ a number of functional blocks such as logic and on board cache memory for executable instructions for instance while the memory chiplets employ at least functional memory blocks.
Regarding claim 10, Yu discloses:
Although Yu does not specifically disclose “wherein each of the first chip group, the second chip group, and the at least one stacked structure has a rectangular footprint”, Yu does provide insight, in paras 0018 and 0026, that the dies 88 (stack 400B) and dies 400A can encompass different sizes (i.e. surface areas). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine a rectangular footprint for the chips stacks of Yu since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized ass being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claims 11-15, Yu discloses:
A semiconductor package (Figs. 19 and 20 in view of layout of Fig. 13) comprising:
an interposer (96) comprising a base layer (70) and a plurality of through-electrodes (74) penetrating the base layer, the base layer comprising silicon (para 0019), and the interposer having a pair of first edges opposite to each other in a first direction (Fig. 13 horizontal) and a pair of second edges opposite to each other in a second direction (Fig. 13 vertical) orthogonal to the first direction;
a stacked structure (400A), the stacked structure comprising a first semiconductor chip (bottommost chip), a plurality of second semiconductor chips (chips above bottommost chip) sequentially stacked on the first semiconductor chip, and a chip molding layer (414 para 0070) on a side surface of the plurality of second semiconductor chips;
a plurality of third semiconductor chips (400B) attached to the interposer adjacent the stacked structure; and
a package molding layer (112) on the interposer, the package molding layer extending around the stacked structure group and the plurality of third semiconductor chips to form a molding interface (interface between 414 and 112) with the chip molding layer,
wherein the plurality of third semiconductor chips comprise a first chip group (Fig. 13; para 0065, left stacks 88/110 equivalent of 400B) arranged in a row along one of the first edges, and a second chip group (Fig. 13; para 0065, right stacks 88/110 equivalent of 400B) arranged in a row along the other one of the first edges, and
wherein the stacked structure group is spaced apart from each of the first edges (Figs. 13 and 19).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the stacked structure group having a plurality of stacked structures similar to that of Yu 400A since such an addition would add further functionality using the noted devices in para 0018. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
(claims 12-15) Figs. 13, 19 and 20.
Regarding claims 16 and 17, Yu discloses:
(claim 16) wherein the plurality of third semiconductor chips (88/110 equivalent of 400B) include a main semiconductor chip (para 0026; memory controller) and a chiplet (para 0026; memory), wherein the main semiconductor chip (para 0026; memory controller) is electrically connected to the chiplet (para 0026; memory) through the interposer; and (claim 17) wherein the first chip group (left) includes a dummy chip (bottom 106) that is adjacent one of the second edges, and a chiplet (top 88(110) equivalent of 400B) that is adjacent the other one of the second edges, wherein the second chip group (right) includes a dummy chip (bottom 106) that is adjacent one of the second edges and a chiplet (top 88(110) equivalent of 400B) that is adjacent the other one of the second edges, and wherein the dummy chip in each of the first chip group and the second chip group does not include a semiconductor device (para 0038; Figs. 18 in view of Fig. 13).
Although Yu does not specifically disclose “the two main semiconductor chips having a plurality of functional blocks and the at least one chiplet having a functional block; and the main semiconductor chip is configured to function as one System on Chip (SoC)”, Yu does provide insight, in para 0026, that the dies 88 (stack 400B) have a memory controller and memory dies in the stack. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the memory controller would employ a number of functional blocks such as logic and onboard cache memory for executable instructions as a SoC for instance while the memory chiplets employ at least functional memory blocks.
Regarding claim 18, Yu discloses:
A semiconductor package (Figs. 19 and 20 in view of layout of Fig. 13) comprising:
a package base substrate (300 para 0050);
an silicon interposer (96 para 0019) attached to the package base substrate, the silicon interposer comprising a base layer (70) and a plurality of through-electrodes (74) penetrating the base layer, and having a pair of first edges opposite to each other in a first direction (Fig. 13 horizontal) and a pair of second edges opposite to each other in a second direction (Fig. 13 vertical) orthogonal to the first direction;
a stacked structure (400A) attached to the silicon interposer, the stacked structure comprising a first semiconductor chip (bottommost chip) including a first semiconductor substrate (402) and a plurality of first through-electrodes (410) penetrating the first semiconductor substrate, a plurality of second semiconductor chips (chips above bottommost chip) sequentially stacked on the first semiconductor chip and including a second semiconductor substrate (408) and a plurality of second through-electrodes (410) penetrating the second semiconductor substrate and electrically connected to the plurality of first through-electrodes (through 406), and a chip molding layer (414 para 0070) on a side surface of the plurality of second semiconductor chips;
a plurality of third semiconductor chips (400B) attached to the interposer adjacent the stacked structure; and
a package molding layer (112) on the silicon interposer, the package molding layer extending around the stacked structure and the plurality of third semiconductor chips to form a molding interface (interface between 414 and 112) with the chip molding layer,
wherein the plurality of third semiconductor chips comprise a first chip group (Fig. 13; para 0065, left stacks 88/110 equivalent of 400B) arranged in a row along one of the first edges, and a second chip group (Fig. 13; para 0065, right stacks 88/110 equivalent of 400B) arranged in a row along the other one of the first edges, and
wherein the stacked structure group is spaced apart from each of the first edges (Figs. 13 and 19), and
the chip molding layer (414) has a first thickness in the second direction from a side surface of the plurality of second semiconductor chips, and the package molding layer (112) has a second thickness in the second direction that is at least twice greater than the first thickness (Figs. 13, 19 and 20), and
a side surface of the at least one stacked structure adjacent to one of the second edges is not closer to the one of the second edges than a side surface of a third semiconductor chip adjacent to the one of the second edges (Fig. 13; 88/110 equivalent of 400B closer to vertical edge than 68 equivalent of 400A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the stacked structure group having a plurality of stacked structures similar to that of Yu 400A since such an addition would add further functionality using the noted devices in para 0018. Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 19, Yu discloses:
wherein the first semiconductor chip is an HDM control die, the second semiconductor chip is a DRAM die (para 0018).
Although Yu does not specifically disclose “at least one of the plurality of third semiconductor chips has a plurality of functional blocks, and at least one of the plurality of third semiconductor chips has one functional block”, Yu does provide insight, in para 0026, that the dies 88 (stack 400B) have a memory controller and memory dies in the stack. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the memory controller would employ a number of functional blocks such as logic and on-board cache memory for executable instructions for instance while the memory chiplets would employ at least functional memory blocks.
Regarding claim 20, although Yu does not specifically disclose “”wherein the first thickness is from about 150um to about 400um, and the second thickness is from about 500um to about 1000um”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the first and second thicknesses of Yu’s molding layers 414 and 112 since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
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/ERROL V FERNANDES/Primary Examiner, AU 2893