DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 2/20/2026 is acknowledged.
Applicant amended claims 13 and 18; and cancelled claims 16 and 17.
Applicant added claim 21.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/23/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US 2014/0004682) (hereafter Yuan), in view of Kim et al. (US 2021/0028112) (hereafter Kim).
Regarding claim 13, Yuan discloses a semiconductor device, comprising:
a plurality of transistors 66 (Fig. 10A, paragraph 0024) arranged in a layer of dielectric material (“liner oxide” in paragraph 0017) such that an end surface of each transistor (left 66 in Fig. 10A) is in direct contact with a layer of silicon 20 (Fig. 10A, paragraph 0013, wherein “silicon”); and
a shallow trench isolation region (upper portions of 34’ and 50’ in Fig. 10A, paragraph 0022) formed in the layer of silicon 20 (Fig. 10A) such that the end surface of each of a first transistor (transistor with first 40 from the left corner of Fig. 10A, paragraph 0024) and a second transistor (transistor with fourth 40 from the left corner of Fig. 10A, paragraph 0024) of the plurality of transistors (left 66 in Fig. 10A) is in direct contact with the shallow trench isolation region (lower portion of 34’ and lower portion of 50’ in Fig. 10A), wherein:
the shallow trench isolation region (upper portions of 34’ and 50’ in Fig. 10A) includes first (upper portion of first 34’ from the left corner of Fig. 10A) and second areas (upper portion of fifth 34’ from the left corner of Fig. 10A) of a first isolation material (see paragraph 0018, wherein “low-k materials, such as boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), and/or the like”) and a third area (upper portion of second 50’ from the left corner of Fig. 10A) of a second isolation material (see paragraph 0021, wherein “silicon oxide”) that is different (see paragraph 0021, wherein “Dielectric material 50 has a k value greater than the k value of low-k dielectric material 34”) than the first isolation material, and
the first (upper portion of first 34’ from the left corner of Fig. 10A) and second areas upper portion of (fifth 34’ from the left corner of Fig. 10A) are separated from one another by the third area (upper portion of second 50’ from the left corner of Fig. 10A).
Yuan does not disclose a contact via electrically connecting one of the plurality of transistors with a buried power rail; and
the shallow trench isolation region extends from a first end surface to a second end surface,
the layer of dielectric material extends from a third end surface to a fourth end surface, the layer of dielectric material arranged such that the fourth end surface is in direct contact with the first end surface,
the contact via extends from the second end surface to the third end surface and is narrower at the fourth end surface than at the first end surface.
Kim discloses a contact via (180, 120 and 255 in Fig. 2) electrically connecting one of the plurality of transistors (“transistor” in paragraph 0027) with a buried power rail (ML2 in Fig. 2, paragraph 0049, wherein “power lines”); and
the shallow trench isolation region (upper portion of 162 and 131 in Fig. 2) extends from a first end surface (top surface of 131 in Fig. 2) to a second end surface (bottom surface of 131 in Fig. 2),
the layer of dielectric material (165 and 135 in Fig. 2) extends from a third end surface (top surface of 165 in Fig. 2) to a fourth end surface (bottom surface of 135 in Fig. 2), the layer of dielectric material (165 and 135 in Fig. 2) arranged such that the fourth end surface (bottom surface of 135 in Fig. 2) is in direct contact with the first end surface (top surface of 131 in Fig. 2),
the contact via (180, 120 and 255 in Fig. 2) extends from the second end surface (bottom surface of 131 in Fig. 2) to the third end surface (top surface of 165 in Fig. 2) and is narrower at the fourth end surface (bottom surface of 135 in Fig. 2) than at the first end surface (top surface of 131 in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yuan to form a contact via electrically connecting one of the plurality of transistors with a buried power rail; and the shallow trench isolation region extends from a first end surface to a second end surface, the layer of dielectric material extends from a third end surface to a fourth end surface, the layer of dielectric material arranged such that the fourth end surface is in direct contact with the first end surface, the contact via extends from the second end surface to the third end surface and is narrower at the fourth end surface than at the first end surface, as taught by Kim, since when a conductive through structure (Kim, paragraph 0144) such as a through silicon via may be formed on a substrate and connected to a buried conductive wiring, a short circuit with other adjacent components (for example, an active region such as Si) may be prevented without decreasing the size of the conductive through structure.
Regarding claim 18, Yuan in view of Kim discloses the semiconductor device of claim 13, however Yuan does not disclose the contact via is narrower at the fourth end surface than at the third end surface.
Kim discloses the contact via (180, 120 and 255 in Fig. 2) is narrower at the fourth end surface (bottom surface of 135 in Fig. 2) than at the third end surface (top surface of 165 in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yuan to form the contact via is narrower at the fourth end surface than at the third end surface, as taught by Kim, since when a conductive through structure (Kim, paragraph 0144) such as a through silicon via may be formed on a substrate and connected to a buried conductive wiring, a short circuit with other adjacent components (for example, an active region such as Si) may be prevented without decreasing the size of the conductive through structure.
Regarding claim 21, Yuan further discloses the semiconductor device of claim 13, further comprising: a further shallow trench isolation region (lower portions of 34’ and 50’ in Fig. 10A, paragraph 0022) formed in the layer of silicon 20 (Fig. 2, paragraph 0023) such that the end surface of each of the second transistor (transistor with fourth 40 in Fig. 10A) and a third transistor (transistor with fifth 40 in Fig. 10A) of the plurality of transistors is in direct contact with the further shallow trench isolation region (lower portions of 34’ and 50’ in Fig. 10A), wherein:
the further shallow trench isolation region (lower portions of 34’ and 50’ in Fig. 10A) includes first (lower portion of first 34’ from the left corner of Fig. 10A) and second areas (lower portion of fifth 34’ from the left corner of Fig. 10A) of the first isolation material (see paragraph 0018, wherein “low-k materials, such as boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), and/or the like”).
Yuan does not disclose the first and second areas of the further shallow trench isolation region are separated from one another by the contact via.
Kim discloses the first (left lower portion of 162 in Fig. 2) and second areas (right lower portion of 162 in Fig. 2) of the further shallow trench isolation region (lower portion of 162 in Fig. 2) are separated from one another by the contact via (180, 120 and 255 in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yuan to form the first and second areas of the further shallow trench isolation region are separated from one another by the contact via, as taught by Kim, since when a conductive through structure (Kim, paragraph 0144) such as a through silicon via may be formed on a substrate and connected to a buried conductive wiring, a short circuit with other adjacent components (for example, an active region such as Si) may be prevented without decreasing the size of the conductive through structure.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yuan in view of Kim as applied to claim 13 above, and further in view of Chung et al. (US 2022/0367454) (hereafter Chung).
Regarding claim 14, Yuan in view of Kim discloses the semiconductor device of claim 13, however Yuan and Kim do not disclose the buried power rail is in direct contact with a backside power distribution network.
Chung discloses the buried power rail 36 (Fig. 31B, paragraph 0094) is in direct contact with a backside power distribution network 166 (Fig. 31B, paragraph 0014).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yuan to form the buried power rail is in direct contact with a backside power distribution network, as taught by Chung, since the backside (Kim, paragraph 0047) of the semiconductor die may accommodate wider power rails, reducing resistance and increasing efficiency of power delivery to the FinFETs.
Allowable Subject Matter
1. Claims 1-12 and 19-20 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Hsu et al. (US 20210359091), discloses a shallow trench isolation region 230 (Fig. 20D, paragraph 0021) extending from a first end surface (bottom surface of 230 in Fig. 20D) to a second end surface (top surface of 230 in Fig. 20D); and a contact via (element number is not shown in Fig. 21B but see 282 in Fig. 20B, paragraph 0050) electrically connecting the transistor to a buried power rail 284 (Fig. 21B, paragraph 0050) but fails to disclose the contact via extending from the second end surface to the third end surface, wherein the contact via is narrower at the fourth end surface than at the first end surface. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: the contact via extending from the second end surface to the third end surface, wherein the contact via is narrower at the fourth end surface than at the first end surface in combination with other elements of claim 1.
In addition, Yuan et al. (US 2014/0004682), discloses forming a plurality of shallow trench isolation regions (34’ and 50’ in Fig. 10A, paragraph 0022) in a layer of silicon 20 (Fig. 10A, paragraph 0013, wherein “silicon”) such that each shallow trench isolation region (34’ and 50’ in Fig. 10A) includes a first area 34’ (Fig. 10A, paragraph 0022) of a first isolation material (see paragraph 0018, wherein “low-k materials, such as boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), and/or the like”) and a second area 50’ (Fig. 10A, paragraph 0022) of a second isolation material (see paragraph 0021, wherein “silicon oxide”); forming a layer of dielectric material 62 (Fig. 10A, paragraph 0024) having a third end surface (bottom surface of 62 in Fig. 10A) in direct contact with the first end surface (top surface of 34’ and 50’) of each shallow trench isolation region (34’ and 50’ in Fig. 10A ) and a fourth end surface (top surface of 62 in Fig. 10A) opposite the third end surface (bottom surface of 62 in Fig. 10A); and forming a first trench (region between 62 in Fig. 10A) portion through the layer of dielectric material 62 (Fig. 10A) but fails to disclose the first trench portion is wider at the fourth end surface than at the third end surface and exposes the first end surface of one of the plurality of shallow trench isolation regions; forming a second trench portion by removing the second area of the one of the plurality of shallow trench isolation regions such that the first trench portion and the second trench portion are continuous with one another; and forming a contact via by filling the first and second trench portions with metal material such that the contact via is wider at the first end surface than at the third end surface. Additionally, the prior art does not teach or suggest a method of making a semiconductor device, the method comprising: the first trench portion is wider at the fourth end surface than at the third end surface and exposes the first end surface of one of the shallow trench isolation regions; forming a second trench portion by removing the second area of the one of the shallow trench isolation regions such that the first trench portion and the second trench portion are continuous with one another; and forming a contact via by filling the first and second trench portions with metal material such that the contact via is wider at the first end surface than at the third end surface in combination with other elements of claim 19.
A closest prior art, Hsu et al. (US 20210359091), discloses a semiconductor device, comprising: a shallow trench isolation region 230 (Fig. 20D, paragraph 0021) extending from a first end surface (bottom surface of 230 in Fig. 20D) to a second end surface (top surface of 230 in Fig. 20D); an inner layer dielectric region (region between 230 and 270 in Fig. 20D; and see 269 in Fig. 15, paragraph 0028) extending from a third end surface (bottom surface of region between 230 and 270 in Fig. 20D) to a fourth end surface (top surface of region between 230 and 270 in Fig. 20D), the inner layer dielectric region (region between 230 and 270 in Fig. 20D; and see 269 in Fig. 15) arranged such that the fourth end surface (top surface of region between 230 and 270 in Fig. 20D) is in direct contact with the first end surface (bottom surface of 230 in Fig. 20D); a transistor (240’, 260, 215 in Fig. 21B) arranged in (see Fig. 20D, wherein 260 is wrapped in the inner layer dielectric region (see 269 in Fig. 15)) the inner layer dielectric region (region between 230 and 270 in Fig. 20D; and see 269 in Fig. 15); and a contact via (element number is not shown in Fig. 21B but see 282 in Fig. 20B, paragraph 0050) electrically connecting the transistor to a buried power rail 284 (Fig. 21B, paragraph 0050) but fails to teach the contact via extending from the second end surface to the third end surface, wherein the contact via is narrower at the fourth end surface than at the first end surface as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-12 depend on claim 1.
In addition, a closest prior art, Yuan et al. (US 2014/0004682), discloses a method of making a semiconductor device, the method comprising: forming a plurality of shallow trench isolation regions (34’ and 50’ in Fig. 10A, paragraph 0022) in a layer of silicon 20 (Fig. 10A, paragraph 0013, wherein “silicon”) such that each shallow trench isolation region (34’ and 50’ in Fig. 10A) includes a first area 34’ (Fig. 10A, paragraph 0022) of a first isolation material (see paragraph 0018, wherein “low-k materials, such as boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), and/or the like”) and a second area 50’ (Fig. 10A, paragraph 0022) of a second isolation material (see paragraph 0021, wherein “silicon oxide”) that is different (see paragraph 0021, wherein “Dielectric material 50 has a k value greater than the k value of low-k dielectric material 34”) than the first isolation material and such that each of the first 34’ (Fig. 10A) and second areas 50’ (Fig. 10A) extends from a first end surface (top surface of 34’ and 50’) to a second end surface (bottom surface of 34’ and 50’) of each shallow trench isolation region (34’ and 50’ in Fig. 10A); forming a layer of dielectric material 62 (Fig. 10A, paragraph 0024) having a third end surface (bottom surface of 62 in Fig. 10A) in direct contact with the first end surface (top surface of 34’ and 50’) of each shallow trench isolation region (34’ and 50’ in Fig. 10A ) and a fourth end surface (top surface of 62 in Fig. 10A) opposite the third end surface (bottom surface of 62 in Fig. 10A); and forming a first trench (region between 62 in Fig. 10A) portion through the layer of dielectric material 62 (Fig. 10A) but fails to teach the first trench portion is wider at the fourth end surface than at the third end surface and exposes the first end surface of one of the plurality of shallow trench isolation regions; forming a second trench portion by removing the second area of the one of the plurality of shallow trench isolation regions such that the first trench portion and the second trench portion are continuous with one another; and forming a contact via by filling the first and second trench portions with metal material such that the contact via is wider at the first end surface than at the third end surface as the context of claim 19. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claim 20 depends on claim 19.
Response to Arguments
1. Applicant's arguments filed 2/20/2026 have been fully considered.
2. Applicant's arguments with respect to claims 13, 14, 18, and 21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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