Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
This is a response to the election filed on 9/23/2025.
Claims 1-14 = elected without traverse.
Claims 15-16 = non-elected and canceled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected because “ the functions” and “the row and the column” lack antecedent basis.
Claims 2-7 are rejected because they depend directly or indirectly from claim 1.
Claims 8-14 are rejected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a) (1) being anticipated
by the prior art of record Brown (US 2013/0159799)
Regarding claim 1, the prior art disclose:
A method to create a robust topology of a layout of cores for performing a function on an array of cores arranged in a grid (array/row-column/vertical-horizontal links of IO blocks/cores in fig 2-3, 5-7), the method comprising:
determining the location of at least one defective core of the array
(par 66, 68: specific areas/location of a core that are failing can often be identified);
assigning at least some of the cores in the array of cores to a configuration layout of an optimal initial topography of cores in the array (fig 2-3, 5-7);
determining whether the at least one defective core is in the configuration layout of the optimal initial topography (see one or more of abstract, summary and/or par 22-25, 64-70); and
assigning the functions of the cores in the row and the column of the at least one defective core to additional neighboring cores in the array of cores to create the robust topology (i.e., see at least:
if any processing core is determined to be faulty, that core can be deactivated and the spare core activated (par 68);
disabling the faulty core and remapping another core (par 84);
faulty cores are reconfigured/mapped/remapped (par 87-88);
identification of a faulty or failing functional unit may also be used to automatically configure a multi-core processor chip (par 24);
depending on the fail location, a failing core may be configured/reconfigured …or enabling an internal patch processor to work around failing logic components (par 66, 79))
(Claim 2) wherein the location of the at least one defective core of the array is determined from a core defect file generated from testing the array of cores (Built in self-test, test pattern generator, fault store/table/codes, fault comparison (abstract, summary, fig 6, 8))
(Claim 3) configuring the cores in the row and the column as wire cores connecting the cores of the configuration layout with the additional neighboring cores (fig 2-3).
(Claim 4) determining whether any of the wire cores may be contracted; and contracting the determined cores to produce a modified robust topology (i.e., reduce capacity/size, functional units may still be reconfigured to operate in a reduced capacity (par 84-85, 88)).
(Claim 5) wherein the initial topology is produced by a place and route algorithm (fig 2-3)
(Claim 6) wherein the cores in the array of cores are homogeneous (fig 2-3, 5-6)
(Claim 7) wherein the cores in the array are each coupled to at least one NOC router (fig 1-3), determining a NOC router in the robust topology has failed; and replacing the functions of the cores in the rows and columns of the cores coupled to the failed network on chip router to additional neighboring cores to create a new robust topology (fig 1-3).
Claims 8-14 recite similar subject matter and are rejected for the same reason.
Claims 1-14 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Liu (US 2021/0303426)
Regarding claim 1, the prior art disclose:
A method to create a robust topology of a layout of cores for performing a function on an array of cores arranged in a grid (fig 1, 4-6), the method comprising:
determining the location of at least one defective core of the array (test whether each core/processor is faulty (par 22, 59),fault in the multicore processor is identified (par 61));
assigning at least some of the cores in the array of cores to a configuration layout of an optimal initial topography of cores in the array (fig 1, 4, 6);
determining whether the at least one defective core array (test whether each core/processor is faulty (par 22, 59),fault in the multicore processor is identified (par 61)) is in the configuration layout of the optimal initial topography (fig 1, 4, 6); and
assigning the functions of the cores in the row and the column of the at least one defective core to additional neighboring cores in the array of cores to create the robust topology (i.e., see at least:
loaded instructions may then be distributed to each core assigned with the corresponding task (par 33, 35);
array can receive data from one or more adjacent processing elements and provide data to one or more other adjacent processing elements…dataflow can be configured through instructions sent to the chip (e.g., settings on multiplexers or routers on the multi-core processor). To continue this example, configuring the many-core processor to perform a task can include configuring the dataflow of the many-core processor (par 52-53)).
(Claim 2) wherein the location of the at least one defective core of the array is determined from a core defect file generated from testing the array of cores (title, fig 1, 3-6.
(Claim 3) configuring the cores in the row and the column as wire cores connecting the cores of the configuration layout with the additional neighboring cores (se wires/bus connecting cores in fig 1, 4-6).
(Claim 4) determining whether any of the wire cores may be contracted; and contracting the determined cores to produce a modified robust topology (see reduction and minimizing in par 46)
(Claim 5) wherein the initial topology is produced by a place and route algorithm (fig 1, 4-6).
(Claim 6) wherein the cores in the array of cores are homogeneous (fig 1, 4-6).
(Claim 7) wherein the cores in the array are each coupled to at least one NOC router (routers on the multi-core processor (par 53)), determining a NOC router in the robust topology has failed; and replacing the functions of the cores in the rows and columns of the cores coupled to the failed network on chip router to additional neighboring cores to create a new robust topology (fig 1, 4-6).
Claims 8-14 recite similar subject matter and are rejected for the same reason.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851