DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 and 16-20 in the reply filed on 3/3/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2022 and 4/11/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-8, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bouchakour et al. US 2007/0069278 and Terzioglu et al. US 2008/0291728.
Re claim 1, Bouchakour teaches a multi-time programmable memory cell (fig4A) comprising:
a floating gate (6, 40 and 41, fig4A, [37]) formed on a field insulating region (20, 21 and 22, fig4B, [4, 40]) formed on a semiconductor substrate (1, fig4B, [4]);
a control gate (50, 51, fig4A, [42]) formed on the field insulating region, the control gate located parallel to a first portion of the floating gate (40, fig4A, [37]);
a program-erase electrode (C, fig4B, [5]) formed on the field insulating region and proximate to a second portion of the floating gate (41, fig4B, [37]);
a first well region (15 or 11, fig4A, [4]) formed in the semiconductor substrate; and
a second well region (10, fig4A, [4]) formed in the semiconductor substrate,
a channel region (region under 6, fig4A and 4B, [37]) formed between the first well region and the second well region,
a third portion of the floating gate (6, fig4A, [37]) overlaying the channel region.
Bouchakour does not explicitly show the field insulating region is a field oxide region.
Terzioglu teaches STI region formed using oxide ([21]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bouchakour and Terzioglu to use oxide as the field insulating region material. The motivation to so is to achieve sufficient isolating and prevent leakage (Bouchakour, [7]; Terzioglu, [21]).
Re claim 3, Bouchakour modified above teaches the memory cell of claim 1, wherein the program-erase electrode is configured and arranged to receive a voltage sufficient to form a tunneling current between the program-erase electrode and the floating gate (Bouchakour, [37, 47]).
Re claim 4, Bouchakour modified above teaches the memory cell of claim 1, wherein coupling capacitance between the control gate and the floating gate is greater than coupling capacitance between the program-erase electrode and the floating gate (C=ε(A/d) overlapping area between 50/51 and 40 greater than electrode C and end of 41 and distance between 50/51 and 40 smaller than 41 and C formed on 16, fig4A).
Re claim 5, Bouchakour modified above teaches the memory cell of claim 1, wherein the first well region (11, fig4B, [4]) is characterized as a source current electrode and the second well region (10, fig4B, [4]) is characterized as a drain current electrode.
Re claim 6, Bouchakour modified above teaches the memory cell of claim 1, wherein the first well region (S 11, fig4B and 6, [4]) is configured for connection to a power supply and the second well region (D 10, fig4B and 6, [4]) is configured for connection to a bit line during a read operation of the memory cell.
Re claim 7, Bouchakour modified above teaches the memory cell of claim 1, wherein the field oxide region is formed as a shallow trench isolation (STI) region (20, 21 and 22 as STI oxide, fig4B, [4, 40]) or a local oxidation of silicon (LOCOS) region.
Re claim 8, Bouchakour modified above teaches the memory cell of claim 1, wherein the control gate (50, 51, fig4A, [42]) and the floating gate (6, 40 and 41, fig4A, [4, 42]) each comprise a polysilicon material.
Re claim 16, Bouchakour teaches a multi-time programmable memory cell (fig4A) comprising:
a first well region having a first conductivity type (P type 11, fig4A, [4]), the first well region formed in a semiconductor substrate (1 with N type 2 and 3, fig4B, [4]) having a second conductivity type (N type, fig4B);
a second well region (P type 10, fig4A, [4]) having the first conductivity type, the second well region formed in the semiconductor substrate such that a channel region (region under 6, fig4A and 4B, [37]) is formed between the first well region and the second well region;
a field insulating region (20, 21 and 22, fig4B, [4, 40]) formed on the semiconductor substrate;
a floating gate (6, 40 and 41, fig4A, [37]) formed on the field insulating region such that a first portion of the floating gate (6, fig4A, [37]) is formed over the channel region;
a control gate (50, 51, fig4A, [42]) formed on the field insulating region, the control gate located parallel and proximate to a second portion of the floating gate (40, fig4A, [37]); and
a program-erase electrode (C, fig4B, [5]) formed on the field insulating region, the program-erase electrode located proximate to a third portion of the floating gate (41, fig4B, [37]).
Bouchakour does not explicitly show the field insulating region is a field oxide region.
Terzioglu teaches STI region formed using oxide ([21]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bouchakour and Terzioglu to use oxide as the field insulating region material. The motivation to so is to achieve sufficient isolating and prevent leakage (Bouchakour, [7]; Terzioglu, [21]).
Re claim 18, Bouchakour modified above teaches the memory cell of claim 16, wherein the program-erase electrode is configured and arranged to receive a voltage sufficient to form a tunneling current between the program-erase electrode and the floating gate (Bouchakour, [37, 47]).
Re claim 19, Bouchakour modified above teaches the memory cell of claim 16, wherein the first well region (S 11, fig4B and 6, [4]) is configured for connection to a power supply and the second well region (D 10, fig4B and 6, [4]) is configured for connection to a bit line during a read operation of the memory cell.
Re claim 20, Bouchakour modified above teaches the memory cell of claim 16, wherein the field oxide region is formed as a shallow trench isolation (STI) region (20, 21 and 22 as STI oxide, fig4B, [4, 40]) or a local oxidation of silicon (LOCOS) region.
Claim(s) 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bouchakour et al. US 2007/0069278, Terzioglu et al. US 2008/0291728 and Wang et al. US 2005/0199936.
Re claim 2, Bouchakour does not explicitly show the memory cell of claim 1, further comprising a spacer dielectric formed on the field oxide region between the floating gate and the program-erase electrode.
Wang teaches forming spacer dielectric (595, fig5, [31]) around floating gate (FG 555, fig5, [31]) used for the formation of the S/D region (540, 590 and 525, fig5, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bouchakour, Terzioglu and Wang form spacers around FG 6/40/41 to protect the gate electrode during formation of the S/D region and assist the formation of the S/D region with add in LDD region. The motivation to so is to achieve greater programming efficiency (wang, [31]).
Re claim 17, Bouchakour does not explicitly show the memory cell of claim 16, further comprising a spacer dielectric formed on the field oxide region between the floating gate and the program-erase electrode.
Wang teaches forming spacer dielectric (595, fig5, [31]) around floating gate (FG 555, fig5, [31]) used for the formation of the S/D region (540, 590 and 525, fig5, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bouchakour, Terzioglu and Wang form spacers around FG 6/40/41 to protect the gate electrode during formation of the S/D region and assist the formation of the S/D region with add in LDD region. The motivation to so is to achieve greater programming efficiency (wang, [31]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bouchakour et al. US 2007/0069278, Terzioglu et al. US 2008/0291728 and Hong US 2012/0273851.
Re claim 9, Bouchakour does not explicitly show the memory cell of claim 1, wherein the program-erase electrode is formed as a metal contact.
Hong teaches contact plug formed of metal (220 as W and 240 as Cu, fig3 and 5, [56, 60]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bouchakour, Terzioglu and Hong to form the contact using tungsten with upper part replaced by copper . The motivation to so is to reduce contact resistance (Hong, [66]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOMING LIU/Examiner, Art Unit 2812
Prosecution Insights