DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 6 (and dependent claims 7-10, 16-19) is/are objected to because of the following informalities: The claims do not recite what the abbreviation “JIMD” stands for in claim 6, line 21. For the purpose of the examination, the "JIMD" will be considered as “intermetal dielectric”.
Appropriate correction is required.
Claim(s) 11 (and dependent claims 11-15, 20-22) is/are objected to because of the following informalities: The claims do not recite what the abbreviation “JIMD” stands for in claim 11, line 21. For the purpose of the examination, the "JIMD" will be considered as “intermetal dielectric”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng(USPGPUB DOCUMENT: 2019/0371725, hereinafter Cheng) in view of Preisler (USPGPUB DOCUMENT: 2021/0217908, hereinafter Preisler) and Shu (USPGPUB DOCUMENT: 2020/0294871, hereinafter Shu).
Re claim 6 Cheng discloses in Fig 3A-C, 9A/9B a method for forming a semiconductor device comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes circuit components disposed on an active surface thereof; forming a dielectric, includes a metal dielectric layer Mi(dielectric)[0095] with metal interconnects or metal lines(MLsi) (907/908), and a via dielectric {Vi) layer (dielectric)[0095] above the Mi, the Vi layer (dielectric)[0095] includes via contacts (VCsi) (929/927), a process control[0049], wherein the PCM structure includes a lower PCM interconnect (PCMLMLi) (906/908) disposed Mi(dielectric)[0095], PCM via contacts (PCMVCsi) (929/927), disposed proximately to the PCMLMLi in Mi without contacting the PCMLMLi or any other lower metal lines in any lower JIMDs, the PCMVCsi extend below a top surface of the PCMLMLi (906/908) by an overlap distance OV (distance between 906/908 and 929/927) which is less than the full depth of Mi, the PCMVCsi (929/927) are separated from the PCMLMLi by the metal dielectric layer of Mi, and an upper PCM interconnect(906/908) (PCMUMLi) of PCMi in Mi+1, wherein the PCMUMLi (906/908) is coupled to top surfaces of the PCMVCsi (929/927) to form a via chain capacitor(933); and measuring the capacitance[0048].
Cheng does not disclose forming a BEOL dielectric; a dielectric having x number of intermetal dielectric (IvD) layers, a process control[0049] monitoring (PCM) structure (PCMi) of Mi for monitoring via contact landing of VCsi (929/927) of Vi landing on MLsi (907/908) of Mi; and applying a test voltage to the PCM structure and measuring the PCM capacitance[0048] which indicates a depth of the PCM via contacts(929/927) relative to the PCM lower interconnect (PCMLMLi) (906/908); in Mi without contacting the PCMLMLi(906/908) or any other lower metal lines in any lower JIMD’s,
Preisler disclose in Fig 6 forming a BEOL dielectric[0051 of Preisler]; a dielectric having x number of intermetal dielectric (IvD) layers (260/268/270 of Preisler), a process control[0049] monitoring (PCM) structure (PCMi) (256/246 of Preisler) of Mi for monitoring via contact (264b/c of Preisler) landing of VCsi of Vi (260 of Preisler) landing on MLsi (266/272 of Preisler) of Mi(268/270 of Preisler); and applying a test voltage[0054 of Preisler] to the PCM structure and measuring [0056 of Preisler] the PCM capacitance[0048] which indicates a depth [0026 of Preisler] of the PCM via contacts(929/927) relative to the PCM lower interconnect (PCMLMLi) (906/908);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Preisler to the teachings of Cheng in order to efficiently and effectively implementing process control monitoring devices with improved productivity [0005, Preisler]. In doing so, forming a BEOL dielectric[0051 of Preisler]; a dielectric having x number of intermetal dielectric (IMD) layers, wherein an i” intermediate dielectric layer (ILD) layer, where i = 1 to x(260/268/270 of Preisler), wherein the i ILD layer and Mi+1 also includes a process control monitoring (PCM) structure(256/246 of Preisler) for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi (260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi(268/270 of Preisler); and applying a test voltage[0054 of Preisler] to the PCM structure and measuring[0056 of Preisler] the PCM capacitance[0048 of Cheng] which indicates a depth[0026 of Preisler] of the PCM via contacts(929/927 of Cheng) relative to the PCM lower interconnect(906/908 of Cheng);
Cheng and Preisler does not disclose disposed proximately to the PCMLMLi in Mi without contacting the PCMLMLi or any other lower metal lines in any lower JIMDs, the PCMVCsi extend below a top surface of the PCMLMLi by an overlap distance OV which is less than the full depth of Mi, the PCMVCsi are separated from the PCMLMLi by the metal dielectric layer of Mi,
and applying a test voltage to the PCMi structure and measuring a PCM capacitance to determine a via etch depth of the PCMVCsi relative to the PCMLMLsi
Shu discloses (MT) disposed proximately to the PCMLMLi[0046 of Shu] in Mi without contacting the PCMLMLi or any other lower metal lines [0048 of Shu] in any lower JIMDs, the PCMVCsi extend below a top surface of the PCMLMLi by an overlap distance OV[0042 of Shu] which is less than the full depth of Mi, the PCMVCsi are separated from the PCMLMLi by the metal dielectric layer of Mi[0031 of Shu],
and applying a test voltage[0030 of Shu] to the PCMi structure and measuring a PCM capacitance[0035,0046 of Shu] to determine a via etch depth[0024 of Shu] of the PCMVCsi relative to the PCMLMLsi
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shu to the teachings of Cheng in order to properly prepared is capable of conducting electricity under certain controllable conditions, such as the application of the small electrical charge [0001, Shu].
Re claim 7 Cheng, Preisler and Shu disclose the method of claim 6, wherein PCM structures(256/246 of Preisler) are disposed in all EID levels layers.
Re claim 8 Cheng, Preisler and Shu disclose the method of claim 6, wherein PCM structures(256/246 of Preisler) are disposed in at least one IMD level layer.
Re claim 9 Cheng, Preisler and Shu disclose the method of claim 6, wherein applying the test voltage to the PCM structure(256/246 of Preisler) is performed after each IMD layer is completed.
Re claim 10 Cheng, Preisler and Shu disclose the method of claim 6, wherein applying the test voltage[0049 of Preisler] to the PCM structure is performed after PCM structures(256/246 of Preisler) for all layers are completed.
Re claim 11 Cheng discloses in Fig 3A-C, 9A/9B a method for forming a semiconductor device comprising: providing a semiconductor wafer, wherein the semiconductor wafer includes a plurality of devices with circuit components[0050] disposed on an active surface thereof, the devices are arranged in a matrix of devices with rows and columns(Fig 3B/3C), wherein the devices are separated by a kerf region between rows and columns of devices[0047]; forming a BEOL dielectric for the devices having x number of intermetal dielectric (IMD) layers, wherein forming an ith IMD layer, where i = 1 to x, includes a metal dielectric layer Mi(dielectric)[0095] with metal interconnects or metal lines (MLsi) (907/908), and a Vi layer Vi(dielectric)[0095] above the Mi, the via dielectric layer includes via contacts(929/927), a metal dielectric layer Mi+1(dielectric)[0095] with metal lines(907/908) (MLsi+1), wherein the VCsi are configured to couple metal lines of Mi and Mi+1; process control [0049] monitoring (PCMi) structures of IMDi for monitoring via contact landing of VCsi Vi landing on MLsi of Mi for the devices, wherein the PCMi structures for the devices are formed in the kerf region of the wafer, wherein the PCMi structures includes PCM capacitance to determine a via etch depth of the PCMVCsi via contacts relative to the PCMLMLsi.
Cheng does not disclose forming a BEOL dielectric for the devices having x number of intermetal dielectric (IMD) layers, wherein an ith intermediate dielectric layer (ILD) layer, where i = 1 to x, also includes process control[0049] monitoring (PCM) structures of IMDi for monitoring via contact landing of via contacts(929/927) of Vi landing on metal lines(907/908) of Mi for the devices, PCMLMLsi in Mi without contacting the PCMLMLsi or any other lower metal lines in any lower JIMDs, the PCMVCsi
and applying a test voltage to the PCMistructures and measuring a PCM capacitance[0048] to determine a via etch depth of the PCMVCsi via contacts(929/927) relative to the PCMLMLsi.
Preisler disclose in Fig 6 forming a BEOL dielectric[0051 of Preisler] for the devices having x number of intermetal dielectric (IMD) layers, wherein forming an ith intermediate dielectric layer (ILD) layer, where i = 1 to x (260/268/270 of Preisler),
also includes process control[0049] monitoring (PCM) structures (256/246 of Preisler) of IMDi for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi (260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi(268/270 of Preisler) for the devices,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Preisler to the teachings of Cheng in order to efficiently and effectively implementing process control monitoring devices with improved productivity [0005, Preisler]. In doing so, a BEOL dielectric[0051 of Preisler] for the devices having x number of intermetal dielectric (IMD) layers, wherein an ith intermediate dielectric layer (ILD) layer, where i = 1 to x (260/268/270 of Preisler), also includes process control monitoring (PCM) structures(256/246 of Preisler) for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi(260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi (268/270 of Preisler) for the devices, and applying a test voltage[0054 of Preisler] to the PCM structures and measuring[0056 of Preisler] the PCM capacitance[0048 of Cheng] which indicates a depth[0026 of Preisler] of the PCM via contacts(929/927 of Cheng) relative to the PCM lower interconnect(906/908 of Cheng).
Cheng and Preisler does not disclose disposed proximately to the PCMLMLsi in Mi without contacting the PCMLMLsi or any other lower metal lines in any lower JIMDs, the PCMVCsi extend below top surfaces of the PCMLMLsi by an overlap distance OV which is less than a thickness of Mi, the PCMVCsi
applying a test voltage to the PCMistructures and measuring a PCM capacitance to determine a via etch depth of the PCMVCsi via contacts relative to the PCMLMLsi
Shu discloses disposed proximately to the PCMLMLsi[0046 of Shu] in Mi without contacting the PCMLMLsi or any other lower metal lines[0048 of Shu] in any lower JIMDs, the PCMVCsi extend below top surfaces of the PCMLMLsi by an overlap distance OV [0042 of Shu] which is less than a thickness of Mi [0031 of Shu], the PCMVCsi applying a test voltage [0030 of Shu] to the PCMistructures and measuring a PCM capacitance[0035,0046 of Shu] to determine a via etch depth[0024 of Shu] of the PCMVCsi via contacts relative to the PCMLMLsi
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shu to the teachings of Cheng in order to properly prepared is capable of conducting electricity under certain controllable conditions, such as the application of the small electrical charge [0001, Shu].
Re claim 12 Cheng, Preisler and Shu disclose the method of claim 11, wherein the PCM structures(256/246 of Preisler) are disposed in all IMD levels layers.
Re claim 13 Cheng, Preisler and Shu disclose the method of claim 11, wherein the PCM structures(256/246 of Preisler) are disposed in at least one IMD level layer.
Re claim 14 Cheng, Preisler and Shu disclose the method of claim 11, wherein applying the test voltage[0054 of Preisler] to the PCM structure is performed each layers completed.
Re claim 15 Cheng, Preisler and Shu disclose the method of claim 11, wherein applying the test voltage[0054 of Preisler] to the PCM structure is performed after PCM structures(256/246 of Preisler) for all layers are completed.
Re claim 16 Cheng, Preisler and Shu disclose the method of claim 6 further comprises: forming a pre-metal dielectric below the metal dielectric M1 with metal lines(907/908),forming pre-metal via contacts(929/927), and wherein the pre-metal via contacts(929/927) are coupled to the metal dielectric M1 with metal lines(907/908) and contact regions on the active surface of the semiconductor substrate.
Re claim 17 Cheng, Preisler and Shu disclose the method of claim 6 further comprises forming a pad metal (MP) dielectric with metal pads above the metal dielectric layer Mi(dielectric)[0095], wherein the PCM via contacts(929/927) of Vi are coupled to the upper PCM interconnect(906/908) in the MP.
Re claim 18 Cheng, Preisler and Shu disclose the method of claim 6, wherein the lower PCM interconnect(906/908) is an M-shaped or double U-shaped interconnect(906/908), and the upper interconnect(906/908) is a U-shaped interconnect(906/908).
Re claim 19 Cheng, Preisler and Shu disclose the method of claim 6, wherein the semiconductor device is a part of a wafer with a plurality of semiconductor devices separated by a kerf region(see Fig 3A of Preisler), wherein the PCM structures(256/246 of Preisler) are disposed in the kerf region of the wafer between the semiconductor devices.
Re claim 20 Cheng, Preisler and Shu disclose the method of claim 11 further co rises: forming a pre-metal dielectric below the metal dielectric M1 with metal lines(907/908),forming pre-metal via contacts(929/927), and wherein the pre-metal via contacts(929/927) are coupled to the metal dielectric M1 with metal lines(907/908) and contact regions on the active surface of the semiconductor substrate.
Re claim 21 Cheng, Preisler and Shu disclose the method of claim 11 further comprises forming a pad metal (MP) dielectric with metal pads above the metal dielectric layer Mi(dielectric)[0095], the PCM via contacts(929/927) of Vi are coupled to the upper PCM interconnect(906/908) in the MP.
Re claim 22 Cheng, Preisler and Shu disclose the method of claim 11, wherein the lower PCM interconnect(906/908) is an M-shaped or double U-shaped interconnect(906/908), and the upper interconnect(906/908) is a U-shaped interconnect(906/908).
Response to Arguments
Applicant’s arguments with respect to claim(s) 6-22 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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