DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 6-15, 16-22 in the reply filed on 09/15/25 is acknowledged. Applicant did not provide an argument regarding the traversal.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng(USPGPUB DOCUMENT: 2019/0371725, hereinafter Cheng) in view of Preisler (USPGPUB DOCUMENT: 2021/0217908, hereinafter Preisler).
Re claim 6 Cheng discloses in Fig 3A-C, 9A/9B a method for forming a semiconductor device comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes circuit components disposed on an active surface thereof; forming a dielectric, includes forming a metal dielectric layer Mi(dielectric)[0095] with metal lines(907/908), and forming a via dielectric layer Vi(dielectric)[0095] above the Mi, the via dielectric layer Vi(dielectric)[0095] includes via contacts(929/927), the via contacts(929/927) are coupled to metal lines(907/908) of Mi and Mi+1; forming a metal dielectric layer Mi+1(dielectric)[0095] with metal lines(907/908); wherein forming the i ILD layer and Mi+1 also includes forming a process control[0049], wherein forming the PCM structure includes forming a lower PCM interconnect(906/908) disposed on the metal dielectric layer Mi(dielectric)[0095], forming PCM via contacts(929/927), wherein the PCM via contacts(929/927) are disposed proximately to the lower metal interconnect(906/908) and extend below a top surface of the lower PCM interconnect(906/908) by an overlap distance OV (distance between 906/908 and 929/927), the PCM via contacts(929/927) are separated by the metal dielectric layer of Mi, forming an upper PCM interconnect(906/908) disposed on Mi+1, wherein the upper interconnect(906/908) is coupled to top surfaces of the PCM via contacts(929/927) to form a via chain capacitor(933); and measuring the capacitance[0048].
Cheng does not disclose forming a BEOL dielectric; forming a dielectric having x number of intermetal dielectric (IMD) layers, wherein forming an i” intermediate dielectric layer (ILD) layer, where i = 1 to x, wherein forming the i ILD layer and Mi+1 also includes forming a process control[0049] monitoring (PCM) structure for monitoring via contact landing of via contacts(929/927) of Vi landing on metal lines(907/908) of Mi; and applying a test voltage to the PCM structure and measuring the PCM capacitance[0048] which indicates a depth of the PCM via contacts(929/927) relative to the PCM lower interconnect(906/908).
Preisler disclose in Fig 6 forming a BEOL dielectric[0051 of Preisler]; forming a dielectric having x number of intermetal dielectric (IMD) layers, wherein forming an i” intermediate dielectric layer (ILD) layer, where i = 1 to x(260/268/270 of Preisler), wherein forming the i ILD layer and Mi+1 also includes forming a process control monitoring (PCM) structure(256/246 of Preisler) for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi (260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi(268/270 of Preisler); and applying a test voltage[0054 of Preisler] to the PCM structure and measuring[0056 of Preisler] which indicates a depth[0026 of Preisler]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Preisler to the teachings of Cheng in order to efficiently and effectively implementing process control monitoring devices with improved productivity [0005, Preisler]. In doing so, forming a BEOL dielectric[0051 of Preisler]; forming a dielectric having x number of intermetal dielectric (IMD) layers, wherein forming an i” intermediate dielectric layer (ILD) layer, where i = 1 to x(260/268/270 of Preisler), wherein forming the i ILD layer and Mi+1 also includes forming a process control monitoring (PCM) structure(256/246 of Preisler) for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi (260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi(268/270 of Preisler); and applying a test voltage[0054 of Preisler] to the PCM structure and measuring[0056 of Preisler] the PCM capacitance[0048 of Cheng] which indicates a depth[0026 of Preisler] of the PCM via contacts(929/927 of Cheng) relative to the PCM lower interconnect(906/908 of Cheng).
Re claim 7 Cheng and Preisler disclose the method of claim 6, wherein the PCM structures(256/246 of Preisler) are disposed in all EID levels layers.
Re claim 8 Cheng and Preisler disclose the method of claim 6, wherein the PCM structures(256/246 of Preisler) are disposed in at least one IMD level layer.
Re claim 9 Cheng and Preisler disclose the method of claim 6, wherein applying the test voltage to the PCM structure(256/246 of Preisler) is performed after each PCM structure for each level layer is completed.
Re claim 10 Cheng and Preisler disclose the method of claim 6, wherein applying the test voltage[0049 of Preisler] to the PCM structure is performed after the PCM structures(256/246 of Preisler) for all layers are completed.
Re claim 11 Cheng discloses in Fig 3A-C, 9A/9B a method for forming a semiconductor device comprising: providing a semiconductor wafer, wherein the semiconductor wafer includes a plurality of devices with circuit components[0050] disposed on an active surface thereof, the devices are arranged in a matrix of devices with rows and columns(Fig 3B/3C), wherein the devices are separated by a kerf region between rows and columns of devices[0047]; forming a BEOL dielectric for the devices having x number of intermetal dielectric (IMD) layers, wherein forming an ith intermediate dielectric layer (ILD) layer, where i = 1 to x, includes forming a metal dielectric layer Mi(dielectric)[0095] with metal lines(907/908), and forming a via dielectric layer Vi(dielectric)[0095] above the Mi, the via dielectric layer includes via contacts(929/927), the via contacts(929/927) are coupled to metal lines(907/908) of Mi and Mi + 1;forming a metal dielectric layer Mi+1(dielectric)[0095] with metal lines(907/908);wherein forming the ith ILD layer and Mi+1 for the devices also includes forming process control[0049], wherein the PCM structures for the devices are formed in the kerf region of the wafer, wherein forming the PCM structures includes forming lower PCM interconnect(906/908)s disposed on Mi for the devices, forming PCM via contacts(929/927), wherein the PCM via contacts(929/927) are disposed proximately to the lower metal interconnect(906/908)s and extend below a top surface of the lower PCM interconnect(906/908)s by an overlap distance OV (distance between 906/908 and 929/927), the PCM via contacts(929/927) are separated by dielectric of Mi, forming upper PCM interconnect(906/908)s disposed on Mi+1, wherein the upper interconnect(906/908)s are coupled to top surfaces of the PCM via contacts(929/927) to form via chain capacitor(933)s;
Cheng does not disclose forming a BEOL dielectric for the devices having x number of intermetal dielectric (IMD) layers, wherein forming an ith intermediate dielectric layer (ILD) layer, where i = 1 to x, also includes forming process control[0049] monitoring (PCM) structures for monitoring via contact landing of via contacts(929/927) of Vi landing on metal lines(907/908) of Mi for the devices, and applying a test voltage to the PCM structures and measuring the PCM capacitance[0048] which indicates a depth of the PCM via contacts(929/927) relative to the PCM lower interconnect(906/908).
Preisler disclose in Fig 6 forming a BEOL dielectric[0051 of Preisler] for the devices having x number of intermetal dielectric (IMD) layers, wherein forming an ith intermediate dielectric layer (ILD) layer, where i = 1 to x (260/268/270 of Preisler), also includes forming process control monitoring (PCM) structures(256/246 of Preisler) for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi(260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi (268/270 of Preisler) for the devices, and applying a test voltage[0054 of Preisler] to the PCM structures and measuring[0056 of Preisler] the PCM which indicates a depth[0026 of Preisler]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Preisler to the teachings of Cheng in order to efficiently and effectively implementing process control monitoring devices with improved productivity [0005, Preisler]. In doing so, forming a BEOL dielectric[0051 of Preisler] for the devices having x number of intermetal dielectric (IMD) layers, wherein forming an ith intermediate dielectric layer (ILD) layer, where i = 1 to x (260/268/270 of Preisler), also includes forming process control monitoring (PCM) structures(256/246 of Preisler) for monitoring via contact landing of via contacts(264b/c of Preisler) of Vi(260 of Preisler) landing on metal lines(266/272 of Preisler) of Mi (268/270 of Preisler) for the devices, and applying a test voltage[0054 of Preisler] to the PCM structures and measuring[0056 of Preisler] the PCM capacitance[0048 of Cheng] which indicates a depth[0026 of Preisler] of the PCM via contacts(929/927 of Cheng) relative to the PCM lower interconnect(906/908 of Cheng).
Re claim 12 Cheng and Preisler disclose the method of claim 11, wherein the PCM structures(256/246 of Preisler) are disposed in all IMD levels layers.
Re claim 13 Cheng and Preisler disclose the method of claim 11, wherein the PCM structures(256/246 of Preisler) are disposed in at least one IMD level layer.
Re claim 14 Cheng and Preisler disclose the method of claim 11, wherein applying the test voltage[0054 of Preisler] to the PCM structure is performed after each PCM structure for each layers completed.
Re claim 15 Cheng and Preisler disclose the method of claim 11, wherein applying the test voltage[0054 of Preisler] to the PCM structure is performed after PCM structures(256/246 of Preisler) for all layers are completed.
Re claim 16 Cheng and Preisler disclose the method of claim 6 further comprises: forming a pre-metal dielectric below the metal dielectric M1 with metal lines(907/908),forming pre-metal via contacts(929/927), and wherein the pre-metal via contacts(929/927) are coupled to the metal dielectric M1 with metal lines(907/908) and contact regions on the active surface of the semiconductor substrate.
Re claim 17 Cheng and Preisler disclose the method of claim 6 further comprises forming a pad metal (MP) dielectric with metal pads above the metal dielectric layer Mi(dielectric)[0095], wherein the PCM via contacts(929/927) of Vi are coupled to the upper PCM interconnect(906/908) in the MP.
Re claim 18 Cheng and Preisler disclose the method of claim 6, wherein the lower PCM interconnect(906/908) is an M-shaped or double U-shaped interconnect(906/908), and the upper interconnect(906/908) is a U-shaped interconnect(906/908).
Re claim 19 Cheng and Preisler disclose the method of claim 6, wherein the semiconductor device is a part of a wafer with a plurality of semiconductor devices separated by a kerf region(see Fig 3A of Preisler), wherein the PCM structures(256/246 of Preisler) are disposed in the kerf region of the wafer between the semiconductor devices.
Re claim 20 Cheng and Preisler disclose the method of claim 11 further co rises: forming a pre-metal dielectric below the metal dielectric M1 with metal lines(907/908),forming pre-metal via contacts(929/927), and wherein the pre-metal via contacts(929/927) are coupled to the metal dielectric M1 with metal lines(907/908) and contact regions on the active surface of the semiconductor substrate.
Re claim 21 Cheng and Preisler disclose the method of claim 11 further comprises forming a pad metal (MP) dielectric with metal pads above the metal dielectric layer Mi(dielectric)[0095], the PCM via contacts(929/927) of Vi are coupled to the upper PCM interconnect(906/908) in the MP.
Re claim 22 Cheng and Preisler disclose the method of claim 11, wherein the lower PCM interconnect(906/908) is an M-shaped or double U-shaped interconnect(906/908), and the upper interconnect(906/908) is a U-shaped interconnect(906/908).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812