DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/03/2026 has been entered.
Claim Objections
Claims 1 and 4-7 are objected to because of the following informalities:
Claim 1 recites “a thickness in the semiconductor substrate in the second region” (lines 1-2 of page 4) should be replaced with “a thickness of the semiconductor substrate in the second region”, to improve claim language.
Claim 1 recites “the semiconductor in the second region” (line 6 of page 4) should be replaced with “the semiconductor substrate in the second region”, for consistency with claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148369 to Aketa et al. (hereinafter Aketa) in view of Naito (US 2019/0288060) and Chen et al. (US 2015/0279980, hereinafter Chen).
With respect to claim 1, Aketa discloses a semiconductor device (e.g., a semiconductor chip including the IGBT 9 connected in parallel to the pn diode 10) (Aketa, Fig. 13, ¶0002, ¶0010-¶0040, ¶0117-¶0200) including a first region (e.g., an IGBT region including gate trench 55 above the collector region 37) and a second region (e.g., a diode region 10 above the cathode region 33/32), comprising:
a semiconductor substrate (23) (Aketa, Fig. 13, ¶0128-¶0130, ¶0197) of a first conductivity type (N-type) having a front surface (24) and a back surface (25);
an Insulated Gate Bipolar Transistor (IGBT) (e.g., IGBT 9) (Aketa, Fig. 13, ¶0133-¶0144, ¶0197-¶0200) formed on the semiconductor substrate (23) of the first region (e.g., an IGBT region including gate trench 55 above the collector region 37);
a diode (e.g., pn-diode 10) (Aketa, Fig. 13, ¶0146-¶0147, ¶0197-¶0200) formed on the semiconductor substrate (23) of the second region (e.g., a diode region 10 above the cathode region 33/32);
a base region (39) (Aketa, Fig. 13, ¶0136, ¶0197-¶0200) of a second conductivity type (e.g., p-type) opposite to the first conductivity type (e.g., n-type) formed on the semiconductor substrate (23) of the first region;
a trench (e.g., gate trench 55) (Aketa, Fig. 13, ¶0198-¶0199) formed on the semiconductor substrate (23) in the first region so that a bottom portion thereof is positioned below the base region (39);
a gate insulating film (56) (Aketa, Fig. 13, ¶0199) formed inside of the trench (55);
a gate electrode (e.g., 57) (Aketa, Fig. 13, ¶0199) formed on the gate insulating film (56) so as to fill the inside of the trench (55);
an emitter region (41) (Aketa, Fig. 13, ¶0137, ¶0197-¶0200) of the first conductivity type (e.g., n-type) formed in the base region (39), the emitter region (41) being in contact with the trench (55);
a collector region (37) (Aketa, Fig. 13, ¶0133, ¶0197-¶0200) of the second conductivity type (e.g., p-type) formed on a back surface side of the semiconductor substrate (23);
an anode region (39/43) (Aketa, Fig. 13, ¶0146, ¶0197-¶0200) of the second conductivity type (e.g., p-type) formed on the semiconductor substrate (23) at a front surface side (e.g., anode side) in the second region (e.g., above the cathode region 33/32), the anode region (39) being in contact with the trench (55);
a cathode region (33/32) (Aketa, Fig. 13, ¶0146, ¶0197-¶0200) of the first conductivity type (e.g., n-type) formed on the semiconductor substrate (23) at the back surface side (e.g., cathode side) in the second region;
an interlayer insulating film (46) (Aketa, Fig. 13, ¶0140, ¶0197-¶0200) formed on the front surface of the semiconductor substrate (23) in the first region (e.g., the IGBT region including gate trench 55 above the collector region 37) and the second region (e.g., above the cathode region 33/32);
an emitter electrode (26) (Aketa, Fig. 13, ¶0142, ¶0197-¶0200) formed on the interlayer insulating film (46); and
a collector electrode (27) (Aketa, Fig. 13, ¶0143-¶0144, ¶0197-¶0200) formed on the back surface of the semiconductor substrate (23) in the first region (e.g., above the collector region 37) and the second region (e.g., above the cathode region 33/32),
wherein a thickness of the semiconductor substrate (23) (Aketa, Fig. 13, ¶0143-¶0144, ¶0197-¶0200) in the first region (e.g., above the collector region 37) is thinner than a thickness of the semiconductor substrate (23) in the second region (e.g., above the cathode region 33/32),
wherein a step (e.g., trenches 36 are dry-etches on the bottom surface 25 of the substrate 23 to form a step corresponding to a sidewall of the trench 36 between a bottom surface of the trench 36 and the bottom surface 25 of the substrate 23) (Aketa, Fig. 13, ¶0150-¶0151, ¶0197-¶0200) is formed on the back surface (25) of the semiconductor substrate (23) so that the back surface (e.g., corresponding to the bottom surface of the trench 36) of the semiconductor substrate (23) in the first region (e.g., above the collector region 37) is positioned above the back surface (25) of the semiconductor in the second region (e.g., above the cathode region 33/32), and
wherein the step (e.g., corresponding to a sidewall of the trench 36) is located under the trench (55).
Further, Aketa does not specifically disclose (1) a gate wiring formed on the interlayer insulating film, (2) wherein a thickness of the semiconductor substrate in the first region is in a range of 1μm or more and 10μm or less.
Regarding (1), Naito teaches forming a semiconductor device (Naito, Figs. 1a-1d, ¶0006, ¶0094-¶0158) with improved turn-off withstand capabilities, wherein the first region (70) (Naito, Figs. 1a-1d, ¶0094, ¶0111-¶0117, ¶0147, ¶0201-¶0202) includes an IGBT transistor provided with gate trenches (40) connected to the gate metal layer (50) formed on the interlayer insulating film (38), and the second region (80) (Naito, Figs. 1a-1d, ¶0094, ¶0113, ¶0136-¶0145, ¶0158) includes a diode portion, and a cathode region (83) extending to the edge termination structure (90) (Naito, Figs. 1a-1d, ¶0094- ¶00097) surrounding the active region (120) including the first region (70) and the second region (80), wherein the gate metal layer (50) surrounds the active region (120) and connected to the gate pad (116) provided in the edge termination structure (90) to supply a gate voltage to the transistor portion of the first region (70), and the edge termination structure (90) relaxes electric field concentration on the upper surface of the semiconductor substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Aketa by forming an IGBT transistor including a gate structure connected to gate metal layer surrounding the active region including the IGBT transistor as taught by Naito to have the semiconductor device, comprising: a gate wiring formed on the interlayer insulating film, in order to supply a gate voltage to the transistor portion surrounded by the edge termination structure to provide a semiconductor device with improved turn-off withstand capabilities (Naito, ¶0006, ¶0094-¶0097, ¶0158).
Regarding (2), Chen teaches forming an IGBT semiconductor device (Chen, Figs. 1L, 2L, ¶0009, ¶0017-¶0033) comprising trenches (40) (Chen, Figs. 1L, 2L, ¶0020, ¶0027, ¶0033) on a back surface of the substrate (10) and having a depth of 1μm or more, to suppress occurrence of parasitic Zener diode, and to enhance performance of the IGBT device.
Further, Chen teaches that a thickness of the substrate depends on desired voltage tolerance of the IGBT (Chen, Figs. 1L, 2L, ¶0027).
Thus, Chen recognizes that a thickness of the substrate and a depth of the backside trenches impact a desired voltage tolerance and performance of the IGBT device. Thus, a thickness of the substrate and a depth of the backside trenches are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a thickness of the substrate and a depth of the backside trenches as Chen has identified a thickness of the substrate and a depth of the backside trenches result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific thickness of the semiconductor substrate in the first region that is thinner than a thickness of the semiconductor substrate in the second region within a range of 1μm or more and 10μm or less, in order to suppress occurrence of parasitic Zener diode, and to enhance performance of the IGBT device as taught by Chen (¶0009, ¶0020, ¶0027, ¶0033) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Aketa by optimizing a thickness of the substrate and a depth of trenches formed on a backside of the substrate in the IGBT region as taught by Chen to have the semiconductor device, wherein a thickness of the semiconductor substrate in the first region is thinner than a thickness in the semiconductor substrate of the second region and is within a range of 1μm or more and 10μm or less, in order to suppress occurrence of parasitic Zener diode, and to enhance performance of the IGBT device (Chen, ¶0009, ¶0020, ¶0027, ¶0033).
Regarding claim 4, Aketa in view of Naito and Chen discloses the semiconductor device according to claim 1. Further, Aketa discloses the semiconductor device, wherein the base region (39) (Aketa, Fig. 13, ¶0136-¶0146, ¶0197-¶0200), the emitter region (41) and the anode region (39/43) are electrically connected to the emitter electrode (26), and wherein the collector region (37) and the cathode region (33/32) are electrically connected to the collector electrode (27), but does not specifically disclose that the gate electrode is electrically connected to the gate wiring.
However, Naito teaches forming the gate metal layer (50) (Naito, Figs. 1a-1d, ¶0098, ¶0101, ¶0117-¶0118, ¶0158) on the interlayer insulating film (38), and connected to the gate electrode (44) inside the gate trenches (40) through the gate runner (48), wherein the gate metal layer (50) surrounds the active region (120) and connected to the gate pad (116) provided in the edge termination structure (90) to supply a gate voltage to the transistor portion of the first region (70).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Aketa/Naito/Chen by forming an IGBT transistor including a gate structure inside the gate trenches and connected to gate metal layer as taught by Naito to have the semiconductor device, wherein the gate electrode is electrically connected to the gate wiring, in order to supply a gate voltage to the transistor portion surrounded by the edge termination structure to provide a semiconductor device with improved turn-off withstand capabilities (Naito, ¶0006, ¶0094-¶0097, ¶0158).
Regarding claim 6, Aketa in view of Naito and Chen discloses a semiconductor device according to claim 4. Further, Aketa does not specifically disclose an outer peripheral region surrounding the first region and the second region in a plan view, wherein the cathode region is also formed on the semiconductor substrate in the outer peripheral region at the back surface side, and wherein a thickness of the semiconductor substrate in the first region is thinner than a thickness of the semiconductor substrate in the outer peripheral region.
However, Naito teaches forming an outer peripheral region (e.g., the edge termination structure (90) (Naito, Figs. 1a-1d, ¶0094- ¶00097) surrounding the first region (70) and the second region (80) in a plan view, to relax the electric field concentration on the upper surface of the semiconductor substrate, wherein the cathode region (83) (Naito, Figs. 1a-1d, ¶0113, ¶0136-¶0145, ¶0158) is also formed on the semiconductor substrate in the outer peripheral region at the back surface side, to improve turn-off withstand capabilities of the semiconductor device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Aketa/Naito/Chen by forming the edge termination structure including a cathode region as taught by Naito to have the semiconductor device, further comprising an outer peripheral region surrounding the first region and the second region in a plan view, wherein the cathode region is also formed on the semiconductor substrate in the outer peripheral region at the back surface side, and wherein a thickness of the semiconductor substrate in the first region is thinner than a thickness of the semiconductor substrate in the outer peripheral region, in order to provide a semiconductor device with improved turn-off withstand capabilities (Naito, ¶0006, ¶0094-¶0097, ¶0158).
Regarding claim 7, Aketa in view of Naito and Chen discloses the semiconductor device according to claim 4. Further, Aketa discloses the semiconductor device, wherein the base region (39) (Aketa, Fig. 13, ¶0136, ¶0197-¶0200) is also formed on the semiconductor substrate (23) of the second region (e.g., above the cathode region 32/33), wherein the anode region (39/43) is formed on the base region of the second region, and wherein a distance between the base region (39, under the emitter region 41 adjacent the trench 55) of the first region and the collector region (37) of the first region is shorter than a distance between the base region (39, adjacent the P+ contact region 43) of the second region and the cathode region (32) of the second region.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148369 to Aketa in view of Naito (US 2019/0288060) and Chen (US 2015/0279980) as applied to claim 4, and further in view of Muzukami (US 2019/0081163).
Regarding claim 5, Aketa in view of Naito and Chen discloses the semiconductor device according to claim 4. Further, Aketa does not specifically disclose the semiconductor device, further comprising a hole injection region of the second conductivity type, wherein the hole injection region is formed in the semiconductor substrate of the second region at the back surface side so as to be in contact with the cathode region.
However, Muzukami teaches forming a semiconductor device (Muzukami, Fig. 2, ¶0014-¶0024, ¶0027-¶0050) comprising an IGBT region (1) and a diode region (2) including a hole injection region (24) (Muzukami, Fig. 2, ¶0038, ¶0046-¶0055) of the second conductivity type (p-type), wherein the hole injection region (24) is formed in the semiconductor substrate (10) of the second region (2) at the back surface side (10b) so as to be in contact with the cathode region (22), to reduce the peak surge voltage at the recovery state, and to reduce the switching loss.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Aketa/Naito/Chen by forming the carrier injection layer as taught by Muzukami to have the semiconductor device, further comprising a hole injection region of the second conductivity type, wherein the hole injection region is formed in the semiconductor substrate of the second region at the back surface side so as to be in contact with the cathode region, in order to reduce the peak surge voltage at the recovery state, and to reduce the switching loss (Muzukami, ¶0038, ¶0054-¶0055).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 4-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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