DETAILED ACTION
This Office Action is in response to RCE filed November 17, 2025.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
On lines 5-8, “a plurality of confinement layers and a plurality of barrier layers alternately stacked in direct contact with each other, without any layer interposed therebetween” should be amended, because while the phrases “alternately stacked in direct contact with each other” and “without any layer interposed therebetween” should refer to a configuration of two neighboring sublayers, Applicants claim as if all of the plurality of barrier layers and all of the plurality of confinement layers were alternately stacked, and there was no layer interposed between all of the plurality of barrier layers and all of the plurality of confinement layers.
On lines 8 and 9, the “plurality” should be delineated such as “plurality of confinement layers” and “plurality of barrier layers”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 7, it is not clear what “the content of indium” and “the content of gallium” refer to, because (a) by amending claim 1, Applicants do not claim “a content of indium” and “a content of gallium” in claim 1 or claim 7, (b) therefore, the limitations “the content of indium” and “the content of gallium” lack the antecedent bases, and (c) also, the previously claimed “a content of indium” and “a content of gallium” were indefinite as the Examiner stated in the Final Office Action mailed November 17, 2025, i.e. “it is not clear what the limitation “a content of indium is greater than a content of gallium in the first oxide semiconductor material so that the first oxide semiconductor material has a larger work function than the second oxide semiconductor material” recited on lines 9-11 suggests, because (a) the work function of a semiconductor material would vary depending on whether the semiconductor material is intrinsic, an n-type or a p-type, which Applicants do not claim in claim 1, (b) also, even for the same conductivity type semiconductor materials, the work function would vary depending on how heavily or lightly the semiconductor materials are doped even though the semiconductor materials have the same material composition due to different locations of the Fermi level for the semiconductor materials with different doping concentrations, which Applicants do not claim in claim 1, (c) in addition, while Applicants claim the material composition of the first oxide semiconductor material, Applicants do not claim the material composition of the second oxide semiconductor material, (d) furthermore, as shown in Fig. 2 of current application, when the first and second oxide semiconductor materials are stacked with each other, the work function of the first and second oxide semiconductor materials would be the same since the work function of the first and second oxide semiconductor materials is the difference between the vacuum energy level and the dotted Fermi level, and the Fermi level is aligned for the first and second oxide semiconductor materials, (e) therefore, it is not clear whether the limitation “a content of indium is greater than a content of gallium in the first oxide semiconductor material so that the first oxide semiconductor material has a larger work function than the second oxide semiconductor material” recited on lines 9-11 suggests that the relative content of the indium and gallium in the first and second oxide semiconductor materials is the only determining factor of the claimed relative work functions, i.e. it is not clear whether the limitation cited above would be true regardless of the conductivity types and doping concentrations of the first and second oxide semiconductor materials as long as the limitation directed to the contents of indium and gallium in the first oxide semiconductor material is met, and (f) it is not clear when and how the claimed different work functions are measured since in the claimed thin-film transistor, the first and second oxide semiconductor materials would have an identical work function rather than different work functions due to the alignment of the Fermi levels of the first and second oxide semiconductor materials.”
(2) Regarding claim 8, it is not clear whether “multiple layers alternately stacked at least twice” recited on line 2 refer to “a plurality of confinement layers and a plurality of barrier layers” recited on lines 5-6 of the amended claim 1, because (a) while claim 1 was amended, claim 8 has not been amended, and therefore, it is not clear whether the “multiple layers alternately stacked at least twice” refer to “a plurality of confinement layers and a plurality of barrier layers”, or the “multiple layers alternately stacked at least twice” can refer to “a stack structure” that includes “a plurality of confinement layers and a plurality of barrier layers” and additional layer(s), and (b) in this case, it is not clear whether “the first oxide semiconductor material of one layer” recited on lines 2-3 of claim 8 refers to the bottommost or topmost confinement layer out of “a plurality of confinement layers” recited on line 5-6, or the “one layer” does not have to be a confinement layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Severing (“A new concept for quasi-superlattice-based transistors,” Electronics (2015)).
Regarding claims 1, 5 and 8, Severing discloses a thin-film transistor (first line on page 1) comprising: a gate electrode (Gate in drawing); a gate insulating layer (AlOx or composite layer of ZrO2 and AlOx); and an active layer (QSL) insulated from the gate electrode by the gate insulating layer, wherein the active layer includes a stack structure (QSL) including a plurality of confinement layers (In2O3 layers on lines 2-3 on second page) and a plurality of barrier layers (Ga2O3 layers on lines 2-3 on second page) alternately stacked in direct contact with each other, because (a) the In2O3 layers and Ga2O3 layers are alternately stacked together with the ZnO layers, and (b) the In2O3 layers and Ga2O3 layers are in direct contact with each other, without any layer interposed therebetween, because (a) the preposition “therebetween” does not necessarily suggest “between” one layer in one level and another layer in the next level, (b) there is no intervening layer between an In2O3 layer and a Ga2O3 layer in a unit, and (c) Applicants do not claim that there is no intervening layer between a barrier layer in one level of the stacked structure and a confinement layer in the next level of the stack structure, each confinement layer of the plurality including a first oxide semiconductor layer (Ga2O3) and each barrier layer of the plurality including a second oxide semiconductor material (In2O3), the second oxide semiconductor material inherently having a larger bandgap than the first oxide semiconductor material, because (a) gallium atoms are smaller than indium atoms, and (b) therefore, gallium oxide has a larger bandgap than indium oxide, which is very conductive (claim 1), the second oxide semiconductor material (Ga2O3) includes a gallium oxide (claim 5), and among multiple layers alternately stacked at least twice, the first oxide semiconductor material of one layer (one of In2O3 layers) is in contact with the gate insulating layer (composite layer of ZrO2 and AlOx) (claim 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubayashi et al. (US 10,074,748)
Regarding claim 1, Matsubayashi et al. disclose a thin-film transistor (Figs. 1 and 2A) comprising: a gate electrode (170) (col. 7, lines 22-23); a gate insulating layer (160) (col. 7, line 20); and an active layer (130) (col. 7, lines 15-16) insulated from the gate electrode by the gate insulating layer, wherein the active layer includes a stack structure (131/132/133) (col. 7, lines 56-58) including a confinement layer (132), see Fig. 2A, and a plurality of barrier layers (131 and 133), see Fig. 2A, the confinement layer including a first oxide semiconductor and each barrier of the plurality including a second oxide semiconductor material, the second oxide semiconductor material having a larger bandgap than the first oxide semiconductor material, see Fig. 2A.
Matsubayashi et al. differ from the claimed invention by not showing that the stack structure includes a plurality of confinement layers and the plurality of barrier layers alternately stacked in direct contact with each other, without any layer interposed therebetween, each confinement layer of the plurality including a first oxide semiconductor layer and each barrier layer of the plurality including a second oxide semiconductor material.
(A) Matsubayashi et al. further disclose that “Although the case where the oxide semiconductor stack 130 is a stack of three layers is described in this embodiment, the oxide semiconductor stack 130 may be a single layer or a stack of two layers or four or more layers (emphasis added)” on lines 3-6 of column 8, and that “In the case of four or more layers, for example, the second oxide semiconductor layer 132 is provided between layers each corresponding to the first oxide semiconductor layer 131 or the third oxide semiconductor layer 133 as described in this embodiment” on lines 21-25 of column 8.
(B) In addition, Matsubayashi et al. further disclose that “For example, when EcS1 is equal to EcS3, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:6:4, or 1:9:6 can be used for the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1 or 3:1:2 can be used for the second oxide semiconductor layer 132” on lines 54-60 of column 12.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the stack structure of the active layer can include a plurality of confinement layers and a plurality of barrier layers alternately stacked in direct contact with each other, without any layer interposed therebetween, each confinement layer of the plurality including a first oxide semiconductor layer and each barrier layer of the plurality including a second oxide semiconductor material, because (a) as at least implicitly suggested by Matsubayashi et al., the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are or can be formed of the same material composition with each atomic ratio of In to Ga and Zn is 1:3:2, 1:6:4, or 1:9:6, (b) as disclosed by Matsubayashi et al., “In the case of four or more layers, for example, the second oxide semiconductor layer 132 is provided between layers each corresponding to the first oxide semiconductor layer 131 or the third oxide semiconductor layer 133 as described in this embodiment”, which suggests that the stack structure would be (i) 131/132/(133=131)/131 or 131/132/(133=131)/132 when there are four layers, (ii) 131/132/(133=131)/131/132 or 131/132/(133=131)/132/(133=131) when there are five layers, (iii) 131/132/(133=131)/131/132/(133=131) or 131/132/(133=131)/132/(133=131)/132, and so on since, when the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are formed of an identical material composition, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that either the first and third oxide semiconductor layer are formed repeatedly or the third oxide semiconductor layer would be considered corresponding to the first oxide semiconductor layer, and (c) in either case, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the stack structure of the active layer can include a plurality of confinement layers and a plurality of barrier layers alternately stacked in direct contact with each other, without any layer interposed therebetween since (i) if the first and third oxide semiconductor layer are formed separately, the composite layer of the first and third oxide semiconductor layer 131+133 = 2 × 131 or 2 × 133 would correspond to a single thicker oxide semiconductor layer having the same material composition with the first and third oxide semiconductor layer, and the thicker first/third oxide semiconductor layer would correspond to the claimed barrier layer, while the second oxide semiconductor layer would correspond to the claimed confinement layer, and (ii) if the first and third oxide semiconductor layer are considered the same or equal, and thus a pair of the first and second oxide semiconductor layer are alternately and repeatedly formed, the first or third oxide semiconductor layer corresponds to the claimed barrier layer and the second oxide semiconductor layer corresponds to the claimed confinement layer.
In this case, each confinement layer of the plurality includes a first oxide semiconductor layer and each barrier layer of the plurality includes a second oxide semiconductor material disclosed on lines 54-60 of column 12, and the second oxide semiconductor material having a larger bandgap than the first oxide semiconductor material as shown in Fig. 2A of Matsubayashi et al.
Regarding claims 5 and 8, Matsubayashi et al. further disclose that the second oxide semiconductor material (material of 132) includes a gallium oxide, because (a) as disclosed by Matsubayashi et al., “an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1 or 3:1:2 can be used for the second oxide semiconductor layer 132”, and (b) therefore, the second oxide semiconductor material formed of InGaZnO includes a gallium oxide inside InGaZnO since the transitional phrase “includes” does not preclude presence of another material or other materials such as indium oxide and zinc oxide (claim 5), and among multiple layers alternately stacked at least twice, the first oxide semiconductor material of one layer (topmost third oxide semiconductor layer 133, which has the same material composition with first oxide semiconductor layer 131 in Fig. 2A) is in contact with the gate insulating layer (160) (claim 8).
Regarding claims 9 and 10, Matsubayashi et al. differ from the claimed invention by not showing that a thickness of the first oxide semiconductor material is the same as a thickness of the second oxide semiconductor material (claim 9), and thicknesses of the first oxide semiconductor material and the second oxide semiconductor material are in a range from 2 nm or more and 5 nm or less (claim 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a thickness of the first oxide semiconductor material can be the same as a thickness of the second oxide semiconductor material, and thicknesses of the first oxide semiconductor material and the second oxide semiconductor material can be in a range from 2 nm or more and 5 nm or less, because (a) the thicknesses of the first and second oxide semiconductor layer should respectively be controlled and optimized to obtain desired electrical and optical characteristics of the thin-film transistor, (b) a repetitive structure such as a superlattice structure has been commonly formed in manufacturing semiconductor devices due to their ease and simplicity of manufacturing, and thus their low cost of manufacturing, and (c) the thicknesses of the first and second oxide semiconductor material can be in the claimed ranges recited in claim 10 since the thicknesses of the first and second oxide semiconductor materials should also be controlled and optimized considering an overall thickness of the semiconductor device including the claimed thin-film transistor.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Severing (“A new concept for quasi-superlattice-based transistors,” Electronics (2015)). The teachings of Severing are discussed above.
Regarding claims 9 and 10, Severing differs from the claimed invention by not showing that a thickness of the first oxide semiconductor material is the same as a thickness of the second oxide semiconductor material (claim 9), and thicknesses of the first oxide semiconductor material and the second oxide semiconductor material are in a range from 2 nm or more and 5 nm or less (claim 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a thickness of the first oxide semiconductor material can be the same as a thickness of the second oxide semiconductor material, and thicknesses of the first oxide semiconductor material and the second oxide semiconductor material can be in a range from 2 nm or more and 5 nm or less, because (a) the thicknesses of the first and second oxide semiconductor layer should respectively be controlled and optimized to obtain desired electrical and optical characteristics of the thin-film transistor, (b) a repetitive structure such as a superlattice structure has been commonly formed in manufacturing semiconductor devices due to their ease and simplicity of manufacturing, and thus their low cost of manufacturing, and (c) the thicknesses of the first and second oxide semiconductor material can be in the claimed ranges recited in claim 10 since the thicknesses of the first and second oxide semiconductor materials should also be controlled and optimized considering an overall thickness of the semiconductor device including the claimed thin-film transistor.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamazaki (US 10,096,628)
Takahashi et al. (US 9,478,668)
Umeda et al. (US 8,343,800)
Shih et al. (US 10,636,916)
Takata et al. (US 8,692,252)
Huang et al. (US 11,527,649)
Huang et al. (US 11,908,936)
Yamazaki et al. (US 10,916,663)
Liu et al. (US 2021/0126024)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 April 13, 2026
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